TWI575537B - Flash memory and method for improving reliability of the same - Google Patents

Description

Flash memory and method for improving the reliability of flash memory

The present invention relates to flash memory, and more particularly to methods for improving the reliability of flash memory.

Flash memory is a memory that allows multiple writes or reads during operation. It can be used to transfer or exchange stored data between electronic devices, such as memory cards and portable hard disk applications. Flash memory is also a very important and widely used technology in the field of non-volatile solid-state storage. Because flash memory is a non-volatile memory, flash memory does not need to store data. Power consumption, this is the advantage of flash memory.

The gate structure of the transistor used in the flash memory has a control gate and a floating gate, and the floating gate is between the gate of the control gate and the transistor, and is used through the floating gate. The flash memory can perform three basic operation modes of reading, writing, and erasing. In some applications, when the floating gate is injected with charge, the bit stored in the flash memory is "0". In contrast, when the charge is removed from the floating gate, the bit is "1". The flash memory is the principle of repeatedly injecting and reading the charge by injecting or removing the charge onto the floating gate.

In some practical applications, the test process of the flash memory write action is affected by the test temperature and the trapping phenomenon. The test result is misjudged by the amount of charge stored in the floating gate, which causes the test result to be wrong, which leads to a decrease in the manufacturing yield of the flash memory.

In view of the above, the present invention provides a flash memory and a method of improving the reliability of a flash memory to overcome the aforementioned problems.

The invention provides a method for improving the reliability of a flash memory, the flash memory comprising a word line, a bit line, a reference level line and a flash memory unit composed of a transistor, the electric The crystal has a gate structure connected to the word line, a first source/drain connected to the bit line, and a second source/drain connected to the reference line. The method includes applying a first turn-on voltage, a first voltage, and a second voltage to the gate structure through the word line, the bit line, and the reference level line during a writing period, respectively. a source/drain and a second source/drain to perform a write operation on the flash memory cell; during the test period after the write period, the word line, the bit line, and the reference level are transmitted through the word line a second opening voltage, a third voltage and a fourth voltage are respectively applied to the gate structure, the first source/drain and the second source/drain to perform a test action, wherein the test action is a test Writing data of the flash memory unit during the writing; wherein the first turn-on voltage is greater than the second turn-on voltage, the first voltage is greater than the second voltage, and the fourth voltage is greater than the third voltage.

The method for improving the reliability of the flash memory, wherein the flash memory unit generates a test current during the test, and the method further comprises when the current amount of the test current is lower than a first predetermined current amount. Ending the test action; and re-executing the write action when the current amount of the test current is higher than the first predetermined current amount.

The present invention provides a flash memory comprising at least one voltage control circuit; at least one word line coupled to a voltage control circuit; at least one bit line coupled to the voltage control circuit; at least one reference level line And coupling the voltage control circuit; and at least one flash memory unit. The flash memory unit includes a transistor, a gate structure of the transistor is coupled to the word line, a first source/drain of the transistor is coupled to the bit line, and a second source of the transistor And the drain electrode is coupled to the reference level line; wherein, during a writing period, the voltage control circuit provides a first turn-on voltage through the word line to the gate structure, and provides a first voltage through the bit line Providing a second voltage to the second source/drain through the first source/drain and through the reference level to perform a write operation on the flash memory unit; wherein, the write operation During a test period after the execution, the voltage control circuit provides a second turn-on voltage to the gate structure through the word line, provides a third voltage to the first source/drain through the bit line, and transmits the reference through the bit line. The level line provides a fourth voltage to the second source/drain to perform a test action for testing data written to the flash memory cell during the writing; wherein the first turn-on voltage Greater than the second turn-on voltage, the first voltage is greater than the second , And the fourth voltage is greater than the third voltage.

The flash memory as described above and the method for improving the reliability of the flash memory, wherein the gate structure of the transistor has a control gate and a floating gate.

100‧‧‧Optoelectronics

101‧‧‧ gate structure

101a‧‧‧Control gate

101b‧‧‧Oxide layer

101c‧‧‧Float

101d‧‧‧Oxide layer

102‧‧‧First source/bungee

103‧‧‧Second source/bungee

104‧‧‧P type substrate

106, 107‧‧‧ plural negative charges

200‧‧‧Flash memory block

201‧‧‧Voltage controller

203‧‧‧Control gate

204‧‧‧First source/bungee

205‧‧‧Second source/bungee

M ₁ ‧‧‧flash memory unit

B ₀ , B ₁ ‧‧‧ bit line

W ₀ ‧‧‧ character line

SL‧‧‧ reference level

300‧‧‧Anti-gate flash memory block

M ₁₁ -M ₁₃ , M ₂₁ -M ₂₃ ‧‧‧Switching elements

S ₁₁ -S ₂₃ ‧‧‧ gate

M ₁₄ , M ₂₄ ‧‧‧ reverse or gate flash memory unit

301‧‧‧Voltage controller

303‧‧‧Control gate

304‧‧‧First source/bungee

305‧‧‧Second source/bungee

I _w ‧‧‧write current

I _t ‧‧‧Test current

400‧‧‧ Flowchart

401-404‧‧‧Steps

1A is a schematic diagram of a transistor of a flash memory in accordance with an embodiment of the present invention.

1B is a transistor of a flash memory according to an embodiment of the invention Schematic diagram.

2A is a schematic diagram of a write operation of a flash memory according to an embodiment of the present invention.

2B is a schematic diagram of a test operation of a flash memory according to an embodiment of the present invention.

3A is a schematic diagram of a write operation of an anti-gate flash memory according to an embodiment of the present invention.

FIG. 3B is a schematic diagram showing the test action of the anti-gate flash memory according to an embodiment of the present invention.

4 is a flow chart of a method for improving the reliability of a flash memory in accordance with an embodiment of the present invention.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

1A is a schematic diagram of a transistor 100 of a flash memory in accordance with one embodiment of the present invention. The transistor 100 includes a gate structure 101, a first source/drain 102, and a second source/drain 103. The gate structure 101 is formed on the P-type substrate 104 and has a control gate 101a, a floating gate 101c, and oxide layers 101b and 101d. The first and second source/drain electrodes 102, 103 are formed of N-type doped regions and are disposed in the P-type substrate 104 on both sides of the gate structure 101. In the gate structure 101, the control gate 101a and the floating gate 101c are electrically isolated by an oxide layer 101b, and an oxide layer 101d is provided between the floating gate 101c and the P-type substrate 104.

In this embodiment, the flash memory is executed during a write period. In a write operation, the control gate 101a of the transistor 100 is connected to a first turn-on voltage; the first source/drain 102 is connected to a first voltage; and the second source/drain 103 is connected to a second voltage, in this embodiment. The first voltage is greater than the second voltage. In some embodiments, the first turn-on voltage can be 9 volts; the first voltage can be 4 volts; and the second voltage can be 0 volts, although the invention is not limited thereto.

Since the first voltage is greater than the second voltage, the voltage applied to the control gate 101a, the first source/drain 102, and the second source/drain 103 may cause hot electrons to be injected into the floating gate 101c. Crystal 100 will have a threshold voltage corresponding to the charge in floating gate 101c. At the same time, due to the occurrence of the charge trapping phenomenon, the oxide layer 101d also has a complex negative charge 107, and the complex negative charge 107 mainly shields the electric field between the partial control gate 101a and the second source/drain 103 (ie, mainly shields The first source/drain 102, the lower voltage of the second source/drain 103, and the electric field between the control gates 101a, thereby affecting the threshold voltage. Wherein, the complex negative charge 107 in the oxide layer 101d is affected by the ambient temperature. For example, after a high temperature test, the plurality of negative charges 107 may partially escape or be removed from the oxide layer 101d.

In this embodiment, during a test after the execution of the write operation, the flash memory further performs a test action to test whether the write action has been completed. Applying a voltage to the control gate 101a, the first source/drain 102, and the second source/drain 103 to detect a test current between the first source/drain 102 and the second source/drain 103 Whether it is less than a predetermined current amount, if the test current is less than the predetermined current amount, the writing action is completed.

According to the conventional operation mode, the conventional test operation connects the control gate 101a to a second turn-on voltage; the first source/drain 102 is connected to a third voltage; And the second source/drain 103 is connected to a fourth voltage, wherein the third voltage is greater than the fourth voltage and the first turn-on voltage is greater than the second turn-on voltage, that is, in a previous test operation, the first source The voltage magnitude relationship of the /drain 102 and the second source/drain 103 is the same as the write operation. The above conventional operation mode makes the threshold voltage of the transistor 100 significantly affected by the complex negative charge 107 (as in the foregoing phenomenon, the complex negative charge 107 mainly shields the first source/drain 102, the second source/drain 103 The lower intermediate voltage and the electric field between the control gates 101a cause the transistor 100 to undergo a significant change in the threshold voltage of the transistor 100 after the previous test operation is completed and further subjected to the high temperature test. This phenomenon may cause a read error in the cache memory. For example, when the previous test action has detected that the test current is less than the predetermined current amount, that is, the write operation has been completed, the read value of the cache memory should be “0”, but further After the high temperature test, the threshold voltage of the transistor 100 decreases due to the decrease of the complex negative charge 107, causing the current of the transistor 100 to conduct between the first source/drain 102 and the second source/drain 103 to be greater than the expected current. The amount causes the read value of the cache to become "1", thus causing a read error.

In this embodiment, the test operation is to connect the control gate 101a of the transistor 100 to a second turn-on voltage; the first source/drain 102 is connected to a third voltage; and the second source/drain 103 is connected to the first The fourth voltage is greater than the third voltage, and the first turn-on voltage is greater than the second turn-on voltage. In some embodiments, the second turn-on voltage can be 6 volts; the third voltage can be 0 volts; and the fourth voltage can be 1 volt, but the invention is not limited thereto.

Since the fourth voltage of the embodiment is greater than the third voltage, that is, the voltages of the first source/drain 102 and the second source/drain 103 of the test action are large. The small relationship is opposite to the write operation, so the threshold voltage of the transistor 100 is significantly less affected by the complex negative charge 107. Therefore, the test action of the embodiment is more resistant to the complex negative charge 107 than the previous test action. The impact is significantly more avoidable of reading errors.

2A a schematic view showing a first embodiment of one of a flash memory block 200 flash memory unit M ₁ one embodiment of a write operation of the present invention. A flash memory can be formed by connecting a plurality of flash memory blocks 200. Flash memory block 200 comprises a voltage controller 201, flash memory unit M _1, a bit line B _0, a reference level line SL and a word line W _0, wherein the flash memory cell M ₁ is a transistor having the same structure as the aforementioned transistor 100. Flash memory block 200 of the flash memory unit M ₁ performs the write operation during a write, one of the flash memory unit M ₁ control gate word lines W ₀ through 203 coupled to the voltage controller 201 provided by the first threshold voltage; the first one of _a first voltage source flash memory unit M / drain bit line B ₀ through 204 coupled to the voltage provided by the controller 201; and a flash memory one source unit ₁ of the second M / drain 205 through the reference level line SL coupled to the voltage controller 201 provided by the second voltage, wherein the first voltage is greater than the second voltage, and the flash memory unit M ₁ generates a write current I _w . When the write operation is completed, the charge in the flash memory unit M ₁ distribution as shown in FIG. 1A, and a flash memory block 200 further perform a test operation, as shown in Figure 2B.

2B a schematic view showing in section one embodiment of a flash memory block 200 of the flash memory unit M ₁ a test operation of the embodiment of the present invention. During the test period after the writing period, the flash memory cell M ₁ of the flash memory block 200 performs the test operation, and the control gate 203 of the flash memory cell M ₁ is coupled through the word line W _{0 .} voltage provided by the controller 201 a second threshold voltage; the third one of _a first voltage source flash memory unit M / drain bit line B ₀ through 204 coupled to the voltage provided by the controller 201; and _a second one of the fourth voltage source flash memory unit M / drain 205 through the reference level line SL coupled to the voltage provided by the controller 201, wherein the fourth voltage is greater than the third voltage and the first The turn-on voltage is greater than the second turn-on voltage. The flash memory cell M ₁ generates a test current I _t .

In some embodiments, when the flash memory block 200 performs the test action, the charge distribution in the flash memory cell M ₁ is as shown in FIG. 1A, and the control gate 203 and the first generated by the test action A threshold voltage between source/drain 204 is not affected by the complex negative charge 107.

In some embodiments, when the test current I _{t is} lower than a predetermined current, the flash memory block 200 ends the test action, and when the test current I _{t is} higher than the predetermined current, the flash memory block 200 re-executes the write action.

The writing and testing operations of the flash memory block 200 can also be extended to a reverse flash memory (Nor Flash), as shown in FIGS. 3A and 3B. 3A is a diagram showing a write operation of one of the inverse or gate flash memory cells M ₁₄ in the inverse gate flash memory block 300 in accordance with one embodiment of the present invention. A reverse or gate flash memory can be formed by connecting a plurality of inverse or gate flash memory blocks 300. The inverse or gate flash memory block 300 includes a voltage controller 301, switching elements M ₁₁ M M ₁₃ and M ₂₁ ~ M ₂₃ , inverse or gate flash memory cells M ₁₄ and M ₂₄ , bit line B ₀ And B ₁ , a reference bit line SL, and a word line W ₀ , wherein the anti-gate flash memory cells M ₁₄ and M _{24 are} each a transistor having the same structure as the transistor 100 described above. NOR flash memory block 300 performs the write operation in a write period, the switching element M ₁₁ ~ M ₁₃ gate electrode of S ₁₁ ~ S ₁₃ coupled to the voltage controller 301 provides a high voltage to turn on one of the a current path of the switching elements M ₁₁ -M ₁₃ , and one of the anti-gate flash memory cells M ₁₄ controls the gate 303 coupled to the first turn-on voltage provided by the voltage controller 301 via the word line W ₀ ; One of the first source/drain 304 of the gate flash memory cell M _{14 is} coupled to the first voltage provided by the voltage controller 301 through the bit line B ₀ ; and one of the inverse or gate flash memory cells M ₁₄ The second source/drain 305 is coupled to the second voltage provided by the voltage controller 301 through the reference level line SL, wherein the first voltage is greater than the second voltage, and the anti-gate flash memory unit M _{14 is} generated. A write current I _w . When the write operation is completed, the charge distribution in the inverse or gate flash memory cell M ₁₄ is as shown in FIG. 1A, and the inverse or gate flash memory block 300 in turn performs a test action, such as FIG. 3B. Shown.

During the test after the writing period, the NOR flash memory block 300 to perform the test operation, the switching element M ₁₁ ~ M ₁₃ gate electrode of S ₁₁ ~ S ₁₃ coupled to the voltage provided by the controller 301 The high voltage is used to turn on the current path of the switching elements M ₁₁ -M ₁₃ , and the control gate 303 of the anti-gate flash memory unit M ₁₄ is coupled to the second opening provided by the voltage controller 301 via the word line W _{0 .} Voltage; the first source/drain 304 of the anti-gate flash memory cell M ₁₄ is coupled to the third voltage provided by the voltage controller 301 through the bit line B ₀ ; and the inverse or gate flash memory cell M The second source/drain 305 of ₁₄ is coupled to the fourth voltage provided by the voltage controller 301 through the reference level line SL, wherein the fourth voltage is greater than the third voltage and the first turn-on voltage is greater than the second turn-on Voltage. Wherein, the inverse or gate flash memory cell M ₁₄ generates a test current I _t .

In some embodiments, when the inverse or gate flash memory block 300 performs the test action, the charge distribution in the inverse or gate flash memory cell M ₁₄ is as shown in FIG. 1A, and the test action is generated. A threshold voltage between the control gate 303 and the first source/drain 304 is not affected by the complex negative charge 107.

When the test current I _{t is} lower than a predetermined current, the inverse or gate flash memory block 300 ends the test operation, and conversely, when the test current I _{t is} higher than the predetermined current, the inverse or gate flash memory block 300 re-executes the write action.

In some embodiments, the anti-flash memory formed by the plurality of flash memory blocks 200 or the anti-gate flash memory formed by the complex inverse or flash memory block 300 The complex reference bit lines of the gate flash memory or the flash memory are all connected to the same voltage level.

4 is a flow chart 400 of a method for improving the reliability of a flash memory in accordance with an embodiment of the present invention. In step 401, a control gate of a transistor of a flash memory cell is coupled to a first turn-on voltage; a first source/drain of the transistor is coupled to a first voltage; and the transistor is A second source/drain is coupled to a second voltage, thereby performing a write operation, wherein the first voltage is greater than the second voltage. In step 402, the control gate is coupled to a second turn-on voltage; the first source/drain is coupled to a third voltage; and the second source/drain is coupled to a fourth voltage, thereby performing a test The action generates a test current, wherein the fourth voltage is greater than the third voltage and the first turn-on voltage is greater than the second turn-on voltage. In step 403, if the test current is greater than a predetermined current amount, return to step 401; if the test current is less than the predetermined current amount, proceed to step 404. Flowchart 400 ends at step 404.

Although the present invention has been disclosed above in the preferred embodiment, it is not The scope of the present invention is defined by those skilled in the art, and modifications and modifications may be made without departing from the spirit and scope of the invention, and the scope of the invention is defined by the scope of the appended claims. Prevail.

200‧‧‧Flash memory block

201‧‧‧Voltage controller

203‧‧‧Control gate

204‧‧‧First source/bungee

205‧‧‧Second source/bungee

M ₁ ‧‧‧flash memory unit

B ₀ ‧‧‧ bit line

W ₀ ‧‧‧ character line

SL‧‧‧ reference level

I _t ‧‧‧Test current

Claims (8)

A method for improving the reliability of a flash memory, the flash memory comprising a word line, a bit line, a reference level line, and a flash memory unit composed of a transistor, the transistor having a a gate structure connecting the word line, a first source/drain connected to the bit line, and a second source/drain connected to the reference line, the method comprising: transmitting during a writing period The word line, the bit line and the reference level line respectively apply a first turn-on voltage, a first voltage and a second voltage to the gate structure, the first source/drain and the second source/drain Performing a write operation on the flash memory unit; applying a second turn-on voltage, one through the word line, the bit line, and the reference level line during a test period after the writing period a third voltage and a fourth voltage to the gate structure, the first source/drain and the second source/drain to perform a test action for writing the flash memory during the test of the write Information of the unit; wherein the first turn-on voltage is greater than the second turn-on voltage, the first voltage To the second voltage and the fourth voltage is greater than the third voltage. The method of claim 1, wherein the flash memory unit generates a test current during the test, the method further comprising: when the current of the test current is lower than a first predetermined current amount Ending the test action; and re-executing when the current amount of the test current is higher than the first predetermined current amount This write action is performed. The method of claim 1, wherein the gate structure of the transistor comprises a control gate and a floating gate. A flash memory comprising: at least one voltage control circuit; at least one word line coupled to one of the voltage control circuits; at least one bit line coupled to the voltage control circuit; at least one reference level line, coupled Connected to the voltage control circuit; and at least one flash memory unit, including a transistor, the gate structure of the transistor is coupled to the word line, and the first source/drain of the transistor is coupled to the bit line And the second source/drain of the transistor is coupled to the reference level line; wherein, during a writing period, the voltage control circuit provides a first turn-on voltage to the gate structure through the word line The bit line provides a first voltage to the first source/drain and a second voltage to the second source/drain through the reference level to perform a write to the flash memory cell The voltage control circuit provides a second turn-on voltage to the gate structure through the word line, and provides a third voltage through the bit line during the test period after the writing operation is performed. a source/drain and through the reference level Supplying a fourth voltage to the second source/drain to perform a test action for testing data written to the flash memory unit during the writing; wherein the first turn-on voltage is greater than the first The second voltage is turned on, the first voltage is greater than the second voltage, and the fourth voltage is greater than the third voltage. The flash memory unit of claim 4, wherein the flash memory unit further comprises: a second transistor, the gate structure of the second transistor is connected to the word line, the second transistor The first source/drain is coupled to a second bit line, and the second source/drain of the transistor is coupled to the reference level line; wherein the second bit line is coupled to the corresponding voltage A control circuit or a corresponding second voltage control circuit. The flash memory of claim 4 or 5, wherein the reference levels are coupled to the same voltage. The flash memory of claim 4, wherein the gate structure of the transistor has a control gate and a floating gate. The flash memory as described in claim 5 is a NOR type flash memory.