TWI574357B - Semiconductor device - Google Patents

Description

Semiconductor device

The present application has priority in the application based on Japanese Patent Application No. 2014-49743 (filing date: March 13, 2014). This application contains the entire contents of the basic application by reference to the basic application.

Embodiments of the present invention relate to a semiconductor device.

A semiconductor device in which a memory chip and a controller wafer for controlling the operation of the memory chip are mounted on a wiring substrate is known. In such a semiconductor device, it is necessary to appropriately combine, for example, a memory chip of various specifications different from the arrangement of a controller wafer and a terminal.

In other words, when the above requirements are satisfied, the difference in the arrangement of the terminals in the memory chip is a factor, and the connection structure between the terminals of the memory chip and the controller chip is complicated.

Specifically, the necessity of three-dimensionally wiring (stereoscopic wiring) between the terminals of the memory chip and the controller chip via the wiring substrate is increased, and as a result, the number of layers of the wiring substrate may have to be increased. Further, it is assumed that the situation in which the wirings of the different layers on the wiring board cross each other three-dimensionally increases, and in this case, there is a concern that the characteristics of the transmission line deteriorate.

The object of the present invention is to provide an increase in the number of substrate layers and a desired transmission line characteristic by a reasonable connection between a memory chip and a controller chip. Semiconductor device.

The semiconductor device of the embodiment includes a wiring substrate, first and second memory chips, and a controller wafer. The wiring board is formed in a rectangular shape, and has a first side portion, and a second side portion facing the first side portion, and a first relay terminal group and a second relay arranged on the first side portion side The terminal group is connected to the wiring pattern of the first relay terminal group and the second relay terminal group, and the third relay terminal group arranged on the second side. The first memory chip is formed in a rectangular shape, and has a third side portion disposed on the first side portion side, and is arranged along the third side portion and electrically connected to the first relay terminal group via a bonding wire. The first busbar terminal group on the memory side of the connection. The second memory chip is formed in a rectangular shape, and has a fourth side portion disposed on the second side portion side and arranged along the fourth side portion and electrically connected to the third relay terminal group via a bonding wire. The second busbar terminal group on the memory side of the memory connection. The controller wafer is formed in a rectangular shape, and has a fifth side portion disposed on the first side portion side, and is arranged along the fifth side portion and electrically connected to the second relay terminal group via a bonding wire. The controller-side first bus bar terminal group is disposed on the sixth side portion on the second side portion side, and is arranged along the sixth side portion and electrically connected to the third relay terminal group via a bonding wire. The second bus terminal group on the controller side. Further, the memory-side first bus bar terminal group and the controller-side first bus bar terminal group are arranged in the order of the bit number, and the directions in which the bit numbers are increased are arranged in opposite directions. Further, the memory-side second bus bar terminal group and the controller-side second bus bar terminal group are arranged in the order of the bit number, and the directions in which the bit numbers are increased are arranged in the same direction. Further, the first memory chip is provided on the wiring substrate. Further, the second memory chip is placed on the first memory chip. Further, the controller chip is placed on the second memory chip.

0a...3a...7a‧‧‧1st busbar terminal group on the controller side

0b...3b...7b, 0c...3c...7c‧‧‧ Memory side first bus terminal group

0d...3d...7d‧‧‧1st relay terminal group

0e...3e...7e‧‧‧2nd relay terminal group

8a...11a...15a‧‧‧2nd busbar terminal group on controller side

8b...11b...15b,8c...11c...15c‧‧‧Memory side second bus terminal group

8d...11d...15d‧‧‧3rd relay terminal group

8e...11e...15e‧‧‧4th relay terminal group

21, 22, 41, 42‧‧‧ memory chips (first memory chip)

21a, 22a‧‧‧ side (third side)

23, 24, 43, 44‧‧‧ memory chip (second memory chip)

23a, 24a‧‧‧ side (fourth side)

25‧‧‧ Controller chip

25a‧‧‧Border (5th side)

25b‧‧‧Border (6th side)

26, 76, 96‧‧‧ wiring substrate

26a, 76a, 96a‧‧‧ side (first side)

26b, 76b, 96b‧‧‧ side (second side)

27‧‧‧ solder balls

28, 77, 78, 98‧‧‧ sealing resin layer

30, 40, 50, 60, 70, 80, 90‧‧‧ semiconductor devices

55‧‧‧Scratch

T1‧‧‧ wiring pattern (first wiring pattern)

T2‧‧‧ wiring pattern (second wiring pattern)

W‧‧‧ bonding wire

Fig. 1 is a view showing a state in which the semiconductor device of the first embodiment is seen from the plane direction.

2 is a view showing a layout of a wiring pattern of a wiring board and a terminal group of a controller wafer included in the semiconductor device of FIG. 1 .

Fig. 3 is a perspective view showing a state in which the semiconductor device of Fig. 1 is seen from the arrow A direction.

4 is a plan view showing the configuration of a memory chip included in the semiconductor device of FIG. 1.

Fig. 5 is a view showing a state in which the semiconductor device of Comparative Example 1 is seen from the plane direction.

Fig. 6 is a view showing a state in which the semiconductor device of the second embodiment is seen from the plane direction.

Fig. 7 is a view showing an image of the logical inversion portion replacement/non-replacement bit ordering of the semiconductor device of Fig. 6.

Fig. 8 is a view showing a state in which the semiconductor device of the third embodiment is seen from the plane direction.

FIG. 9 is a view showing a layout of a wiring pattern of a wiring board provided in the semiconductor device of FIG. 8.

Fig. 10 is a perspective view showing a state in which the semiconductor device of Fig. 8 is seen from the arrow B direction.

Fig. 11 is a view showing a state in which the semiconductor device of Comparative Example 2 is seen from the plane direction.

FIG. 12 is a view showing a layout of a wiring pattern of a wiring board provided in the semiconductor device of FIG. 11.

Fig. 13 is a view showing a state in which the semiconductor device of the fourth embodiment is seen from the plane direction.

FIG. 14 is a view showing a layout of a wiring pattern of a wiring board provided in the semiconductor device of FIG.

Fig. 15 is a perspective view showing a state in which the semiconductor device of Fig. 13 is seen from the arrow C direction.

Fig. 16 is a view showing a state in which the semiconductor device of Comparative Example 3 is seen from the plane direction.

17 is a view showing a layout of a wiring pattern of a wiring board provided in the semiconductor device of FIG. 16.

Hereinafter, embodiments will be described based on the drawings.

<First embodiment>

As shown in FIG. 1 to FIG. 3, the semiconductor device 30 of the present embodiment is a semiconductor package such as an FBGA (Fine pitch Ball Grid Array), and includes a wiring substrate 26 and memory chips 21 and 22 ( The first memory chip), the memory chips 23 and 24 (the second memory chip), the controller wafer 25, the sealing resin layer 28, and the solder balls 27.

As shown in FIG. 1 and FIG. 2, the wiring board 26 is a rectangular (rectangular) printed wiring board in which a plurality of wiring patterns including a wiring pattern T1 (first wiring pattern) are formed on the surface layer or the inner layer. The wiring board 26 has a side portion 26a (first side portion) and a side portion (second side portion) 26b opposed to the side portion 26a as a pair of long sides, in addition to a pair of short sides facing each other. . The first relay terminal group 7d...3d...0d, the second relay terminal group 0e...3e...7e, and the third relay terminal group 8d are formed on one main surface (the mounting surface of the wafer) of the wiring board 26, respectively. 11d...15d.

The first relay terminal group 7d...3d...0d and the second relay terminal group 0e...3e...7e are arranged on the side of the side portion 26a of the wiring board 26, respectively. As shown in FIG. 2, the plurality of wiring patterns T1 electrically connect the first relay terminal groups 7d...3d...0d and the second relay terminal groups 0e...3e to 7e. The third relay terminal groups 8d ... 11d ... 15d are arranged on the side of the side portion 26b of the wiring board 26. Further, as shown in FIG. 3, the solder ball 27 is provided as an external connection terminal on the other main surface (the non-mounting surface of the wafer) of the wiring board 26.

As shown in FIGS. 1, 3, and 4, the memory chips 21, 22, 23, and 24 are rectangular (rectangular) nonvolatile semiconductor memory elements, for example, NAND (reverse) type flash memory chips. The memory chips 21 and 22 have one pair of short sides facing each other and one pair of long sides facing each other including the side portions 21a and 22a (third side portions). On the other hand, the memory chip 23, 24 have one pair of short sides facing each other, and one side of the opposite sides including the side portions 23a, 24a (fourth side portions).

As shown in FIG. 3, the memory chips 21, 22, 23, and 24 are attached to each other on one main surface side of the wiring board 26 via an insulating resin (not shown). In other words, the memory chips 21 and 22 as the first memory chip and the memory chips 23 and 24 as the second memory chip are mounted on the wiring substrate for each of a plurality of places (two in the present embodiment). 26 on. Further, as shown in FIGS. 1 and 3, the memory chips 21 and 22 are respectively arranged with the memory-side first busbar terminal groups 7b...3b...0b and 7c...3c along the side portions 21a and 22a thereof. 0c. On the other hand, the memory chips 23 and 24 are respectively arranged with the memory side second bus bar terminal groups 8b ... 11b ... 15b and 8c ... (11c) ... 15c along the side portions 23a, 24a.

Further, as shown in FIG. 1, the side portions 21a and 22a of the memory chips 21 and 22 are disposed on the side of the side portion 26a of the wiring board 26, respectively. On the other hand, the side portions 23a and 24a of the memory chips 23 and 24 are disposed on the side of the side portion 26b of the wiring board 26, respectively. Here, as shown in FIG. 3, the memory chips 21 and 22 as the first memory chip and the memory chips 23 and 24 as the second memory chip have the same structure (where the non-mounting surface of the wafer is set) A memory wafer of the thickness of the memory chips 21 to 24 in the case of the lower case. That is, as shown in FIG. 1, the memory chips 23 and 24 as the second memory chips are rotated 180 in the direction along the surface of the wiring substrate 26 by the memory chips 21 and 22 as the first memory chips. The state of the degree.

The memory-side first busbar terminal groups 7b...3b...0b and 7c...3c...0c of the memory chips 21 and 22 thus arranged are respectively connected to the first relay via the bonding wires W as shown in Figs. 1 and 3 The terminal groups 7d...3d...0d are electrically connected. On the other hand, the memory-side second busbar terminal groups 8b...11b...15b and 8c(11c)...15c of the memory chips 23 and 24 are respectively connected via the bonding wires W as shown in Figs. 1 and 3 3 Relay terminal groups 8d...11d...15d are electrically connected.

As shown in FIG. 1 to FIG. 3, the controller chip 25 is paired with the memory chips 21, 22, and 23, A rectangular (rectangular) semiconductor control element that controls 24 operations separately. The controller wafer 25 has a side portion 25a (the fifth side portion) and a side portion (the sixth side portion) 25b opposed to the side portion 25a as a pair, in addition to the pair of long sides facing each other. Short side. As shown in FIG. 3, the controller wafer 25 is mounted in a state of being laminated on the upper portion of the memory chip 24 via an insulating resin (not shown). Further, as shown in FIGS. 1 and 2, the side portions 25a and 25b of the controller wafer 25 are disposed on the side portions 26a and 26b of the wiring board 26, respectively. More specifically, the controller wafer 25 is mounted on the memory chip 24 at a position offset from the short side (the left side in FIG. 1) from the thickness direction (planar direction) of the wiring board 26.

Further, as shown in FIGS. 1 to 3, the controller wafer 25 includes controller-side first busbar terminal groups 0a...3a...7a and controller-side second busbar terminal groups 8a...11a...15a. The controller-side first bus bar terminal groups 0a...3a...7a are arranged along the side portion 25a, and are electrically connected to the second relay terminal groups 0e...3e...7e via the bonding wires W. On the other hand, the controller-side second bus bar terminal groups 8a...11a...15a are arranged along the side portion 25b, and are electrically connected to the third relay terminal groups 8d...11d...15d via the bonding wires W.

The bonding wire W is made of, for example, gold, silver, copper, or the like as a material. Further, for each of the above-described terminal groups formed on the controller wafer 25 and the memory chips 21, 22, 23, and 24, for example, aluminum or the like is used as a material. Further, as shown in FIG. 3, the sealing resin layer 28 is a bonding wire W together with a memory wafer (first memory chip) 21, 22, a memory chip (second memory chip) 23, 24, and a controller wafer 25. Sealed on the wiring substrate 26.

Further, as shown in FIG. 1, the semiconductor device 30 of the present embodiment mainly exemplifies the following data input/output terminals (I/O terminals), that is, I/O terminals which are I/O (data input/output) bus bars. No. 0 to 15th, the controller side first busbar terminal group 0a...3a...7a, the controller side second busbar terminal group 8a...11a...15a, and the memory side first busbar terminal Data input/output terminals (I/O terminals) such as groups 7b...3b...0b, 7c...3c...0c, and memory-side second bus terminal groups 8b...11b...15b, 8c...15c. In the semiconductor device 30 of the present embodiment, such a busbar other than the I/O bus bar is used. For example, the read enable terminal, the enable write terminal, the command lock enable terminal, the address latch enable terminal, and the like are also provided to the controller chip 25 and the memory chips 21, 22, 23, 24.

Here, a reasonable connection structure between the controller wafer 25 and the memory chips 21, 22, 23, and 24 of the semiconductor device 30 of the present embodiment will be described. As shown in FIG. 1, the semiconductor device 30 is associated with the 0th (I/O 0)~bit number 7 (I/O 7) of the I/O bus. The memory-side first busbar terminal groups 7b...3b...0b, 7c...3c...0c and the controller-side first busbar terminal groups 0a...3a...7a are arranged in the order of the bit numbers, and will be placed. The direction in which the element number is increased (the direction from the lower bit number to the upper bit number) is arranged in the opposite direction (the opposite direction).

Further, in FIG. 1, the semiconductor device 30 is associated with the eighth (I/O 8)-bit number 15 (I/O 15) of the bit number of the I/O bus. Then, the memory-side second busbar terminal groups 8b...11b...15b,8c...(11c)...15c and the controller-side second busbar terminal groups 8a...11a...15a are arranged in the order of the bit numbers, respectively. And the directions in which the bit numbers are increased are arranged in the same direction (same direction) as each other.

In this order, the controller chip 25 side and the terminal groups on the memory chips 21, 22, 23, and 24 sides are arranged, whereby the thickness direction (planar direction) of the wiring substrate 26 is as shown in FIG. 1 and FIG. It is observed that the controller wafer 25 and the terminals of the memory chips 21, 22, 23, and 24 can be electrically connected without interlacing a plurality of bonding wires W or a plurality of wiring patterns T1.

On the other hand, as shown in FIG. 5, the semiconductor device 40 of Comparative Example 1 is provided with a controller wafer 45 instead of the controller wafer 25. In the controller wafer 45, the direction in which the bit number of the controller-side first bus bar terminal group and the controller-side second bus bar terminal group increases is completely opposite to the controller chip 25. In other words, the memory-side first busbar terminal group 7b...3b...0b, 7c...3c...0c of the semiconductor device 40 of Comparative Example 1 and the controller-side first busbar terminal group 7a...3a...0a are bits. The direction in which the number is increased is arranged in the same direction as each other.

Further, as shown in FIG. 5, the memory-side second busbar terminal groups 8b...11b...15b, 8c...(11c)...15c of the semiconductor device 40 of Comparative Example 1 and the controller-side second busbar terminal group 15a... 11a...8a are arranged such that the direction in which the bit number is increased is set to be opposite to each other. As a result, as shown in FIG. 5, the controller wafer 25 and the memory wafer 21 are in a state in which the plurality of bonding wires W and the plurality of wiring patterns T1 cross each other as viewed in the thickness direction (planar direction) of the wiring substrate 26. The terminals of 22, 23, and 24 are electrically connected.

Therefore, in the semiconductor device 40 of the first comparative example, since the plurality of wiring patterns T1 are required to be three-dimensionally wired (stereoscopic wiring) in the wiring substrate 26, the number of the substrate layers is increased, and the manufacturing cost or the product is worried. Increase in size, etc. Further, at this time, since the wirings of the different layers of the wiring board 26 cross each other three-dimensionally, deterioration of the transmission line characteristics (characteristic impedance of the transmission line) or the like is caused.

On the other hand, according to the semiconductor device 30 of the present embodiment, as shown in FIGS. 1 and 2, the respective terminal groups on the controller wafer 25 side and the memory chips 21, 22, 23, and 24 sides are appropriately sorted. The arrangement is such that the controller chip can be properly connected to the memory chip, thereby suppressing an increase in the number of substrate layers and ensuring desired transmission line characteristics.

<Second embodiment>

Next, a second embodiment will be described with reference to Figs. 6 and 7 . It is noted that the same components as those in the first embodiment shown in FIG. 1 to FIG. 4 are denoted by the same reference numerals, and the description thereof will not be repeated.

In the semiconductor device 50 of the second embodiment, as shown in FIG. 6, the memory chips 41 and 42 (first memory chip) and the memory chips 43 and 44 (second memory chip) are provided instead of the semiconductor of the first embodiment. The memory chips 21 and 22 (first memory chips) and the memory chips 23 and 24 (second memory chips) shown in FIG. 1 of the device 30 are provided. Further, as shown in FIGS. 6 and 7, the semiconductor device 50 of the present embodiment further includes a register 55 that functions as a logic inversion unit.

As shown in FIG. 6, the memory chips 43 and 44 as the second memory chip are applied. The memory chips 41 and 42 which are the first memory chips are rotated by 180 degrees in the direction along the surface of the wiring board 26. Here, as shown in FIG. 6, the memory chips 41, 42, 43, and 44 are the memory-side first busbar terminal groups 0b...3b...7b, 0c...3c...7c, and the memory-side second busbar terminal. The direction in which the bit numbers of the groups 15b...11b...8b, 15c...(11c)...8c increase is completely opposite to the memory chips 21, 22, 23, 24 shown in Fig. 1.

Therefore, as shown in FIG. 5, as seen from the thickness direction (planar direction) of the wiring board 26, the controller is connected in a state in which a plurality of bonding wires W and a plurality of wiring patterns T1 cross each other. The wafer 25 is interposed between the terminals of the memory chips 41, 42, 43, and 44.

Therefore, as shown in FIGS. 6 and 7, the register 55 corresponds to at least one of the controller-side first bus bar terminal group and the controller-side second bus bar terminal group of the controller chip 25. The sort order of the bit numbers is logically inverted. In the present embodiment, the register 55 outputs, for example, a specific external signal to the controller chip 25 side, and as shown in FIG. 6, the second busbar on the controller side is connected to the first busbar terminal group and the controller side. The sort order of the bit numbers of both sides of the row terminal group is logically reversed (the sort order is reversed from 0a...3a...7a and 8a...11a...15a shown in Fig. 1 to 7a...3a as shown in Fig. 6... 0a and 15a...11a...8a).

Alternatively, the register 55 may be mounted on the controller wafer 25 itself or as a separate component from the controller wafer 25 as shown in FIG. In addition, in FIG. 6, in order to visually understand the inversion of the order of the bit numbers, the order of the symbols in FIG. 6 of the first bus bar terminal group on the controller side and the second bus bar terminal group on the controller side is displayed. This is illustrated in reverse contrast to the ordering of the symbols in Figure 1. Further, in FIG. 6, a case where the first relay terminal group 0d...3d...7d of the wiring board 26 and the second relay terminal group 7e...3e...0e are electrically connected are schematically illustrated by a broken line. The plurality of wiring patterns T1 do not cross each other.

As described above, in the semiconductor device 50 of the present embodiment, the number of the bit number 0 (the first I/O 0) to the bit number of the I/O bus bar is also 7 (the I/O 7). The memory-side first busbar terminal groups 0b...3b...7b, 0c...3c...7c and the controller-side first busbar terminal groups 7a...3a...0a are arranged in the order of the bit numbers, respectively, and The directions in which the bit numbers are increased are arranged in directions opposite to each other. Further, the second side of the memory side which is related to the eighth (I/O 8) to the bit number of the I/O bus, and the fifteenth (the first I/O 15) of the bit number. The row terminal groups 15b ... 11b ... 8b, 15c ... (11c) ... 8c and the controller side second bus bar terminal groups 15a ... 11a ... 8a are arranged in the order of the bit number, and the direction in which the bit number is increased is set to Arrange in the same direction as each other.

Therefore, according to the semiconductor device 50 of the present embodiment, the inversion function of the order of the bit numbers by the register 55 is effectively utilized, and the controller wafer 25 side and the memory chips 41, 42, 43, and 44 sides are provided. The terminal groups are appropriately arranged. Thus, as shown in FIG. 6, the controller wafer 25 and the memory chips 41, 42, 43 can be separated without crossing a plurality of bonding wires W or a plurality of wiring patterns T1. 44 terminals are electrically connected. Thereby, an increase in the number of substrate layers of the wiring substrate 26 can be suppressed, and good transmission line characteristics can be obtained.

<Third embodiment>

Next, a third embodiment will be described with reference to Figs. 8 to 10 (and Figs. 11 and 12 showing a comparative example 2). It is noted that the same components as those in the first embodiment shown in FIG. 1 to FIG. 4 are denoted by the same reference numerals, and the description thereof will not be repeated.

As shown in FIGS. 8 to 10, the semiconductor device 70 of the third embodiment includes a wiring board 76 instead of the wiring board 26 included in the semiconductor device 30 of the first embodiment. Further, the semiconductor device 70 includes the register 55 as in the second embodiment.

As shown in FIG. 8 and FIG. 9, the wiring board 76 is formed in a surface layer or an inner layer by a plurality of wiring patterns including a wiring pattern T1 (first wiring pattern) and a wiring pattern T2 (second wiring pattern). Rectangular printed wiring board. The first relay terminal group 7d...3d...0d, the second relay terminal group 7e...3e...0e, and the third relay terminal group 8d are formed on one main surface (the mounting surface of the wafer) of the wiring board 76. 11d...15d and the fourth relay terminal group 8e...11e...15e.

As shown in FIGS. 8 and 9, the first relay terminal group 7d...3d...0d and the second relay terminal group 7e...3e...0e are arranged on the side of the side portion 76a (first side portion) of the wiring board 76, respectively. The plurality of wiring patterns T1 electrically connect the first relay terminal groups 7d...3d...0d and the second relay terminal groups 7e...3e...0e. On the other hand, the third relay terminal groups 8d ... 11d ... 15d and the fourth relay terminal groups 8e ... 11e ... 15e are arranged on the side of the side portion 76b (second side portion) of the wiring board 76, respectively. The plurality of wiring patterns T2 electrically connect the third relay terminal groups 8d to 11d...15d and the fourth relay terminal groups 8e...11e to 15e.

As shown in FIG. 10, the controller wafer 25 is mounted directly above one main surface of the wiring board 76. Further, as shown in FIGS. 8 and 9, the controller wafer 25 is mounted on the central portion of the wiring substrate 76 as viewed in the thickness direction (planar direction) of the wiring substrate 26. Further, the controller-side first busbar terminal groups 7a...3a...0a of the controller wafer 25 are electrically connected to the second relay terminal groups 7e...3e...0e via the bonding wires W. On the other hand, the controller-side second bus bar terminal groups 8a...11a...15a of the controller wafer 25 are electrically connected to the fourth relay terminal groups 8e...11e...15e via the bonding wires W.

As shown in FIG. 10, the controller wafer 25 thus connected is sealed to the wiring substrate 76 together with the bonding wires W by the sealing resin layer 77. On the other hand, the memory chips 21, 22, 23, and 24 are sequentially mounted on the upper portion of the sealing resin layer 77. As shown in FIG. 10, the memory chips 21, 22, 23, and 24 are sealed together with the sealing resin layer 77 for sealing the controller wafer 25 and the bonding wires W for connecting the memory chips by the sealing resin layer 78. On the wiring substrate 76.

Here, in the present embodiment, as shown in FIGS. 8 and 9, the register 55 logically inverts the order of the bit numbers of the controller-side first bus terminal group of the controller wafer 25. The sort order is inverted from 0a...3a...7a to 7a...3a...0a) as shown in Figs. 8 and 9 .

Further, in the semiconductor device 70 of the present embodiment, as shown in FIG. 8, the memory side is provided. The first bus bar terminal group 7b...3b...0b, 7c...3c...0c and the controller side first bus bar terminal group 7a...3a...0a electrically connected to the second relay terminal group 7e...3e...0e One group and the memory side second bus bar terminal groups 8b...11b...15b,8c...11c...15c and the controller side second bus bar terminal group electrically connected to the fourth relay terminal group 8e...11e...15e In the second group of 8a...11a...15a, all of the terminal groups of the first and second groups are arranged in the order of the bit numbers, and the terminal groups of the first group and the terminal groups of the second group are respectively The direction in which the bit numbers are increased is arranged in the same direction as each other.

In this order, the controller chip 25 side and the terminal groups on the memory chips 21, 22, 23, and 24 sides are arranged, and the order of sorting the bit numbers by the register 55 is effectively utilized. As shown in FIG. 8 and FIG. 9, the controller can be connected to the thickness direction (planar direction) of the wiring board 76 without crossing a plurality of bonding wires W or a plurality of wiring patterns T1 or T2. The wafer 25 is reasonably connected to the terminals of the memory chips 21, 22, 23, 24.

On the other hand, as shown in FIG. 11 and FIG. 12, in the semiconductor device 80 of the comparative example 2 which does not have the register 55, the memory-side first busbar terminal group 7b...3b...0b, 7c...3c...0c and The first group of the controller-side first busbar terminal groups 0a...3a...7a electrically connected to the second relay terminal group 0e...3e...7e is different from the semiconductor device 70 shown in FIG. 8 of the present embodiment. The directions in which the bit numbers are increased are arranged in opposite directions to each other. On the other hand, the memory side second bus bar terminal groups 15b ... 11b ... 8b, 15c ... 11c ... 8c and the controller side second bus bar terminal group electrically connected to the fourth relay terminal group 8e ... 11e ... 15e The second group of 8a...11a...15a is arranged such that the direction in which the bit number is increased is set to be the same direction.

As a result, as seen from the thickness direction (planar direction) of the wiring substrate 76, it is easy to cause a situation in which the controller wafer 25 is connected in a state where the plurality of wiring patterns T1 cross each other. Between the terminals of the memory chips 21 and 22 (first memory chip). Therefore, in the semiconductor device 80 of the second comparative example, it is necessary to perform a three-dimensional wiring between the plurality of wiring patterns T1 in the wiring substrate 76, and thus the number of substrate layers or the transmission line is increased. Concerns about deterioration of road characteristics.

On the other hand, in the semiconductor device 70 of the present embodiment, as shown in FIGS. 8 and 9, the controller chip 25 is made by effectively utilizing the inversion function of the order of the bit numbers by the register 55. The terminal groups on the side of the memory chips 21, 22, 23, and 24 are arranged in an appropriate order, whereby the controller wafer 25 can be connected without the bonding wires W or the wiring patterns T1 or T2 crossing each other. The terminals of the memory chips 21, 22, 23, and 24 are electrically connected. In other words, the semiconductor device 70 of the present embodiment is different from the layout of the first and second embodiments in which the controller wafer 25 is placed on the memory chip 24, and the controller wafer 25 is disposed on the wiring substrate 76. In the layout of the third embodiment above, it is also possible to suppress an increase in the number of substrate layers and to secure desired transmission line characteristics.

<Fourth embodiment>

Next, a fourth embodiment will be described with reference to Figs. 13 to 15 (and Figs. 16 and 17 showing Comparative Example 3). It is noted that the same components as those in the third embodiment shown in FIG. 8 to FIG. 10 are denoted by the same reference numerals, and the description thereof will not be repeated.

As shown in FIGS. 13 and 14 , the semiconductor device 90 of the fourth embodiment includes a wiring board 96 instead of the wiring board 76 included in the semiconductor device 70 of the third embodiment. Further, the semiconductor device 90 includes the register 55 as in the third embodiment.

As shown in FIG. 13 and FIG. 14, the first relay terminal group 7d...3d...0d and the second relay terminal group 0e...3e...7e which are electrically connected to each other by the plurality of wiring patterns T1 are arranged in the wiring. The side portion 96a (first side portion) side of the substrate 96. On the other hand, the third relay terminal groups 8d to 11d...15d and the fourth relay terminal groups 15e to 11e...8e which are electrically connected to each other by the plurality of wiring patterns T2 are arranged on the side of the wiring substrate 96, respectively. 96b (2nd side) side.

As shown in FIG. 15, the memory chips 21, 22, 23, and 24 are sequentially laminated on one main surface (the mounting surface of the wafer) of the wiring substrate 96. On the other hand, the controller wafer 25 is individually mounted on one main surface (the mounting surface of the wafer) of the wiring substrate 96. More specifically, the controller chip 25 is disposed at a position parallel to the memory chips 21, 22, 23, 24 in the direction along the surface of the substrate of the wiring substrate 96, that is, as shown in FIG. 13, from the thickness direction of the wiring substrate 96 (planar direction) It is observed that the wiring substrate 96 is placed on a short side (left side in FIG. 13).

As shown in FIG. 15, the memory chips 21, 22, 23, and 24 and the controller wafer 25 are sealed to the wiring substrate 96 together with the bonding wires W by the sealing resin layer 98.

Here, in the present embodiment, as shown in FIGS. 13 and 14, the register 55 logically inverts the order of the bit numbers of the controller-side second bus terminal group of the controller wafer 25 ( The sort order is inverted from 8a...11a...15a to 15a...11a...8a) as shown in Figs. 13 and 14 .

Further, in the semiconductor device 90 of the present embodiment, as shown in FIG. 13, the memory-side first busbar terminal groups 7b...3b...0b, 7c...3c...0c are electrically connected to the second relay terminal group 0e. ...3e...7e, the first group of the first busbar terminal groups 0a...3a...7a on the controller side, and the second busbar terminal groups 8b...11b...15b,8c...11c...15c on the memory side and electrically connected to The second group of the controller-side second busbar terminal groups 15a...11a...8a of the fourth relay terminal group 15e...11e...8e is targeted, and all the terminal groups of the first and second groups are in the order of the bit number. In the arrangement, the terminal groups of the first group and the terminal groups of the second group are arranged such that the direction in which the bit numbers are increased are opposite to each other.

As shown in FIG. 13, even when the controller wafer 25 and the memory chips 21, 22, 23, and 24 are arranged on the wiring substrate 96, the controller wafer 25 side and the memory chips 21, 22, The terminal groups on the 23 and 24 sides are arranged in an appropriate order, and the order of the order of the bit numbers by the register 55 is effectively utilized, thereby, as shown in FIGS. 13 and 14 , the self-wiring substrate When the thickness direction of 96 is observed, the controller wafer 25 and the terminals of the memory chips 21, 22, 23, and 24 can be electrically connected without interlacing a plurality of bonding wires W or a plurality of wiring patterns T1 or T2.

On the other hand, as shown in FIG. 16 and FIG. 17, the comparative example 3 which does not have the register 55 is shown. In the semiconductor device 60, the memory-side first bus terminal group 7b...3b...0b, 7c...3c...0c and the controller-side first bus terminal electrically connected to the second relay terminal group 0e...3e...7e The first group of the groups 0a...3a...7a is arranged such that the direction in which the bit numbers are increased is set to be opposite to each other. On the other hand, the memory side second bus bar terminal groups 15b ... 11b ... 8b, 15c ... 11c ... 8c and the controller side second bus bar terminal group electrically connected to the fourth relay terminal group 8e ... 11e ... 15e The second group of 8a...11a...15a is different from the semiconductor device 90 shown in Fig. 13 of the present embodiment in that the direction in which the bit numbers are increased is arranged in the same direction.

Therefore, as seen in the thickness direction (planar direction) of the wiring substrate 96, as shown in FIG. 17, the result is that the controller wafer 25 and the memory chip are connected in a state where the plurality of wiring patterns T2 cross each other. 23, 24 (second memory chip) between the terminals. Therefore, in the semiconductor device 60 of Comparative Example 3, it is necessary to three-dimensionally interconnect a plurality of wiring patterns T2 in the wiring substrate 96, which inevitably leads to an increase in the number of substrate layers or deterioration in transmission line characteristics.

On the other hand, in the semiconductor device 90 of the present embodiment, as shown in FIGS. 13 and 14, the inversion function of the order of the bit numbers by the register 55 is effectively utilized, and the controller wafer 25 side is provided. The terminal groups on the memory chips 21, 22, 23, and 24 sides are arranged in an appropriate order, whereby the controller wafer 25 and the memory can be mounted without crossing the bonding wires W or the wiring patterns T1 or T2. The terminals of the wafers 21, 22, 23, 24 are electrically connected. In other words, the semiconductor device 90 of the present embodiment differs from the layout of the first and second embodiments in which the controller wafer 25 is disposed on the memory chip 24, even in the controller wafer 25 and the memory chip 21, In the layout of the fourth embodiment in which the 22, 23, and 24 arrays are arranged on the wiring substrate 96, the increase in the number of substrate layers of the wiring substrate 96 can be suppressed, and good transmission line characteristics can be obtained.

The embodiments of the present invention have been described above, but the embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments are It is to be understood that various modifications, substitutions and changes may be made without departing from the scope of the invention. The scope of the invention and its modifications are intended to be included within the scope of the invention and the scope of the invention.

For example, in the above-described first to fourth embodiments, semiconductor devices in which two first memory chips (memory chips 21 and 22) and second memory chips (memory chips 23 and 24) are respectively mounted are exemplified, but Alternatively, a semiconductor device in which four first memory chips and a second memory chip are mounted may be used as another embodiment, and one first memory chip and second memory may be mounted on each. The semiconductor device of the bulk wafer is further used as another embodiment.

0a...3a...7a‧‧‧1st busbar terminal group on the controller side

0b...3b...7b, 0c...3c...7c‧‧‧ Memory side first bus terminal group

0d...3d...7d‧‧‧1st relay terminal group

0e...3e...7e‧‧‧2nd relay terminal group

8a...11a...15a‧‧‧2nd busbar terminal group on controller side

8b...11b...15b,8c...11c...15c‧‧‧Memory side second bus terminal group

8d...11d...15d‧‧‧3rd relay terminal group

21, 22‧‧‧ memory chip (first memory chip)

21a, 22a‧‧‧ side (third side)

23, 24‧‧‧ memory chip (second memory chip)

23a, 24a‧‧‧ side (fourth side)

25‧‧‧ Controller chip

25a‧‧‧Border (5th side)

25b‧‧‧Border (6th side)

26‧‧‧Wiring substrate

26a‧‧‧Border (1st side)

26b‧‧‧Border (2nd side)

30‧‧‧Semiconductor device

W‧‧‧ bonding wire

Claims (6)

A semiconductor device comprising: a rectangular wiring board including: a first side portion; and a second side portion facing the first side portion, and a first relay terminal arranged on the first side portion side The group and the second relay terminal group are connected to the wiring pattern of the first relay terminal group and the second relay terminal group, and the third relay terminal group arranged on the second side portion; A memory wafer comprising: a third side portion disposed on the first side portion side; and a memory body that is arranged along the third side portion and electrically connected to the first relay terminal group via a bonding wire a first bus bar terminal group; a rectangular second memory chip including: a fourth side portion disposed on the second side portion; and a fourth side portion arranged along the fourth side portion and connected to the above via a bonding wire a memory-side second bus bar terminal group electrically connected to the third relay terminal group; and a rectangular controller chip including a fifth side portion disposed on the first side portion side along the fifth side The controller-side first busbar that is electrically connected to the second relay terminal group via the bonding wires a sub-group, a sixth side portion disposed on the second side portion side, and a controller-side second bus bar that is arranged along the sixth side portion and electrically connected to the third relay terminal group via a bonding wire a terminal group; the first busbar terminal group on the memory side and the first busbar terminal group on the controller side are arranged in the order of the bit number, and the directions in which the bit numbers are increased are reversed; The second busbar terminal group on the memory side and the second busbar terminal group on the controller side are arranged in the order of the bit number, and the directions in which the bit numbers are increased in the same direction are arranged in the same direction; a memory chip is disposed on the wiring substrate; the second memory chip is disposed on the first memory chip; The controller chip is disposed on the second memory chip. The semiconductor device according to claim 1, further comprising: a logic inversion unit that causes at least one of the controller-side first bus bar terminal group and the controller-side second bus bar terminal group The sort order of the bit numbers corresponding to the group is logically inverted. A semiconductor device comprising: a rectangular wiring board including: a first side portion; and a second side portion facing the first side portion, and a first relay terminal arranged on the first side portion side The group and the second relay terminal group are connected to the first interconnect pattern of the first relay terminal group and the second relay terminal group, and are arranged on the third side of the second side, and the fourth relay terminal group and the fourth a relay terminal group, and a second wiring pattern that connects the third relay terminal group and the fourth relay terminal group; and the rectangular first memory chip includes a first side portion disposed on the first side a side portion, and a memory-side first bus bar terminal group that is electrically connected to the first relay terminal group via the bonding wires and arranged along the third side portion; and a rectangular second memory chip. The memory side second bus bar terminal disposed on the second side portion side and the fourth side portion arranged along the fourth side portion and electrically connected to the third relay terminal group via a bonding wire a controller chip of rectangular shape, comprising: a fifth side portion disposed on the side of the first side portion, along The controller-side first bus bar terminal group in which the fifth side portion is arranged and electrically connected to the second relay terminal group via the bonding wire is disposed on the sixth side portion on the second side portion side, and along a controller-side second busbar terminal group electrically connected to the fourth relay terminal group via a bonding wire, and a logic inverting portion that is connected to the controller-side first confluence The sort order of the bit numbers corresponding to at least one of the terminal group and the second bus bar terminal group on the controller side is logically inverted; The memory-side first busbar terminal group and the first group of the controller-side first busbar terminal group, the memory-side second busbar terminal group, and the controller-side second busbar terminal group In the second group, all of the terminal groups of the first and second groups are arranged in the order of the bit numbers, and the terminal groups of the first group and the terminal groups of the second group are mutually increased by the bit number. The directions are arranged in the same direction; the controller chip is disposed on the wiring substrate; the first memory chip is disposed on the controller wafer; and the second memory chip is disposed on the first memory chip. A semiconductor device comprising: a rectangular wiring board including: a first side portion; and a second side portion facing the first side portion, and a first relay terminal arranged on the first side portion side The group and the second relay terminal group are connected to the first interconnect pattern of the first relay terminal group and the second relay terminal group, and are arranged on the third side of the second side, and the fourth relay terminal group and the fourth a relay terminal group, and a second wiring pattern that connects the third relay terminal group and the fourth relay terminal group; and the rectangular first memory chip includes a first side portion disposed on the first side a side portion, and a memory-side first bus bar terminal group that is electrically connected to the first relay terminal group via the bonding wires and arranged along the third side portion; and a rectangular second memory chip. The memory side second bus bar terminal disposed on the second side portion side and the fourth side portion arranged along the fourth side portion and electrically connected to the third relay terminal group via a bonding wire a controller chip having a rectangular shape and including a fifth side portion disposed on the side of the first side portion, along the upper side a controller-side first bus bar terminal group in which the fifth side portions are arranged and electrically connected to the second relay terminal group via the bonding wires, is disposed on the sixth side portion on the second side portion side, and along the above The sixth side is arranged and connected via a bonding wire a controller-side second busbar terminal group electrically connected to the fourth relay terminal group; and a logic inverting portion that is connected to the controller-side first busbar terminal group and the controller-side second busbar The order of the bit numbers corresponding to at least one of the terminal groups is logically reversed; and the memory-side first bus terminal group and the first group of the controller-side first bus terminal groups are And the second group of the second busbar terminal group on the memory side and the second busbar terminal group on the controller side, wherein all of the terminal groups of the first and second groups are arranged in the order of the bit number, the first The terminal groups of the group and the terminal group of the second group are arranged such that the direction in which the bit numbers of each other increase are reversed, and the controller chip and the first memory chip are disposed on the wiring substrate; The memory chip is placed on the first memory chip. The semiconductor device according to any one of claims 1 to 4, wherein the second memory chip is in a state in which the first memory chip is rotated by 180 degrees in a direction along a surface of the wiring board. The semiconductor device according to any one of claims 1 to 4, wherein the first and second memory chips are mounted on the wiring board in plural numbers.