JP6071929B2 - Semiconductor device - Google Patents

Description

  Embodiments described herein relate generally to a semiconductor device.

  A semiconductor device is known in which a memory chip and a controller chip for controlling the operation of the memory chip are mounted on a wiring board. This type of semiconductor device has a need to selectively use a combination of, for example, one type of controller chip and memory chips having various specifications with different terminal arrangements.

  By the way, when it is going to satisfy such a request | requirement, there exists a possibility that the connection structure between the terminals of a memory chip and a controller chip may become complicated by the difference in the arrangement of the terminals in a memory chip.

US Patent Application Publication No. 2013/0114323

  Specifically, the need for three-dimensional wiring (three-dimensional wiring) between the terminals of the memory chip and the controller chip described above via a wiring board increases, and as a result, the number of wiring board layers increases. May be forced. Furthermore, it is assumed that wirings of different layers on the wiring board cross three-dimensionally. In such a case, there is a concern about deterioration of transmission line characteristics.

  Therefore, the problem to be solved by the present invention is to provide a semiconductor device capable of ensuring desired transmission line characteristics while suppressing an increase in the number of substrate layers by rational connection between a memory chip and a controller chip.

  The semiconductor device according to the embodiment includes a wiring board, first and second memory chips, and a controller chip. The wiring board is configured in a rectangular shape, and the first relay is arranged on the first side, the second side facing the first side, and the first side. A terminal group, a second relay terminal group, a wiring pattern connecting the first relay terminal group and the second relay terminal group, and a third relay terminal group arranged on the second side portion side, Have. The first memory chip has a rectangular shape, and is arranged along the third side portion disposed on the first side portion side and the third side portion, and a bonding wire. And a memory-side first bus terminal group electrically connected to the first relay terminal group via the first and second relay terminal groups. The second memory chip has a rectangular shape, is arranged along the fourth side portion arranged on the second side portion side, the fourth side portion, and a bonding wire. And a memory-side second bus terminal group electrically connected to the third relay terminal group via the first and second relay terminal groups. The controller chip is configured in a rectangular shape, and is arranged along the fifth side portion disposed on the first side portion side and the fifth side portion, and via a bonding wire. A controller-side first bus terminal group electrically connected to the second relay terminal group, a sixth side disposed on the second side, and an array along the sixth side And a controller-side second bus terminal group electrically connected to the third relay terminal group via a bonding wire. Further, the memory-side first bus terminal group and the controller-side first bus terminal group are arranged in the order of bit numbers, respectively, and are arranged with the directions in which the bit numbers increase in opposite directions. The memory-side second bus terminal group and the controller-side second bus terminal group are arranged in the order of bit numbers, and are arranged in the same direction in which the bit numbers increase. Furthermore, the first memory chip is provided on the wiring board. The second memory chip is provided on the first memory chip. Further, the controller chip is provided on the second memory chip.

The figure which shows the state which saw through the semiconductor device which concerns on 1st Embodiment from the plane direction. FIG. 2 is a diagram illustrating a wiring pattern of a wiring board provided in the semiconductor device of FIG. 1 and a layout of a terminal group of a controller chip. The arrow view which shows the state which saw through the semiconductor device of FIG. 1 from arrow A direction. FIG. 2 is a plan view illustrating a configuration of a memory chip included in the semiconductor device of FIG. 1. The figure which shows the state which saw through the semiconductor device of the comparative example 1 from the plane direction. The figure which shows the state which saw through the semiconductor device which concerns on 2nd Embodiment from the plane direction. FIG. 7 is a diagram illustrating an image with / without replacement of bit arrangement by a logic inversion unit included in the semiconductor device of FIG. 6. The figure which shows the state which saw through the semiconductor device which concerns on 3rd Embodiment from the plane direction. FIG. 9 is a diagram showing a layout of a wiring pattern of a wiring board included in the semiconductor device of FIG. 8. The arrow view which shows the state which saw through the semiconductor device of FIG. 8 from the arrow B direction. The figure which shows the state which saw through the semiconductor device of the comparative example 2 from the plane direction. FIG. 12 is a diagram showing a layout of a wiring pattern of a wiring board provided in the semiconductor device of FIG. 11. The figure which shows the state which saw through the semiconductor device which concerns on 4th Embodiment from the plane direction. FIG. 14 is a diagram showing a layout of a wiring pattern of a wiring board provided in the semiconductor device of FIG. 13. The arrow view which shows the state which saw through the semiconductor device of FIG. 13 from the arrow C direction. The figure which shows the state which saw through the semiconductor device of the comparative example 3 from the plane direction. FIG. 17 is a diagram showing a layout of a wiring pattern of a wiring board included in the semiconductor device of FIG. 16.

Hereinafter, embodiments will be described with reference to the drawings.
<First Embodiment>
As shown in FIGS. 1 to 3, the semiconductor device 30 of this embodiment includes a wiring board 26, memory chips 21 and 22 (first memory chip), and memory chips 23 and 24 (second memory chip). And a semiconductor package such as an FBGA (Fine Pitch Ball Grid Array) including a controller chip 25, a sealing resin layer 28, and solder balls 27.

  As shown in FIGS. 1 and 2, the wiring board 26 is a rectangular (rectangular) printed wiring board in which a plurality of wiring patterns including a wiring pattern T1 (first wiring pattern) are formed on a surface layer or an inner layer. is there. The wiring substrate 26 includes a pair of short sides, a pair of long sides, a side part 26a (first side part), and a side part (second side part) 26b opposite to the side part 26a. Have. On one main surface (chip mounting surface) of the wiring board 26, a first relay terminal group 7d ... 3d ... 0d, a second relay terminal group 0e ... 3e ... 7e, a third relay terminal group 8d ... 11d ... 15d, Are formed respectively.

  The first relay terminal groups 7d ... 3d ... 0d and the second relay terminal groups 0e ... 3e ... 7e are arranged on the side 26a side of the wiring board 26, respectively. As shown in FIG. 2, the plurality of wiring patterns T1 electrically connect the first relay terminal groups 7d ... 3d ... 0d and the second relay terminal groups 0e ... 3e ... 7e. The third relay terminal groups 8d to 11d are arranged on the side 26b side of the wiring board 26. Further, as shown in FIG. 3, the solder ball 27 described above is provided as an external connection terminal on the other main surface (chip non-mounting surface) of the wiring board 26.

  As shown in FIGS. 1, 3, and 4, the memory chips 21, 22, 23, and 24 are each a rectangular (rectangular) nonvolatile semiconductor memory element, for example, a NAND flash memory chip. The memory chips 21 and 22 have a pair of short sides facing each other and a pair of long sides facing each other including the side portions 21a and 22a (third side portions). On the other hand, the memory chips 23 and 24 have a pair of short sides facing each other and a pair of long sides facing each other including the side portions 23a and 24a (fourth side portions).

  As shown in FIG. 3, these memory chips 21, 22, 23, and 24 are mounted on one main surface side of the wiring board 26 in a state where they are sequentially stacked via an insulating resin (not shown). . That is, a plurality of memory chips 21 and 22 as first memory chips and a plurality of memory chips 23 and 24 as second memory chips are mounted on the wiring board 26 (two in this embodiment). ing. As shown in FIGS. 1 and 3, the memory chips 21 and 22 have memory side first bus terminal groups 7b ... 3b ... 0b and 7c ... 3c ... 0c along the side portions 21a, 22a. Each is arranged. On the other hand, in the memory chips 23, 24, memory side second bus terminal groups 8b ... 11b ... 15b and 8c ... (11c) ... 15c are arranged along the side portions 23a, 24a, respectively.

  Further, as shown in FIG. 1, the side portions 21 a and 22 a of the memory chips 21 and 22 are arranged on the side portion 26 a side of the wiring substrate 26, respectively. On the other hand, the side parts 23 a and 24 a of the memory chips 23 and 24 are respectively arranged on the side part 26 b side of the wiring board 26. Here, as shown in FIG. 3, the memory chips 21 and 22 as the first memory chip and the memory chips 23 and 24 as the second memory chip have the same structure (however, the non-mounting surface of the chip). Is the memory chip excluding the thickness of the memory chips 21 to 24). That is, as shown in FIG. 1, the memory chips 23 and 24 as the second memory chips rotate the memory chips 21 and 22 as the first memory chips by 180 degrees in the direction along the surface of the wiring board 26. The thing of letting it be applied is applied.

  The memory side first bus terminal groups 7b... 3b... 0b and 7c... 3c... 0c of the memory chips 21 and 22 arranged in this way are respectively connected via bonding wires W as shown in FIGS. The first relay terminal groups 7d... 3d. On the other hand, the memory-side second bus terminal groups 8b ... 11b ... 15b and 8c ... (11c) ... 15c of the memory chips 23, 24 are respectively connected via bonding wires W as shown in FIGS. 3 relay terminal groups 8d ... 11d ... 15d are electrically connected.

  As shown in FIGS. 1 to 3, the controller chip 25 is a rectangular (rectangular) semiconductor control element that controls the operations of the memory chips 21, 22, 23, and 24. The controller chip 25 includes a pair of short sides, a pair of short sides, a side portion 25a (fifth side portion), and a side portion (sixth side portion) 25b that faces the side portion 25a. Have. As shown in FIG. 3, the controller chip 25 is mounted on the top of the memory chip 24 in a state of being laminated via an insulating resin (not shown). As shown in FIGS. 1 and 2, the side portions 25 a and 25 b of the controller chip 25 are disposed on the side portions 26 a and 26 b side of the wiring substrate 26, respectively. More specifically, the controller chip 25 is mounted at a position unevenly distributed on one short side (left side in FIG. 1) on the memory chip 24 as viewed from the thickness direction (planar direction) of the wiring board 26. .

  Furthermore, as shown in FIGS. 1-3, the controller chip 25 is provided with controller side 1st bus terminal group 0a ... 3a ... 7a and controller side 2nd bus terminal group 8a ... 11a ... 15a. The controller side first bus terminal groups 0a ... 3a ... 7a are arranged along the side 25a and are electrically connected to the second relay terminal groups 0e ... 3e ... 7e via bonding wires W. . On the other hand, the controller side second bus terminal groups 8a... 11a... 15a are arranged along the side portions 25b and are electrically connected to the third relay terminal groups 8d. ing.

  The bonding wire W described above uses, for example, gold, silver, copper, or the like as a material. The terminal groups formed on the controller chip 25 and the memory chips 21, 22, 23, 24 use, for example, aluminum as a material. Further, as shown in FIG. 3, the sealing resin layer 28 includes the bonding chips W and the memory chips (first memory chips) 21 and 22, the memory chips (second memory chips) 23 and 24, and the controller chip. 25 is sealed on the wiring board 26.

  As shown in FIG. 1, in the semiconductor device 30 of this embodiment, the controller-side first bus terminal group in which the I / O terminal numbers of the I / O (data input / output) bus are ports related to the 0th to 15th ports. 0a ... 3a ... 7a, controller side second bus terminal group 8a ... 11a ... 15a, memory side first bus terminal group 7b ... 3b ... 0b, 7c ... 3c ... 0c, memory side second bus terminal group 8b ... 11b ... 15b , 8c... 15c, data input / output terminals (I / O terminals) are mainly exemplified. However, the semiconductor device 30 according to the present embodiment includes, for example, a read enable terminal, a write enable terminal, a command latch enable terminal, an address latch enable terminal, and the like which are ports of buses other than the I / O bus, as well as a controller chip. 25 and the memory chips 21, 22, 23, 24.

  Here, a rational connection structure between the controller chip 25 and the memory chips 21, 22, 23, and 24 in the semiconductor device 30 of the present embodiment will be described. As shown in FIG. 1, the first bus terminal group 7b on the memory side serving as a port related to bit number 0 (I / O0) to bit number 7 (I / O7) of the I / O bus in the semiconductor device 30. 3b... 0b, 7c... 3c... 0c and the controller side first bus terminal group 0a... 3a... 7a are arranged in the order of bit numbers. The bit numbers are arranged in the opposite directions (direct directions).

  Further, as shown in FIG. 1, a memory-side second bus terminal group that is a port related to bit number 8 (I / O 8) to bit number 15 (I / O 15) of the I / O bus in the semiconductor device 30. 8b ... 11b ... 15b, 8c ... (11c) ... 15c and the controller side second bus terminal group 8a ... 11a ... 15a are arranged in the order of bit numbers, and the direction in which the bit numbers increase is the same as each other. They are arranged in the same direction.

  By arranging the terminal groups on the controller chip 25 side and the memory chips 21, 22, 23, and 24 side in this arrangement, as shown in FIG. 1 and FIG. Direction), the terminals of the controller chip 25 and the memory chips 21, 22, 23, and 24 are electrically connected without crossing the bonding wires W and the wiring patterns T1. It becomes possible.

  On the other hand, as shown in FIG. 5, the semiconductor device 40 of Comparative Example 1 includes a controller chip 45 instead of the controller chip 25. The controller chip 45 is arranged in the opposite direction to the controller chip 25 in the direction in which the bit numbers in the controller side first bus terminal group and the controller side second bus terminal group increase. That is, the memory-side first bus terminal groups 7b ... 3b ... 0b, 7c ... 3c ... 0c and the controller-side first bus terminal groups 7a ... 3a ... 0a of the semiconductor device 40 in Comparative Example 1 have an increased bit number. They are arranged in the same direction.

  Further, as shown in FIG. 5, the memory-side second bus terminal groups 8b ... 11b ... 15b, 8c ... (11c) ... 15c and the controller-side second bus terminal groups 15a ... 11a ... 8a of the semiconductor device 40 in Comparative Example 1. Are arranged with the bit numbers increasing in opposite directions. As a result, as shown in FIG. 5, when viewed from the thickness direction (planar direction) of the wiring board 26, the controller chip 25 and the memory chip 21 in a state where the plurality of bonding wires W and the plurality of wiring patterns T1 intersect each other. , 22, 23, and 24 are electrically connected.

  For this reason, since the semiconductor device 40 of Comparative Example 1 needs to wire a plurality of wiring patterns T1 three-dimensionally (three-dimensional wiring) in the wiring substrate 26, the number of substrate layers is increased. There are concerns about an increase in manufacturing cost and an increase in product size. Further, at this time, since wirings of different layers in the wiring board 26 cross three-dimensionally, there is a concern about deterioration of transmission line characteristics (characteristic impedance of the transmission line) and the like.

  On the other hand, according to the semiconductor device 30 of the present embodiment, as shown in FIGS. 1 and 2, the terminal groups on the controller chip 25 side and the memory chips 21, 22, 23, and 24 side are arranged in an appropriate arrangement. As a result, the controller chip and the memory chip can be rationally connected, thereby ensuring desired transmission line characteristics while suppressing an increase in the number of substrate layers.

<Second Embodiment>
Next, a second embodiment will be described with reference to FIGS. In FIG. 6, the same constituent elements as those in the first embodiment shown in FIGS. 1 to 4 are given the same reference numerals and redundant description is omitted.

  The semiconductor device 50 according to the second embodiment includes the memory chips 21 and 22 (first memory chip) and the memory chips 23 and 24 (second memory) shown in FIG. 1 included in the semiconductor device 30 according to the first embodiment. In place of the memory chip), as shown in FIG. 6, memory chips 41 and 42 (first memory chip) and memory chips 43 and 44 (second memory chip) are provided. In addition, the semiconductor device 50 of this embodiment further includes a register 55 that functions as a logic inversion unit, as shown in FIGS.

  As shown in FIG. 6, the memory chips 43 and 44 as the second memory chips rotate the memory chips 41 and 42 as the first memory chip by 180 degrees in the direction along the surface of the wiring board 26. The thing of the state is applied. Here, as shown in FIG. 6, the memory chips 41, 42, 43, and 44 have memory side first bus terminal groups 0b ... 3b ... 7b, 0c ... 3c ... 7c and memory side second bus terminal groups 15b ... 11b. ... 8b, 15c... (11c)... 8c are arranged in the opposite direction to the memory chips 21, 22, 23, and 24 shown in FIG.

  Therefore, in the first embodiment, as shown in FIG. 5, the plurality of bonding wires W and the plurality of wiring patterns T <b> 1 intersect with each other when viewed from the thickness direction (planar direction) of the wiring board 26. There is a concern that the terminals of the controller chip 25 and the memory chips 41, 42, 43, 44 are connected.

  Therefore, as shown in FIGS. 6 and 7, the register 55 has a bit number corresponding to at least one of the controller-side first bus terminal group and the controller-side second bus terminal group in the controller chip 25. The order of arrangement is logically reversed. In the present embodiment, the register 55 outputs a predetermined external signal to the controller chip 25 side, for example, as shown in FIG. 6, and the controller side first bus terminal group and the controller side second bus terminal group 1 is logically reversed (from 0a... 3a... 7a and 8a... 11a... 15a shown in FIG. 1 to 7a... 3a... 0a and 15a as shown in FIG. (Reverse to 11a ... 8a).

  The register 55 may be mounted on the controller chip 25 itself, or may be configured as a separate element from the controller chip 25 as shown in FIG. Further, in FIG. 6, in order to make it easier to visually understand the reversal of the order of arrangement of the bit numbers, the arrangement of the symbols in FIG. 6 with the controller side first bus terminal group and the controller side second bus terminal group is It is shown opposite to the arrangement of the symbols in FIG. Further, in FIG. 6, a plurality of wiring patterns T1 that electrically connect the first relay terminal groups 0d... 3d... 7d and the second relay terminal groups 7e. ) Is schematically shown by dotted lines.

  As described above, also in the semiconductor device 50 of the present embodiment, the memory-side first bus terminal group serving as a port related to bit number 0 (I / O0) to bit number 7 (I / O7) of the I / O bus. 0b... 3b... 7b, 0c... 3c... 7c and the controller-side first bus terminal group 7a... 3a. Are arranged. Further, the memory side second bus terminal groups 15b ... 11b ... 8b, 15c ... (11c) which are ports related to bit number 8 (I / O8) to bit number 15 (I / O15) of the I / O bus. 8c and controller-side second bus terminal group 15a ... 11a ... 8a are arranged in the order of bit numbers, and the bit numbers increase in the same direction.

  Therefore, according to the semiconductor device 50 of the present embodiment, the terminal groups on the controller chip 25 side and the memory chips 41, 42, 43, and 44 side are set while utilizing the function of reversing the order of bit numbers by the register 55. By arranging them appropriately, as shown in FIG. 6, between the terminals of the controller chip 25 and the memory chips 41, 42, 43, 44 without crossing a plurality of bonding wires W and a plurality of wiring patterns T <b> 1. It becomes possible to connect electrically. Thereby, an increase in the number of substrate layers of the wiring substrate 26 can be suppressed, and good transmission line characteristics can be obtained.

<Third Embodiment>
Next, a third embodiment will be described based on FIGS. 8 to 10 (and FIGS. 11 and 12 showing a comparative example 2). 8 to 10, the same components as those in the first embodiment illustrated in FIGS. 1 to 4 are denoted by the same reference numerals and redundant description is omitted.

  The semiconductor device 70 according to the third embodiment includes a wiring substrate 76 as shown in FIGS. 8 to 10 instead of the wiring substrate 26 included in the semiconductor device 30 according to the first embodiment. Further, the semiconductor device 70 includes a register 55 as in the second embodiment.

  As shown in FIGS. 8 and 9, the wiring board 76 has a plurality of wiring patterns including a wiring pattern T1 (first wiring pattern) and a wiring pattern T2 (second wiring pattern) formed on the surface layer and the inner layer. A rectangular printed wiring board. On one main surface (chip mounting surface) of the wiring board 76, a first relay terminal group 7d ... 3d ... 0d, a second relay terminal group 7e ... 3e ... 0e, a third relay terminal group 8d ... 11d ... 15d, The fourth relay terminal groups 8e ... 11e ... 15e are formed.

  As shown in FIGS. 8 and 9, the first relay terminal groups 7d... 3d... 0d and the second relay terminal groups 7e... 3e... 0e are on the side 76a (first side) side of the wiring board 76, respectively. It is arranged. The plurality of wiring patterns T1 electrically connect the first relay terminal groups 7d ... 3d ... 0d and the second relay terminal groups 7e ... 3e ... 0e. On the other hand, the third relay terminal groups 8d ... 11d ... 15d and the fourth relay terminal groups 8e ... 11e ... 15e are arranged on the side 76b (second side) side of the wiring board 76, respectively. The plurality of wiring patterns T2 electrically connect the third relay terminal groups 8d ... 11d ... 15d and the fourth relay terminal groups 8e ... 11e ... 15e.

  As shown in FIG. 10, the controller chip 25 is mounted immediately above one main surface of the wiring board 76. As shown in FIGS. 8 and 9, the controller chip 25 is mounted on the central portion of the wiring board 76 when viewed from the thickness direction (planar direction) of the wiring board 26. Further, the controller-side first bus terminal groups 7a ... 3a ... 0a of the controller chip 25 are electrically connected to the second relay terminal groups 7e ... 3e ... 0e via bonding wires W. On the other hand, the controller-side second bus terminal groups 8a ... 11a ... 15a of the controller chip 25 are electrically connected to the fourth relay terminal groups 8e ... 11e ... 15e via bonding wires W.

  The controller chip 25 connected in this way is sealed on the wiring substrate 76 together with the bonding wires W by a sealing resin layer 77 as shown in FIG. On the other hand, the memory chips 21, 22, 23, and 24 are sequentially mounted on the sealing resin layer 77. As shown in FIG. 10, these memory chips 21, 22, 23, and 24 are encapsulated by a sealing resin layer 78 together with a sealing resin layer 77 for sealing the controller chip 25 and a bonding wire W for connecting the memory chip. Sealed on the wiring board 76.

  In this embodiment, as shown in FIGS. 8 and 9, the register 55 logically reverses the order of arrangement of the bit numbers for the controller-side first bus terminal group in the controller chip 25 (the order of arrangement is 7a... 3a... 7a as shown in FIG. 8 and FIG.

  Furthermore, in the semiconductor device 70 of the present embodiment, as shown in FIG. 8, the memory side first bus terminal groups 7b... 3b... 0b, 7c. The first set of controller-side first bus terminal groups 7a ... 3a ... 0a, and the memory-side second bus terminal groups 8b ... 11b ... 15b, 8c ... 11c ... 15c and the fourth relay terminal group 8e ... 11e... 15e electrically connected to the controller-side second bus terminal group 8a... 11a... 15a, all the terminal groups of the first and second groups are in bit number order. Furthermore, the first set of terminal groups and the second set of terminal groups are arranged so that the bit numbers increase in the same direction.

  By arranging the terminal groups on the controller chip 25 side and the memory chips 21, 22, 23, and 24 side in such an arrangement and utilizing the reversal of the arrangement order of the bit numbers by the register 55, FIG. 9, the controller chip 25 and the memory chip can be seen without crossing a plurality of bonding wires W or a plurality of wiring patterns T1 or T2 when viewed from the thickness direction (planar direction) of the wiring board 76. Terminals 21, 22, 23, and 24 can be rationally connected.

  On the other hand, as shown in FIGS. 11 and 12, in the semiconductor device 80 of the comparative example 2 that does not include the register 55, the first bus terminal groups 7b... 3b... 0b, 7c. The first set of controller side first bus terminal groups 0a ... 3a ... 7a electrically connected to the two relay terminal groups 0e ... 3e ... 7e is the semiconductor device 70 shown in FIG. 8 of the present embodiment. Unlikely, the bit numbers are arranged in the opposite directions. On the other hand, the controller side second bus terminal groups 8a ... 11a ... 15a electrically connected to the memory side second bus terminal groups 15b ... 11b ... 8b, 15c ... 11c ... 8c and the fourth relay terminal groups 8e ... 11e ... 15e. Are arranged in the same direction in which the bit numbers increase.

  As a result, as schematically shown in FIG. 12, the controller chip 25 and the memory chip 21, with the plurality of wiring patterns T <b> 1 intersecting (crossing) when viewed from the thickness direction (planar direction) of the wiring substrate 76. 22 (first memory chip) is connected between the terminals. For this reason, in the semiconductor device 80 of the comparative example 2, since it is necessary to three-dimensionally wire the plurality of wiring patterns T1 within the wiring board 76, there is a concern about an increase in the number of board layers and a deterioration in transmission line characteristics.

  On the other hand, in the semiconductor device 70 of the present embodiment, as shown in FIGS. 8 and 9, the controller chip 25 side and the memory chips 21, 22, 23, The terminals of the controller chip 25 and the memory chips 21, 22, 23, 24 are arranged without crossing the bonding wires W and the wiring patterns T 1 or T 2 by arranging the terminal groups on the 24 side in an appropriate arrangement. They can be electrically connected. That is, according to the semiconductor device 70 of the present embodiment, unlike the layouts of the first and second embodiments in which the controller chip 25 is disposed on the memory chip 24, the controller chip 25 is disposed directly on the wiring board 76. Also in the layout of the third embodiment, desired transmission line characteristics can be ensured while suppressing an increase in the number of substrate layers.

<Fourth embodiment>
Next, a fourth embodiment will be described with reference to FIGS. 13 to 15 (and FIGS. 16 and 17 showing Comparative Example 3). 13 to 15, the same components as those in the third embodiment illustrated in FIGS. 8 to 10 are denoted by the same reference numerals, and redundant description is omitted.

  A semiconductor device 90 according to the fourth embodiment includes a wiring substrate 96 as shown in FIGS. 13 and 14 instead of the wiring substrate 76 included in the semiconductor device 70 according to the third embodiment. Further, the semiconductor device 90 includes a register 55 as in the third embodiment.

  As shown in FIGS. 13 and 14, the first relay terminal groups 7d... 3d... 0d and the second relay terminal groups 0e. They are respectively arranged on the side 96a (first side) side. On the other hand, the third relay terminal groups 8d... 11d... 15d and the fourth relay terminal groups 15e... 11e. Part) side.

  As shown in FIG. 15, the memory chips 21, 22, 23, and 24 are sequentially stacked on one main surface (chip mounting surface) of the wiring board 96. On the other hand, the controller chip 25 is mounted alone on one main surface (chip mounting surface) of the wiring board 96. More specifically, the controller chip 25 is aligned with the memory chips 21, 22, 23, and 24 in the direction along the substrate surface of the wiring board 96, that is, as shown in FIG. When viewed from the vertical direction (planar direction), the wiring board 96 is arranged at a position unevenly distributed on one short side (left side in FIG. 13).

  As shown in FIG. 15, the memory chips 21, 22, 23, 24 and the controller chip 25 are sealed on the wiring board 96 by a sealing resin layer 98 together with the bonding wires W.

  Here, in the present embodiment, as shown in FIGS. 13 and 14, the register 55 logically inverts the arrangement order of the bit numbers for the controller-side second bus terminal group in the controller chip 25 (the arrangement order is 8a... 11a... 15a are inverted to 15a... 11a... 8a as shown in FIGS.

  Further, in the semiconductor device 90 of the present embodiment, as shown in FIG. 13, the memory side first bus terminal groups 7b... 3b... 0b, 7c... 3c ... 0c and the second relay terminal groups 0e. The first set of controller-side first bus terminal groups 0a ... 3a ... 7a, and the memory-side second bus terminal groups 8b ... 11b ... 15b, 8c ... 11c ... 15c and the fourth relay terminal group 15e ... 11e... 8e electrically connected to the controller-side second bus terminal group 15a... 11a... 8a, all the terminal groups of the first and second groups are in bit number order. Furthermore, the first set of terminal groups and the second set of terminal groups are arranged with their bit numbers increasing in opposite directions.

  As shown in FIG. 13, even when the controller chip 25 and the memory chips 21, 22, 23, and 24 are arranged side by side on the wiring board 96, the controller chip 25 side and the memory chips 21, 22, 23, and 24 side As shown in FIGS. 13 and 14, a plurality of terminal groups are arranged in an appropriate arrangement and the reversal of the arrangement order of the bit numbers by the register 55 is used, as shown in FIGS. It is possible to electrically connect the terminals of the controller chip 25 and the memory chips 21, 22, 23, and 24 without crossing the bonding wires W and the plurality of wiring patterns T1 or T2.

  On the other hand, as shown in FIGS. 16 and 17, in the semiconductor device 60 of the comparative example 3 that does not include the register 55, the first bus terminal groups 7b... 3b... 0b, 7c. The first set of controller side first bus terminal groups 0a... 3a... 7a electrically connected to two relay terminal groups 0e... 3e. Has been. On the other hand, the controller side second bus terminal groups 8a ... 11a ... 15a electrically connected to the memory side second bus terminal groups 15b ... 11b ... 8b, 15c ... 11c ... 8c and the fourth relay terminal groups 8e ... 11e ... 15e. Unlike the semiconductor device 90 shown in FIG. 13 of the present embodiment, the second set is arranged in such a way that the bit numbers increase in the same direction.

  For this reason, as schematically shown in FIG. 17, the controller chip 25 and the memory chips 23 and 24 (the first chip) in a state where the plurality of wiring patterns T2 intersect each other when viewed from the thickness direction (planar direction) of the wiring board 96. As a result, the terminals of the two memory chips are connected. Therefore, in the semiconductor device 60 of Comparative Example 3, it is necessary to three-dimensionally wire the plurality of wiring patterns T2 in the wiring board 96, and the number of board layers is increased and the transmission line characteristics are inevitably deteriorated.

  On the other hand, in the semiconductor device 90 of the present embodiment, as shown in FIGS. 13 and 14, the controller chip 25 side and the memory chips 21 and 22 are utilized while utilizing the function of reversing the arrangement order of the bit numbers by the register 55. , 23, and 24, by arranging each terminal group in an appropriate arrangement, the controller chip 25 and the memory chips 21, 22, 23, 24 do not cross the bonding wires W or the wiring patterns T 1 or T 2. And the terminals can be electrically connected. That is, according to the semiconductor device 90 of the present embodiment, unlike the layouts of the first and second embodiments in which the controller chip 25 is disposed on the memory chip 24, the controller chip 25 and the memory chips 21, 22, 23 , 24 are arranged side by side on the wiring board 96, the increase in the number of substrate layers of the wiring board 96 can be suppressed, and good transmission line characteristics can be obtained.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, in the above-described first to fourth embodiments, a semiconductor device in which two each of the first memory chip (memory chips 21 and 22) and the second memory chip (memory chips 23 and 24) are mounted is provided. Although illustrated, instead of this, a semiconductor device in which four first memory chips and four second memory chips are mounted may be applied as another embodiment, and further, the first memory chip may be applied. A semiconductor device in which a chip and a second memory chip are mounted one by one can also be applied as another embodiment.

  0a ... 3a ... 7a, controller side first bus terminal group, 0b ... 3b ... 7b, 0c ... 3c ... 7c, ... memory side first bus terminal group, 0d ... 3d ... 7d, ... first relay terminal group, 0e ... 3e ... 7e, ... second relay terminal group, 8a ... 11a ... 15a, ... controller side second bus terminal group, 8b ... 11b ... 15b, 8c ... 11c ... 15c, ... memory side second bus terminal group, 8d ... 11d ... 15d, ... third relay terminal group, 8e ... 11e ... 15e, ... fourth relay terminal group, 21,22,41,42 ... memory chip (first memory chip), 21a, 22a ... side (first) 3 side), 23, 24, 43, 44... Memory chip (second memory chip), 23a, 24a... Side part (fourth side part), 25... Controller chip, 25a. Side), 25b... Side part (sixth side part), 26 76, 96 ... wiring board, 26a, 76a, 96a ... side (first side), 26b, 76b, 96b ... side (second side), 30, 50, 70, 90 ... semiconductor device, 55... Register, T1... Wiring pattern (first wiring pattern), T2... Wiring pattern (second wiring pattern), W.

Claims (6)

A first side part, a second side part facing the first side part, a first relay terminal group and a second relay terminal group respectively arranged on the first side part side, and the first side part A rectangular wiring board having a wiring pattern connecting one relay terminal group and the second relay terminal group, and a third relay terminal group arranged on the second side,
A third side portion disposed on the first side portion side and the third side portion are arranged along the third side portion, and are electrically connected to the first relay terminal group via a bonding wire. A memory-side first bus terminal group, a rectangular first memory chip,
A fourth side disposed on the second side and the fourth side are arranged along the fourth side, and are electrically connected to the third relay terminal group via a bonding wire. A second memory chip having a rectangular shape having a second bus terminal group on the memory side;
The fifth side portion disposed on the first side portion side and the fifth side portion are arranged along the fifth side portion, and are electrically connected to the second relay terminal group through bonding wires. The first bus terminal group on the controller side, the sixth side disposed on the second side, the array along the sixth side, and the first side through the bonding wire. A controller-side second bus terminal group electrically connected to the three relay terminal groups, and a rectangular controller chip,
The memory-side first bus terminal group and the controller-side first bus terminal group are arranged in the order of bit numbers, respectively, and are arranged so that the directions in which the bit numbers increase are opposite to each other,
The memory-side second bus terminal group and the controller-side second bus terminal group are arranged in the order of bit numbers, respectively, and the directions in which the bit numbers increase are arranged in the same direction,
The first memory chip is provided on the wiring substrate;
The second memory chip is provided on the first memory chip;
The semiconductor device, wherein the controller chip is provided on the second memory chip. A logic inversion unit that logically inverts the order of bit numbers corresponding to at least one of the controller-side first bus terminal group and the controller-side second bus terminal group;
The semiconductor device according to claim 1, further comprising: A first side part, a second side part facing the first side part, a first relay terminal group and a second relay terminal group respectively arranged on the first side part side, and the first side part A first wiring pattern that connects one relay terminal group and the second relay terminal group, a third relay terminal group and a fourth relay terminal group that are arranged on the second side, and the third A rectangular wiring board having a second wiring pattern connecting the relay terminal group and the fourth relay terminal group;
A third side portion disposed on the first side portion side and the third side portion are arranged along the third side portion, and are electrically connected to the first relay terminal group via a bonding wire. A memory-side first bus terminal group, a rectangular first memory chip,
A fourth side disposed on the second side and the fourth side are arranged along the fourth side, and are electrically connected to the third relay terminal group via a bonding wire. A second memory chip having a rectangular shape having a second bus terminal group on the memory side;
The fifth side portion disposed on the first side portion side and the fifth side portion are arranged along the fifth side portion, and are electrically connected to the second relay terminal group through bonding wires. The first bus terminal group on the controller side, the sixth side disposed on the second side, the array along the sixth side, and the first side through the bonding wire. A rectangular controller chip having a controller-side second bus terminal group electrically connected to the four relay terminal groups;
A logic inverting unit that logically inverts the order of bit numbers corresponding to at least one of the controller-side first bus terminal group and the controller-side second bus terminal group;
A first set of the memory side first bus terminal group and the controller side first bus terminal group, and a second set of the memory side second bus terminal group and the controller side second bus terminal group; As a target, all the terminal groups of the first and second groups are arranged in the order of bit numbers, the first group of terminal groups and the second group of terminal groups, respectively, Arranged in the same direction of increasing bit numbers,
The controller chip is provided on the wiring board,
The first memory chip is provided on the controller chip;
The semiconductor device, wherein the second memory chip is provided on the first memory chip. A first side part, a second side part facing the first side part, a first relay terminal group and a second relay terminal group respectively arranged on the first side part side, and the first side part A first wiring pattern that connects one relay terminal group and the second relay terminal group, a third relay terminal group and a fourth relay terminal group that are arranged on the second side, and the third A rectangular wiring board having a second wiring pattern connecting the relay terminal group and the fourth relay terminal group;
A third side portion disposed on the first side portion side and the third side portion are arranged along the third side portion, and are electrically connected to the first relay terminal group via a bonding wire. A memory-side first bus terminal group, a rectangular first memory chip,
A fourth side disposed on the second side and the fourth side are arranged along the fourth side, and are electrically connected to the third relay terminal group via a bonding wire. A second memory chip having a rectangular shape having a second bus terminal group on the memory side;
The fifth side portion disposed on the first side portion side and the fifth side portion are arranged along the fifth side portion, and are electrically connected to the second relay terminal group through bonding wires. The first bus terminal group on the controller side, the sixth side disposed on the second side, the array along the sixth side, and the first side through the bonding wire. A rectangular controller chip having a controller-side second bus terminal group electrically connected to the four relay terminal groups;
A logic inverting unit that logically inverts the order of bit numbers corresponding to at least one of the controller-side first bus terminal group and the controller-side second bus terminal group;
A first set of the memory side first bus terminal group and the controller side first bus terminal group, and a second set of the memory side second bus terminal group and the controller side second bus terminal group; As a target, all the terminal groups of the first and second groups are arranged in the order of bit numbers, and the terminal groups of the first group and the terminal groups of the second group have bit numbers, respectively. Arranged in increasing directions opposite to each other,
The controller chip and the first memory chip are provided on the wiring board,
The semiconductor device, wherein the second memory chip is provided on the first memory chip. The second memory chip is applied in a state where the first memory chip is rotated 180 degrees in a direction along the surface of the wiring board.
The semiconductor device according to claim 1. A plurality of the first and second memory chips are mounted on the wiring board, respectively.
The semiconductor device according to claim 1.

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