TWI573390B - Operational transconductance amplifier for wide input range application - Google Patents

Description

Transconductance op amp for wide input range applications

The present invention relates to an Operational Transconductance Amplifier (OTA), and more particularly to a transconductance operational amplifier suitable for wide input range applications, wherein a wide input range application includes, for example, an application including a light emitting diode driver.

For a switched LED device, it is required that the LED driver generates a pulse width modulation signal to drive. The pulse width modulator for generating the pulse width modulation signal has a transconductance operational amplifier, and the transconductance operational amplifier amplifies the error between the reference voltage and the feedback voltage generated by the feedback current of the LED The signal is such that the pulse width modulator adjusts the period of duty cycle of the pulse width modulation signal.

Please refer to FIG. 1. FIG. 1 is a schematic circuit diagram of a conventional transconductance operational amplifier. As shown in FIG. 1, the transconductance operational amplifier 1 includes an input stage circuit 10 and a current mirror circuit 12, wherein the input stage circuit 10 is electrically coupled to the current mirror circuit 12. The input stage circuit 10 receives the first input voltage CS (eg, the feedback voltage generated by the feedback current from the LED) and the second input voltage VREF (eg, the reference voltage) through the input transistor pair to be based on the second input. The voltage difference between the voltage VREF and the first input voltage CS changes its bias applied to the current mirror circuit 12, that is, the voltage at the terminals aa, bb is supplied as a bias voltage to the current mirror circuit 12, thereby causing the current mirror Circuit 12 The output signal COMP (for example, an error signal between the reference voltage and the feedback voltage generated by the feedback current of the LED).

Further, the input stage circuit 10 includes a current source S, an input transistor pair and a bias transistor pair, wherein the input transistor pair is composed of two P-type transistors MP1, MP2, and the bias transistor pair is composed of two The N-type transistors MN1, MN2 are composed. The output end of the current source S is electrically connected to the source terminals of the P-type transistors MP1 and MP2, and the gate terminals of the P-type transistors MP1 and MP2 respectively receive the first input voltage CS and the second input voltage VREF, and the P-type transistor MP1. The 汲 extremes of MP2 are respectively the two internal endpoints aa and bb of the electrical input stage circuit 10. The 汲 terminal of the N-type transistor MN1 is electrically connected to the gate terminal of the N-type transistor MN1 and the first bias terminal of the current mirror circuit 12, and is electrically connected to the 汲 terminal of the P-type transistor MP1 through the terminal aA. The 汲 terminal of the N-type transistor MN2 is electrically connected to the gate terminal of the N-type transistor MN2 and the second bias terminal of the current mirror circuit 12, and is electrically connected to the 汲 terminal of the P-type transistor MP2 through the terminal bb. The source terminals of the N-type transistors MN1, MN2 are electrically connected to the ground GND.

The current mirror circuit 12 includes P-type transistors MP3, MP4 and N-type transistors MN5, MN6. The gate terminals of the P-type transistors MP3 and MP4 are electrically connected to each other, and the source terminals of the P-type transistors MP3 and MP4 are electrically connected to the voltage terminal VDD of the system. The 汲 terminal of the P-type transistor MP3 is electrically connected to the gate terminal of the P-type transistor MP3 and the 汲 terminal of the N-type transistor MN5, and the 汲 terminal of the P-type transistor MP4 is electrically connected to the 汲 terminal of the N-type transistor MN6. The gate terminals of the N-type transistors MN5 and MN6 are electrically connected to the gate terminals of the N-type transistors MN1 and MN2, respectively, to serve as the first bias terminal and the second bias terminal of the current mirror circuit 12, respectively. The source terminals of the N-type transistors MN5 and MN6 are electrically connected to the ground GND.

When the transconductance operational amplifier 1 is applied to a general DC voltage converter (DC/DC converter), there is no difference in the foot space of the input stage circuit 10 due to the excessive difference between the second input voltage VREF and the first input voltage CS. (foot room) The swing is too large. In other words, the 汲 extreme/source extreme voltages V _DS1 and V _{DS2 of the} P-type transistors MP1, MP2 do not coincide. However, in an LED driver application, the second input voltage VREF may be 0.2 volts, while the first input voltage may have an average voltage of 0.2 volts and a maximum swing voltage of 1 volt triangular wave voltage signal, therefore, P-type The 汲 extreme/source extreme voltages V _DS1 and V _{DS2 of the} transistors MP1, MP2 (corresponding to the voltages of the terminals aa and bb) do not coincide. The 汲 extreme/source extreme voltages V _DS1 and V _{DS2 of the} P-type transistors MP1 and MP2 determine the transconductance coefficients g _m1 and g _{m2 of the} P-type transistors MP1 and MP2, respectively, and cause the current mirror circuits MN1, MN5 and MN2, MN6. If the replica current shift is caused by the channel length modulation, if the 汲 extreme/source extreme voltages V _DS1 and V _{DS2 of the} P-type transistors MP1 and MP2 are inconsistent, the output signal COMP will be shifted ( Offset).

Embodiments of the present invention provide a transconductance operational amplifier suitable for wide input range applications, the transconductance operational amplifier including an input stage circuit, a current mirror circuit, and a voltage latching pair. The input stage circuit includes an input transistor pair and a bias transistor pair, and the input transistor pair is electrically connected to the bias transistor pair through the two ends of the input stage circuit. The first bias end and the second bias end of the current mirror circuit are electrically connected to the two ends. The voltage latching pair has a first latching circuit and a second latching circuit. The first latching circuit and the second latching circuit are electrically connected to a ground terminal or a system voltage terminal, and are electrically connected to the bias transistor. Yes, and electrically connect the two ends. The first latch circuit and the second latch circuit are used to latch the voltage at the two ends to a specific voltage or to make the voltages at the two ends different from each other.

Accordingly, the transconductance operational amplifier provided by the embodiment of the present invention does not have an offset of the output signal even when the difference between the two input voltages received by the input stage circuit is large, so the transconductance The op amp has high accuracy and is suitable for wide input range applications.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

1~5‧‧‧transconductance operational amplifier

10, 20, 30, 40, 50‧‧‧ input stage circuits

12, 22, 32, 42, 52‧‧‧ current mirror circuit

24, 34, 44, 54‧‧‧ voltage latching pairs

Aa, bb‧‧‧ endpoint

Agnda, agndb, vdda, vddb‧‧‧ endpoints

OP1, OP2‧‧‧ amplifier

S‧‧‧current source

VDD‧‧‧ system voltage terminal

GND‧‧‧ ground terminal

MN1~MN8‧‧‧N type transistor

MP1~MP8‧‧‧P type transistor

CS‧‧‧First input voltage

VREF‧‧‧second input voltage

COMP‧‧‧ output signal

Vb‧‧‧specific voltage

1 is a circuit diagram of a conventional transconductance operational amplifier.

2A is a circuit diagram of a transconductance operational amplifier according to an embodiment of the present invention.

2B is a circuit diagram of a transconductance operational amplifier according to another embodiment of the present invention.

3A is a circuit diagram of a transconductance operational amplifier according to another embodiment of the present invention.

3B is a circuit diagram of a transconductance operational amplifier according to another embodiment of the present invention.

Various illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these exemplary embodiments are provided so that this invention will be in the In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout, and the term "or" as used herein may include all combinations of any one or more of the associated listed items.

Embodiments of the present invention provide a transconductance operational amplifier suitable for a wide input range application. Even if the difference between two input voltages received by the input stage circuit is large, the output signal of the transconductance operational amplifier is not biased accordingly. shift. The transconductance operational amplifier includes an input stage circuit, a current mirror circuit, and a voltage latching pair. The input stage circuit comprises an input transistor pair, a bias transistor pair and a current source, the current source is electrically connected to the input transistor pair, the input transistor is electrically connected to the bias transistor pair, and the bias transistor is electrically connected Current mirror circuit. The voltage latching pair has two voltage latching circuits, and the biasing transistor pair is electrically connected to the grounding terminal or the system voltage terminal through the two voltage latching circuits, respectively. The two voltage latching circuits are also electrically connected to the two ends between the input transistor pair and the bias transistor pair, respectively, thereby thereby connecting the two ends between the input transistor pair and the bias transistor pair The voltage at the point is maintained at a specific voltage or the two endpoints are The voltages are the same as each other.

The voltage latch pair is essentially a pair of negative feedback circuit architectures for latching the voltages at the two terminals between the input transistor pair and the bias transistor pair, such that the input transistor pair The input terminal's 汲 extreme/source extreme voltage and transconductance coefficient will be the same, without the problem of offset of the output signal. Each voltage latching circuit of the voltage latching pair includes an amplifier and a switching transistor, wherein a gate terminal of the switching transistor receives a voltage signal output by the amplifier, and a 汲 terminal of the switching transistor is electrically connected to the bias transistor pair One end of the corresponding bias transistor, the source terminal of the switching transistor is electrically connected to the ground terminal or the system voltage terminal, the positive input terminal of the amplifier is electrically connected to the corresponding end point, and the negative input terminal of the amplifier is electrically connected to the specific voltage. Or the corresponding other endpoint. In this way, the voltage at the two terminals between the input transistor pair and the bias transistor pair will be maintained at a specific voltage, or the voltages at the two terminals will be identical to each other, and the input transistor pair can be avoided. The 汲 extreme/source extreme voltages (or transconductance coefficients) of the two input transistors do not coincide with each other.

Please refer to FIG. 2A. FIG. 2A is a circuit diagram of a transconductance operational amplifier according to an embodiment of the present invention. The transconductance operational amplifier 2 includes an input stage circuit 20, a current mirror circuit 22 and a voltage latching pair 24, wherein the input stage circuit 20 is electrically coupled to the current mirror circuit 22 and the voltage latching pair 24, and the input stage circuit 20 is permeable to voltage latching. Connect 24 to ground GND. The transconductance operational amplifier 2 can be adapted for wide input range applications, such as in the application of a light emitting diode driver, but the invention is not limited thereto.

The input stage circuit 20 receives the first input voltage CS and the second input voltage VREF, wherein the second input voltage VREF may be a reference voltage, for example, 0.2 volts, and the first input voltage CS may be a reference voltage that is an average voltage of the triangular wave voltage signal. For example, a triangular wave voltage signal with a maximum of 1 volt is oscillated with a minimum voltage of -0.3 volts and a maximum of 0.8 volts, respectively. The input stage circuit 20 generates two bias voltages (voltages of the terminals aa, bb) according to the first input voltage CS and the second input voltage VREF, respectively, at the first bias end and the second bias end of the current mirror circuit 22, and Current mirror circuit 22 produces an output signal COMP based on the two bias voltages.

In order to avoid inconsistency between the 汲 extreme/source extreme voltages V _DS1 and V _DS2 of the paired input transistors MP1, MP2 in the input stage circuit 20 (ie, avoiding the inconsistency of the transconductance coefficients g _m1 , g _{m2 of the} input transistors MP1, MP2) The output signal COMP is shifted, and the voltage latching pair 24 is transmitted through a pair of negative feedback circuits, and the two terminals aa, bb inside the input stage circuit 20 are latched at a specific voltage Vb.

The input stage circuit 20 includes a current source S, an input transistor pair and a bias transistor pair, wherein the input transistor pair is composed of two input transistors MP1, MP2 (eg, a P-type transistor), and a bias transistor pair It consists of two bias transistors MN1, MN2 (for example, an N-type transistor). The output end of the current source S is electrically connected to the source terminals of the input transistors MP1 and MP2, and the gate terminals of the input transistors MP1 and MP2 respectively receive the first input voltage CS and the second input voltage VREF, and are input to the transistors MP1 and MP2. The two internal end points aa and bb of the electrical input stage circuit 20 are respectively extreme. The 汲 terminal of the bias transistor MN1 is electrically connected to the gate terminal of the bias transistor MN1 and the first bias terminal of the current mirror circuit 22, and is electrically connected to the 汲 terminal of the input transistor MP1 through the terminal aA. The 汲 terminal of the bias transistor MN2 is electrically connected to the gate terminal of the bias transistor MN2 and the second bias terminal of the current mirror circuit 22, and is electrically connected to the 汲 terminal of the input transistor MP2 through the terminal bb. The source terminals of the bias transistors MN1 and MN2 are electrically connected to both ends of the voltage latching pair 24 (end points agnda, agndb), and are electrically connected to the ground GND through the voltage latching pair 24.

The current mirror circuit 22 includes P-type transistors MP3, MP4 and N-type transistors MN5, MN6. The gate terminals of the P-type transistors MP3 and MP4 are electrically connected to each other, and the source terminals of the P-type transistors MP3 and MP4 are electrically connected to the voltage terminal VDD of the system. The 汲 terminal of the P-type transistor MP3 is electrically connected to the gate terminal of the P-type transistor MP3 and the 汲 terminal of the N-type transistor MN5, and the 汲 terminal of the P-type transistor MP4 is electrically connected to the 汲 terminal of the N-type transistor MN6. The gate terminals of the N-type transistors MN5, MN6 are electrically connected to the gate terminals of the bias transistors MN1, MN2, respectively, to serve as the first bias terminal and the second bias terminal of the current mirror circuit 22, respectively. The source terminals of the N-type transistors MN5 and MN6 are electrically connected to both ends of the voltage latching pair 24 (end points agnda, agndb), and are transmitted through The voltage latch pair 24 is electrically connected to the ground GND.

The voltage latch pair 24 includes two voltage latch circuits, one of which is comprised of an amplifier OP1 and a switching transistor MN7, and the other voltage latch circuit is comprised of an amplifier OP2 and a switching transistor MN8. In this embodiment, the switching transistors MN7, MN8 are, for example, N-type transistors. The gate terminals of the switching transistors MN7, MN8 are electrically connected to the output terminals of the amplifiers OP1, OP2, respectively, to receive the voltage signals output by the amplifiers OP1, OP2, respectively. The source terminals of the switching transistors MN7 and MN8 are electrically connected to the ground GND, and the 汲 terminals of the switching transistors MN7 and MN8 are electrically connected to the terminals agnda and agndb, respectively, so that the 电 terminal of the switching transistor MN7 is electrically connected to the N-type. The transistor MN5 is connected to the source terminal of the bias transistor MN1, and the anode of the switching transistor MN8 is electrically connected to the source terminals of the N-type transistor MN6 and the bias transistor MN2. In addition, the negative input terminals of the amplifiers OP1 and OP2 are electrically connected to the specific voltage Vb, and the positive input terminals of the amplifiers OP1 and OP2 are electrically connected to the terminals aa and bb, respectively.

Through the above connection relationship, it can be known that the voltage latch is a negative feedback circuit structure. Therefore, at steady state, the voltage on the positive input terminals of the amplifiers OP1 and OP2 should be equal to the specific voltage Vb, that is, the terminal aa and The voltage on bb will be equal to the specific voltage Vb, and the excess voltage will be absorbed by the switching transistors MN7 and MN8 (corresponding to the voltages at the terminals agnda and agndb). Since the voltages at the terminals aa and bb are equal to the specific voltage Vb, the input transistors MP1 and MP2 are identical in their extreme/source extreme voltages V _DS1 , V _DS2 (ie, the transconductance coefficients of the input transistors MP1, MP2 are made). g _m1 and g _{m2 are} identical), thereby avoiding an offset of the output signal COMP due to an excessive voltage difference between the first input voltage CS and the second input voltage VREF.

Please refer to FIG. 2B. FIG. 2B is a circuit diagram of a transconductance operational amplifier according to another embodiment of the present invention. In FIG. 2B, transconductance operational amplifier 30 includes an input stage circuit 30, a current mirror circuit 32, and a voltage latching pair 34. In this embodiment, the input stage circuit 30 and the current mirror circuit 32 are the same as the input stage circuit 20 and the current mirror circuit 22 of FIG. 2A, respectively, and therefore will not be described again. Compared to the voltage latch pair 24 of FIG. 2A, the negative inputs of the amplifiers OP1 and OP2 in the voltage latching pair 34 of FIG. 2B are not receiving the specific voltage Vb, but are connected to the terminals bb and aa, respectively, so that The voltages of the endpoints aa and bb are identical to each other. In this way, the input/transmission source voltages V _DS1 and V _{DS2 of} the input transistors MP1 and MP2 can be identical (that is, the transconductance coefficients g _m1 and g _{m2 of} the input transistors MP1 and MP2 are matched), thereby The offset of the output signal COMP due to the excessive voltage difference between the first input voltage CS and the second input voltage VREF is avoided.

Please refer to FIG. 3A. FIG. 3A is a circuit diagram of a transconductance operational amplifier according to another embodiment of the present invention. The transconductance operational amplifier 4 includes an input stage circuit 40, a current mirror circuit 42 and a voltage latching pair 44, wherein the input stage circuit 40 is electrically coupled to the current mirror circuit 42 and the voltage latching pair 44, and the input stage circuit 40 is permeable to voltage latching. The pair 44 is electrically connected to the system voltage terminal VDD. Transconductance operational amplifier 4 can be adapted for wide input range applications, such as in the application of light emitting diode drivers, although the invention is not limited thereto.

The input stage circuit 40 receives the first input voltage CS and the second input voltage VREF, wherein the second input voltage VREF can be a reference voltage. In order to avoid inconsistency of the 汲 extreme/source extreme voltages V _DS1 , V _DS2 of the paired input transistors MN1, MN2 in the input stage circuit 40 (ie, to avoid inconsistencies in the transconductance coefficients g _m1 , g _{m2 of the} input transistors MP1, MP2) The output signal COMP is shifted, and the voltage latching pair 44 is transmitted through a pair of negative feedback circuits, and the two terminals aa, bb inside the input stage circuit 40 are latched at a specific voltage Vb.

The input stage circuit 40 includes a current source S, an input transistor pair and a bias transistor pair, wherein the input transistor pair is comprised of two input transistors MN1, MN2 (eg, an N-type transistor), and a bias transistor pair It consists of two bias transistors MP1, MP2 (for example, a P-type transistor). The output terminal of the current source S is electrically connected to the source terminals of the input transistors MN1 and MN2, and the gate terminals of the input transistors MN1 and MN2 respectively receive the first input voltage CS and the second input voltage VREF, and input to the transistors MN1 and MN2. The two internal end points aa and bb of the extreme electrical input stage circuit 40 are respectively extreme. The 汲 terminal of the bias transistor MP1 is electrically connected to the bias transistor MP1 The gate terminal is connected to the first bias end of the current mirror circuit 42 and is electrically connected to the drain terminal of the input transistor MN1 through the terminal connection point aa. The 汲 terminal of the bias transistor MP2 is electrically connected to the gate terminal of the bias transistor MP2 and the second bias terminal of the current mirror circuit 42, and is electrically connected to the 汲 terminal of the input transistor MN2 through the terminal bb. The source terminals of the biasing transistors MP1 and MP2 are electrically connected to the two ends of the voltage latching pair 44, vdda, vddb, and are electrically connected to the system voltage terminal VDD through the voltage latching pair 44.

The current mirror circuit 42 includes N-type transistors MN3, MN4 and P-type transistors MP5, MP6. The gate terminals of the N-type transistors MN3 and MN4 are electrically connected to each other, and the source terminals of the N-type transistors MN3 and MN4 are electrically connected to the ground GND. The 汲 terminal of the N-type transistor MN3 is electrically connected to the 极端 terminal of the N-type transistor MN3 and the 汲 terminal of the P-type transistor MP5, and the 汲 terminal of the N-type transistor MN4 is electrically connected to the 汲 terminal of the P-type transistor MP6. The gate terminals of the P-type transistors MP5 and MP6 are electrically connected to the gate terminals of the bias transistors MP1 and MP2, respectively, to serve as the first bias terminal and the second bias terminal of the current mirror circuit 22, respectively. The source terminals of the P-type transistors MP5 and MP6 are electrically connected to the two ends of the voltage latching pair 44, vdda, vddb, and are electrically connected to the system voltage terminal VDD through the voltage latching pair 44.

The voltage latching pair 44 includes two voltage latching circuits, one of which is comprised of an amplifier OP1 and a switching transistor MP7, and the other voltage latching circuit is comprised of an amplifier OP2 and a switching transistor MP8. In this embodiment, the switching transistors MP7, MP8 are, for example, P-type transistors. The gate terminals of the switching transistors MP7 and MP8 are electrically connected to the output terminals of the amplifiers OP1 and OP2, respectively, to receive the voltage signals output by the amplifiers OP1 and OP2, respectively. The source terminals of the switching transistors MP7 and MP8 are electrically connected to the voltage terminal VDD of the system, and the 汲 terminals of the switching transistors MP7 and MP8 are electrically connected to the terminals vdda and vddb, respectively, so that the 汲 terminal of the switching transistor MP7 is electrically connected. The type of transistor MP5 and the source terminal of the bias transistor MP1, and the anode of the switching transistor MP8 are electrically connected to the source terminals of the P-type transistor MP6 and the bias transistor MP2. In addition, the negative input terminals of the amplifiers OP1 and OP2 are electrically connected to the specific voltage Vb, and the positive input terminals of the amplifiers OP1 and OP2 are electrically connected to the terminal aa respectively. With bb.

Through the above connection relationship, it can be known that the voltage latch is a negative feedback circuit structure. Therefore, at steady state, the voltage on the positive input terminals of the amplifiers OP1 and OP2 should be equal to the specific voltage Vb, that is, the terminal aa and The voltage on bb will be equal to the specific voltage Vb, and the excess voltage will be absorbed by the switching transistors MP7 and MP8 (corresponding to the voltages at the terminals vdda, vddb). Since the voltages at the terminals aa and bb are equal to the specific voltage Vb, the input transistors MP1 and MP2 are identical in their extreme/source extreme voltages V _DS1 , V _DS2 (ie, the transconductance coefficients of the input transistors MP1, MP2 are made). g _m1 and g _{m2 are} identical), thereby avoiding an offset of the output signal COMP due to an excessive voltage difference between the first input voltage CS and the second input voltage VREF.

Please refer to FIG. 3B. FIG. 3B is a circuit diagram of a transconductance operational amplifier according to another embodiment of the present invention. In FIG. 3B, transconductance operational amplifier 50 includes an input stage circuit 50, a current mirror circuit 52, and a voltage latching pair 54. In this embodiment, the input stage circuit 50 and the current mirror circuit 52 are the same as the input stage circuit 40 and the current mirror circuit 42 of FIG. 3A, respectively, and therefore will not be described again. Compared to the voltage latching pair 44 of FIG. 3A, the negative inputs of the amplifiers OP1 and OP2 in the voltage latching pair 54 of FIG. 3B are not receiving a specific voltage Vb, but are connected to the terminals bb and aa, respectively, so that The voltages of the endpoints aa and bb are identical to each other. In this way, the input/transmission source voltages V _DS1 and V _{DS2 of} the input transistors MN1 and MN2 can be identical (that is, the transconductance coefficients g _m1 and g _{m2 of} the input transistors MN1 and MN2 are matched), thereby The offset of the output signal COMP due to the excessive voltage difference between the first input voltage CS and the second input voltage VREF is avoided.

In summary, the transconductance operational amplifier provided by the embodiment of the present invention locks two internal terminals of the input stage circuit to a specific voltage or the voltages of the two end points are identical to each other through a voltage latching pair. The extreme input/source extreme voltages V _DS1 , V _DS2 of the two input transistors in the input stage circuit are identical (ie, the transconductance coefficients g _m1 , g _{m2 of} the input transistor are made uniform). As such, the output voltage of the transconductance operational amplifier is not offset by the difference between the first input voltage and the second input voltage, that is, the transconductance operational amplifier is suitable for wide input range applications.

The above description is only the preferred embodiment of the present invention, but the features of the present invention are not limited thereto, and any one skilled in the art can easily change or modify it in the field of the present invention. Covered in the following patent scope of this case.

2‧‧‧Transconductance operational amplifier

20‧‧‧Input stage circuit

22‧‧‧current mirror circuit

24‧‧‧Voltage latching pair

Aa, bb, agnda, agndb‧‧‧ endpoint

OP1, OP2‧‧‧ amplifier

S‧‧‧current source

VDD‧‧‧ system voltage terminal

GND‧‧‧ ground terminal

MN1, MN2, MN5, MN6, MN7, MN8‧‧‧N type transistor

MP1~MP4‧‧‧P type transistor

CS‧‧‧First input voltage

VREF‧‧‧second input voltage

COMP‧‧‧ output signal

Vb‧‧‧specific voltage

Claims (9)

A transconductance operational amplifier suitable for a wide input range application includes: an input stage circuit having two ends therein, including an input transistor pair and a bias transistor pair, the input transistor pair transmitting the two The terminal is electrically connected to the bias transistor pair; a current mirror circuit has a first bias terminal and a second bias terminal, and the first bias terminal and the second bias terminal are respectively electrically Connecting the two ends; a voltage latching pair having a first latching circuit and a second latching circuit, the first latching circuit and the second latching circuit being electrically connected to a ground a terminal or a system voltage terminal electrically connected to the bias transistor pair and electrically connected to the two end points, wherein the first latch circuit and the second latch circuit are used to connect the two The voltage on the terminal latches at a particular voltage, or causes the voltages at the two ends to be identical to each other; wherein the first latch circuit includes a first amplifier and a first switching transistor, and the second latch The lock circuit includes a second amplifier and a second switch transistor, the first switch transistor The gate terminals of the second switching transistor are electrically connected to the output ends of the first amplifier and the second amplifier, respectively, and the first switching transistor is electrically connected to the second terminal of the second switching transistor. The pair of bias transistors, the first switch transistor and the source terminal of the second switch transistor are electrically connected to the ground terminal or the system voltage terminal, the first amplifier and the first The positive input terminals of the two amplifiers are electrically connected to a first end point and a second end point of the two end points, respectively, and the first amplifier and the negative input end of the second amplifier are electrically connected to the specific The voltage is electrically connected to the second end point and the first end point respectively. The transconductance operational amplifier of claim 1, wherein the input transistor pair is composed of a first input transistor and a second input transistor, the bias transistor pair being biased by a first The transistor is composed of a second bias transistor, and the input stage circuit further includes a current source, wherein the current source is electrically connected to the a first input transistor and a source terminal of the second input transistor, the first input transistor and the gate of the second input transistor respectively receiving a first input voltage and a second input voltage, The first input transistor and the second terminal of the second input transistor are electrically connected to the first bias transistor and the second bias through the first end point and the second end point, respectively a first terminal of the transistor, the first bias transistor and the gate of the second bias transistor being electrically connected to the first terminal and the second terminal, and the first bias transistor And a source terminal of the second bias transistor is electrically connected to a first terminal of the first switching transistor and the second switching transistor, respectively. The transconductance operational amplifier of claim 2, wherein the current mirror circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor, the first transistor and the The 电 of the second transistor is electrically connected to the voltage terminal or the ground of the system, and the gates of the first transistor and the second transistor are electrically connected to each other, and the 电 of the first transistor Extremely electrically connecting the gate terminal of the first transistor to the 汲 terminal of the third transistor, the 汲 terminal of the second transistor being electrically connected to the 汲 terminal of the fourth transistor, the third The transistor and the gate terminal of the fourth transistor are electrically connected to the first end point and the second end point, respectively, and the third transistor is electrically connected to the source end of the fourth transistor respectively The first switching transistor and the second terminal of the second switching transistor. The transconductance operational amplifier of claim 3, wherein the first input transistor, the second input transistor, the first transistor, and the second transistor are P-type transistors, The first bias transistor, the second bias transistor, the third transistor, the fourth transistor, the first switching transistor and the second switching transistor are N-type a transistor, the source of the first switching transistor and the second switching transistor being electrically connected to the ground, and a source of the first transistor and the second transistor Sexually connected to the voltage terminal of the system. The transconductance operational amplifier of claim 3, wherein the first input transistor, the second input transistor, the first transistor, and the second transistor are N-type transistors, The first bias transistor, the second bias transistor, the third transistor, the fourth transistor, the first switching transistor and the second switching transistor are P-type a transistor, the source of the first switching transistor and the second switching transistor being electrically connected to the voltage terminal of the system, and a source terminal of the first transistor and the second transistor Electrically connecting the ground terminal. The transconductance operational amplifier of claim 2, wherein the second input voltage is a reference voltage, and the first reference voltage is an average voltage of a triangular wave voltage signal. The transconductance operational amplifier of claim 1, wherein the input stage circuit generates two bias voltages to the current mirror circuit according to a received first input voltage and a second input voltage, and The current mirror circuit generates an output signal at one end of the current mirror circuit in accordance with the two bias voltages. The transconductance operational amplifier of claim 3, wherein the fourth terminal of the fourth transistor produces an output signal. The transconductance operational amplifier of claim 1, wherein the wide input range is applied as an application of a light emitting diode driver.