TW201926886A - Compensation circuit for input voltage offset of error amplifier - Google Patents

Abstract

A compensation circuit for compensating an input voltage offset of an error amplifier has a level shifter, a first trimming circuit, a second trimming circuit, and a compensation current sinking device. The level shifter shifts levels of a feedback voltage and a predetermined reference voltage and outputs a level shifted feedback voltage and a level shifted reference voltage. The first trimming circuit adjusts the level shifted reference voltage by trimming a first resistance thereof according to a trimming code, wherein the trimming code has the ratio relation of the input voltage offset and a resistance to be trimmed. The second trimming circuit adjusts the level shifted feedback voltage by trimming a second resistance thereof according to a trimming code. The compensation current sinking device sinks currents passing through the first and second trimming circuits.

Description

Compensation circuit for compensating the input voltage offset of the error amplifier

The present invention relates to an error amplifier circuit, and more particularly to a compensation circuit for compensating for an input voltage offset of an error amplifier and an error amplifier circuit having the compensation circuit.

Switched light-emitting diode (LED) drivers currently on the market operate in boundary current mode (BCM) and also have a closed loop circuit for locking the LED current. Referring to Figure 1A, Figure 1A is a schematic illustration of a conventional switch mode LED driver. The conventional switch mode LED driver 1 includes a current-voltage converter 11, an error amplifier EA, a compensation capacitor C_COMP, and a comparator CMP. The current-to-voltage converter 11 is connected to an error amplifier EA which is connected to a compensation capacitor C_COMP and a comparator CMP.

The LED current iLED (ie, the current through the LED) is fed back to the switch mode LED driver 1, and the current-voltage converter 11 receives the LED current iLED and converts the LED current iLED into a feedback voltage CS, wherein the LED current iLED is a triangular wave signal, Therefore, the feedback voltage CS is also a triangular wave signal. The error amplifier EA receives the feedback voltage CS and the reference voltage VREF, and then compares the feedback voltage CS with the reference voltage VREF to generate the error signal COMP accordingly. The compensation capacitor C_COMP is connected between the output of the error amplifier EA and the ground voltage GND for compensating for the error signal COMP. The comparator CMP compares the error signal COMP with the sawtooth signal V_SAW to generate a pulse signal DUTY for modulating the LED current iLED.

Referring to Figure 1B, Figure 1B is a schematic diagram of an error amplifier. The error amplifier EA includes a current source IS, NMOS transistors MN1 to MN4, and PMOS transistors MP1 to MP4. The source terminals of the PMOS transistors MP3 and MP4 are connected to a high voltage (for example, a system voltage), the gate terminals of the PMOS transistors MP3 and MP4 are connected to each other, and the NMOS terminals of the PMOS transistors MP3 and MP4 are respectively connected to the gates of the PMOS transistor MP3. Extreme and compensation capacitor C_COMP one end.

The source terminals of the NMOS transistors MN1 to MN4 are connected to a low voltage (for example, a ground voltage), the gate terminals of the NMOS transistors MN1 and MN3 are connected to each other, and the gate terminals of the NMOS transistors MN2 and MN4 are connected to each of the NMOS transistors MN3 and The 汲 terminal of MN1 is connected to the 汲 terminal of PMOS transistor MP3 and the gate terminal of NMOS transistor MN1, respectively, and the 汲 terminals of NMOS transistors MN4 and MN2 are respectively connected to the 汲 terminal of PMOS transistor MP4 and the gate terminal of NMOS transistor MN2, respectively. .

The source terminals of the PMOS transistors MP1 and MP2 are connected to the current source IS, the gate terminals of the PMOS transistors MP1 and MP2 receive the feedback voltage CS and the reference voltage VREF, respectively, and the 汲 terminals of the PMOS transistors MP1 and MP2 are respectively connected to the NMOS transistor. The 汲 extremes of MN1 and MN2. The PMOS transistors MP1 and MP2 are used as differential pair circuits, and the NMOS transistors MN1 and MN2 are used as active load circuits.

The error amplifier EA must allow a large input differential signal formed by the feedback voltage CS and the reference voltage VREF. To ensure that the error amplifier EA can tolerate a large differential signal, the error amplifier EA should have a small transconductance Gm, and the differential pair circuit and the active load circuit should have small transconductances Gm1 and Gm2, respectively. However, the mismatch of the active load circuit (ie, voltage offset Vos2) is reflected to the input voltage offset Vos2' of the differential pair circuit, ie Vos2' = Vos2 * Gm2 / Gm1, so the error amplifier EA for small transconductance Gm operation Causes a larger input offset.

In order to heal the defect of the input voltage offset (ie, reduce the input voltage offset), one way is to increase the area of the error amplifier EA. However, in current applications, the reference voltage VREF of a conventional switch mode LED driver is required to be 200 microvolts with a tolerance of ± 3%, thus requiring a small voltage offset.

Referring to FIG. 2A, FIG. 2A is a schematic diagram of a conventional compensation circuit for compensating for an input voltage offset of an error amplifier. The conventional compensation circuit 2 includes a bandgap voltage generator 21, a trimming circuit 22, switches SW1, SW2, and a dimming control circuit 23. The bandgap voltage generator 21 is connected to the trimming circuit 22, the switch SW1 is connected to the trimming circuit 22 and the error amplifier EA, and the switch SW2 is connected to the dimming control circuit 23 and the error amplifier EA.

The bandgap voltage generator 21 is for generating a bandgap voltage to the trimming circuit 21. The trimming circuit 21 has resistors R1 to R4 connected in series, and also has fuses F1 and F2, wherein the fuse F1 is connected in parallel to the resistor R2, and the fuse F2 is connected in parallel to the resistor R3. The junction of resistors R2 and R3 is coupled to error amplifier EA to provide a reference voltage VREF to error amplifier EA.

The bandgap voltage is input to the trimming circuit 21. When the input voltage offset Vos is not present, the fuses F1 and F2 are not blown, so that the reference voltage VREF is the divided voltage generated by the voltage division of the bandgap voltage by the resistors R1 and R4. When the input voltage offset Vos is present, at least one of the fuses F1 and F2 is blown, and the reference voltage VREF is the energy gap by the resistors "R1, R2, R4", "R1, R3, R4" or "R1 to R4". The voltage division produces a partial voltage to compensate for the input voltage offset Vos. For example, when the required reference voltage VREF is 200 microvolts and the input voltage offset Vos is -20 microvolts, at least one of the fuses F1 and F2 is blown to compensate for -20 microvolts, so the actual reference voltage VREF is increased to 220 microvolts.

When the dimming function is disabled, the switch SW1 is turned on, so the reference voltage VREF whose input voltage offset Vos has been compensated is input to the error amplifier. When the dimming function is enabled, the switch SW2 is turned on. The dimming control circuit 23 has an analog dimming ratio curve defining the relationship between the input analog signal AND and the reference voltage VREF, and thus the dimming control circuit 23 converts the input analog signal AND into the reference voltage VREF based on the analog dimming ratio curve.

Referring to Figure 2B, Figure 2B is a graph of an analog dimming ratio curve. The ideal analog dimming ratio curve of the dimming control circuit 23 is as shown in FIG. 2B. However, the analog dimming ratio curve shifts up or down due to the presence of the input voltage offset Vos. That is, the trimming circuit 21 cannot help the dimming control circuit 23 to compensate for the influence of the input voltage offset Vos, and the dimming control circuit 23 should adjust the ideal analog dimming example ratio curve to handle the influence of the input voltage offset Vos.

Note here that for analog dimming as shown in Figures 2A and 2B, the actual reference voltage VREF for dimming can be expressed as VREF = (AND - 0.2) + Vos. In addition, while using pulse width modulation (PWM) dimming, the input voltage offset Vos still affects PWM dimming. The actual reference voltage VREF of dimming can be expressed as VREF = (VREF _IDEAL + Vos) * DUTY, where ideal The reference voltage is expressed as VREF _IDEAL and the duty cycle is expressed as DUTY. In short, the above-mentioned trimming method of compensating for the input voltage offset cannot be applied in the dimming function.

There are other compensation compensation circuits on the market for compensating for the input voltage offset of the error amplifier. However, in each of the above commercially available compensation circuits, the current source of the error amplifier must be the same as the compensation current source, and the offset current must be known before compensation, and more than two transistors in the compensation circuit should be Designed to match. Unfortunately, the offset current is not readily known as the process changes, and the design used to match more than two transistors is not easy.

An exemplary embodiment of the present invention provides a compensation circuit for compensating for an input voltage offset of an error amplifier, and the compensation circuit includes a quasi-displacer, a first trim circuit, a second trim circuit, and a compensation current sink. The quasi-displacer is configured to shift the level of the feedback voltage and the level of the predetermined reference voltage, thereby outputting the quasi-displacement feedback voltage and the quasi-displacement reference voltage. The first trimming circuit is connected to the quasi-displacer and the error amplifier for trimming the first resistance value according to the trimming code to adjust the quasi-displacement bit reference voltage, wherein the trimming code has an input voltage offset and a resistance value to be trimmed Ratio relationship. The second trimming circuit is connected to the quasi-displacer and the error amplifier for trimming the second resistance value according to the trimming code to adjust the quasi-displacement feedback voltage. A compensation current absorbing device is coupled to the first and second trimming circuits for absorbing current through the first and second trimming circuits.

Exemplary embodiments of the present invention also provide an error amplifier circuit including an error amplifier and the above-described compensation circuit.

In summary, because only two transistors must be designed to match, and only the resistors must be designed to match, the compensation circuit provided to compensate for the input voltage offset of the error amplifier can be easily designed, and Has a smaller area.

The objects, features, and concepts of the present invention will be more fully understood and understood by the appended claims. However, the following detailed description and drawings are merely for the purpose of illustration

Reference will now be made in detail to the exemplary embodiments embodiments embodiments Wherever possible, the same reference numerals are in the

An exemplary embodiment of the present invention provides a compensation circuit for use in an error amplifier circuit, and the compensation circuit can compensate for an input voltage offset of an error amplifier in the error amplifier circuit. The compensation circuit compensates for the input voltage offset in front of the input of the error amplifier, so that only the input voltage offset needs to be measured during circuit detection. Then, the trimming code of the input voltage offset can be calculated, wherein the trimming code records the ratio of the input voltage offset to the resistance value to be trimmed.

In an exemplary embodiment of the invention, the resistors should be designed to match each other and only two transistors must be designed to match each other. Therefore, the matching design of the compensation circuit in the exemplary embodiment of the present invention is easier than the matching design of the conventional compensation circuit. Furthermore, since it is only necessary to design the two transistors to match each other, in the exemplary embodiment, the circuit area of the compensation circuit can be reduced, and the operating point and compensation current of other transistors can be ignored.

The compensation circuit in the exemplary embodiment of the present invention includes a quasi-displacer, a first trimming circuit, a second trimming circuit, and a compensating current sinking device. The quasi-bit shifter receives the predetermined reference voltage and the feedback voltage generated by the LED current, and outputs the reference voltage and the feedback voltage of the quasi-displaced bit to the first and second trimming circuits, respectively. Each of the first and second trimming circuits has a plurality of resistors connected in series and a plurality of fuses connected in parallel to the plurality of resistors. A compensation current absorbing device is coupled to the first and second trimming circuits to absorb the compensation current.

The trimming code records the ratio of the input voltage offset to the resistance of the first or second trimming circuit to be trimmed. The fuse in the first or second trimming circuit is blown according to the trimming code, so the first or second trimming circuit can trim the quasi-displacement bit reference voltage (reference voltage after the quasi-displacement bit) or the quasi-displacement feedback voltage (The feedback voltage after the quasi-displacement bit) to output the trimming reference voltage (trimmed reference voltage) or the trimming feedback voltage (trimmed feedback voltage) to the error amplifier. Since the level shift reference voltage or the quasi-bit shift feedback voltage is trimmed, the input voltage offset can be compensated.

Please refer to FIG. 3, which is a schematic diagram of an error amplifier circuit of an exemplary embodiment of the present invention. The error amplifier circuit includes an error amplifier EA and a compensation circuit 3. The compensation circuit 3 is connected to the error amplifier EA and outputs a trim reference voltage (ie VREF + Vos) and a quasi-bit shift feedback voltage to the error amplifier EA (when the input voltage offset is positive), or alternatively, the output level Shift the reference voltage and trim the feedback voltage to the error amplifier EA (when the input voltage offset is negative).

The compensation circuit 3 includes a bandgap voltage generator 31, a voltage divider 32, a first trimming circuit 33, a second trimming circuit 34, a quasi-displacer 35, and a compensating current sinking device 36. The bandgap voltage generator 31 is connected to the quasi-displacer 35, which is connected to the first trimming circuit 33 and the second trimming circuit 34. The first trimming circuit 33 and the second trimming circuit 34 are connected to the error amplifier EA and the compensating current sinking device 36.

The bandgap voltage generator 31 is for providing a bandgap voltage. The voltage divider 32 divides the bandgap voltage to produce a predetermined reference voltage VD (e.g., 200 microvolts). The voltage divider 32 may include resistors R1 and R2 connected in series, and generate a predetermined reference voltage VD at a connection point of the resistors R1 and R2. It should be noted here that the implementation of the aforementioned voltage divider 32 is not intended to limit the invention. Further, the bandgap voltage generator 31 and the voltage divider 32 are not necessary components in the compensation circuit 3, and the predetermined reference voltage VD can be input from the external voltage source to the compensation circuit 3.

The quasi-bit shifter 35 is configured to receive the predetermined reference voltage VD and the feedback voltage CS, and shift the positions of the predetermined reference voltage VD and the feedback voltage CS to respectively generate the quasi-displacement bit reference voltage and the quasi-displacement bit feedback voltage to The first trimming circuit 33 and the second trimming circuit 34.

The quasi-displacer 35 can be implemented by current sources IS1, IS2 and PMOS transistors MP1, MP2, and the present invention does not limit the implementation of the quasi-displacer 35. The gate terminal of the PMOS transistor MP1 is connected to the connection point of the resistors R1 and R2 to receive a predetermined reference voltage VD, the source terminal of the PMOS transistor MP1 is connected to the current source IS1 and the first trimming circuit 33, and the PMOS transistor MP1 is turned on. Extremely connected to the ground voltage GND. The gate terminal of the PMOS transistor MP2 is for receiving the feedback voltage CS, the source terminal of the PMOS transistor MP2 is connected to the current source IS2 and the second trimming circuit 34, and the drain terminal of the PMOS transistor MP2 is connected to the ground voltage GND.

The first trimming circuit 33 includes a plurality of resistors RA connected in series and a plurality of fuses F1 connected in parallel to the plurality of resistors RA. The second trimming circuit 34 includes a plurality of resistors RB connected in series and a plurality of fuses F2 connected in parallel to the plurality of resistors RB. Please note that in order to make FIG. 3 more compact, FIG. 3 only shows one resistor RA and one fuse F1 in the first trimming circuit 33, and one resistor in the second trimming circuit 34 is illustrated. RB and one fuse F2, but the invention is not limited thereto. The fuses F1 and F2 are blown according to the trimming code to trim the quasi-displacement bit reference voltage, so the first trimming circuit 33 is used to generate a trim reference voltage (ie, VREF + Vos) to one input of the error amplifier EA.

Specifically, in the ideal case, the input voltage offset Vos does not exist, so that all of the fuses F1 and F2 are not blown. At this time, the first trimming circuit 33 and the second trimming circuit 34 respectively output the reference voltage VREF (for example, 200 microvolts) and the quasi-shift bit feedback voltage to the error amplifier EA. When the input voltage offset Vos is positive, at least one fuse F1 is blown, so the first trimming circuit 33 generates a trimming reference voltage (ie, VREF + Vos) to the error amplifier EA. When the input voltage offset Vos is negative, at least one of the fuses F2 is blown, so the second trimming circuit 34 generates a trimming feedback voltage (i.e., CS + Vos) to the error amplifier EA.

Please note here that the resistor RA can have different resistance values. For example, the resistance of the resistor RA may be 0.25R, 0.5R, R, 2R, 4R, and R multiplied by 2, where R is the unit resistance value. In a similar manner, the resistance of resistor RB can be 0.25R, 0.5R, R, 2R, 4R, and R multiplied by 2 to other powers. However, the resistance values of the resistors RA and RB are not intended to limit the invention.

The PMOS transistors MP1 and MP2 may not be designed to match each other because the trim reference voltage or the trim feedback voltage of the first or second trimming circuits 33, 34 not only compensates for the input voltage offset Vos of the error amplifier EA, but also compensates for the level. The mismatch of the PMOS transistors MP1 and MP2 in the shifter 35.

The compensation current absorbing means 36 is for absorbing the compensation current, wherein the compensation current is the sum of the currents Ios_B, Ios_A passing through the first trimming circuit 33 and the second trimming circuit 34. The compensation current absorbing device 36 includes an operational amplifier Ios_OP having a high gain and a small voltage offset, NMOS transistors MN1, MN2, and a resistor RC. The input terminals of the operational amplifier Ios_OP are respectively connected to a predetermined reference voltage VD (or another regulated voltage reference) and one end of the resistor RC. The gate terminals of the NMOS transistors MN1 and MN2 are connected to the output of the operational amplifier Ios_OP. The source terminals of the NMOS transistors MN1 and MN2 are connected to one end of the resistor RC, and the other end of the resistor RC is connected to the ground voltage GND. The NMOS terminals of the NMOS transistors MN1 and MN2 are connected to the second trimming circuit 34 and the first trimming circuit 33, respectively.

The NMOS transistors MN1 and MN2 should be designed to match each other such that the currents Ios_B, Ios_A through the NMOS transistors MN1 and MN2 are the same. Further, the resistance value of the resistor RC may be a multiple of the unit resistance R, for example, 10R, that is, the resistors RA, RB, RC need to be designed to match each other. It should be noted that the design of the matching resistors RA, RB, RC is easier than the design of the matching transistor, and matching the design of only two NMOS transistors MN1 and MN2 is easier than designing for matching more than two transistors.

For example, when the predetermined reference voltage is 200 microvolts (mv), the resistance value of the resistor RC is 10R, the input voltage offset Vos is 5 microvolts, and one fuse F1 corresponding to the resistor RA having a resistance value of 5R is in the first A trim circuit 33 is blown to compensate for the input voltage offset Vos with 5 microvolts. That is, the incremental voltage on the reference voltage VREF is Vos_c = 0.5 *(200mv / 10R)* RA, and when Vos_c is 5 microvolts, the resistance value of the resistor RA should be R, wherein the first trimming circuit 33 The current Ios_B is 0.5 * (200 mv / 10R).

As described above, the operational amplifier Ios_OP has a small voltage offset, and the voltage offset of the operational amplifier Ios_OP can be divided by the resistance value of the resistor RC. For example, in the case of three standard deviations, the error amplifier EA has a maximum input voltage offset Vos of 20 microvolts, the voltage offset of the operational amplifier Ios_OP is represented as Vos_x, and corresponds to a resistor RA having a resistance value of 2R One of the fuses is blown. At this time, the incremental voltage on the reference voltage VREF is Vos_c = 0.5 * (200mv + Vos_x) / 10R * 2R = 20mv + Vos_x / 10. Assume that the input stage area size of the operational amplifier Ios_OP is 400 μm ² , and in the case of three standard deviations, the maximum value of the voltage offset Vos_x is 3.3 microvolts. Therefore, the voltage offset Vos_x affecting the incremental voltage on the reference voltage VREF is only 0.33 microvolts. 0.33 microvolts is a 0.165% voltage change of 200 microvolts, which meets the specification of a tolerance of ±3% of 200 microvolts.

Therefore, in the exemplary embodiment of the present invention, since only two transistors must be designed to be matched, and a plurality of resistors must be designed to match, the compensation circuit for compensating the input voltage offset of the error amplifier can be easily designed And has a small area. In addition, in the circuit detection process, it is only necessary to know the input voltage offset, and the offset current of the error amplifier and the transconductance of the error amplifier can be ignored without being known.

The above description is only exemplary embodiments of the invention and is not intended to limit the scope of the invention. Accordingly, various equivalents, modifications, and alterations of the present invention are intended to be included within the scope of the present invention.

1‧‧‧Switch mode LED driver

11‧‧‧Current-to-Voltage Converter

2‧‧‧Traditional compensation circuit

22‧‧‧Finishing circuit

23‧‧‧ dimming control circuit

3‧‧‧Compensation circuit

2, 31‧‧‧gap voltage generator

32‧‧‧Divider

33‧‧‧First trimming circuit

34‧‧‧Second trimming circuit

35‧‧‧quasi-positioner

36‧‧‧Compensated current absorbing device

AND‧‧‧ input analog signal

C_COMP‧‧‧Compensation Capacitor

CMP‧‧‧ comparator

COMP‧‧‧ error signal

CS‧‧‧feedback voltage

DUTY‧‧‧ pulse signal

EA‧‧‧Error Amplifier

F1, F2‧‧‧ fuse

GND‧‧‧ Grounding voltage

iLED‧‧‧LED current

Ios_OP‧‧‧Operational Amplifier

IOS_A, IOS_B‧‧‧ current

IS, IS1, IS2‧‧‧ current source

MN1, MN2, MN3, MN4‧‧‧ NMOS transistor

MP1, MP2, MP3, MP4‧‧‧ PMOS transistors

R1, R2, R3, R4, RA, RB, RC‧‧‧ resistance

SW1, SW2‧‧‧ switch

VD‧‧‧Predetermined reference voltage

VREF‧‧‧reference voltage

V_SAW‧‧‧Sawtooth signal

Vos‧‧‧Input voltage offset

The drawings are provided to enable a person of ordinary skill in the art to have a further understanding of the invention, and are incorporated in and constitute a part of the specification. The drawings illustrate exemplary embodiments of the invention and, together,

Figure 1A is a schematic diagram of a conventional switch mode LED driver.

Figure 1B is a schematic diagram of an error amplifier.

Figure 2A is a schematic diagram of a conventional compensation circuit for compensating for the input voltage offset of the error amplifier.

Figure 2B is a graph of the analog dimming ratio curve.

Figure 3 is a schematic diagram of an error amplifier circuit of an exemplary embodiment of the present invention.

no

Claims (11)

A compensation circuit for compensating an input voltage offset of an error amplifier, comprising: a quasi-bit shifter for shifting a level of a feedback voltage and a level of a predetermined reference voltage, thereby outputting a a quasi-displacement feedback voltage and a quasi-displacement reference voltage; a first trimming circuit coupled to the quasi-displacer for trimming a first resistance value according to a trimming code to adjust the quasi-displacement a bit reference voltage, wherein the trimming code has a ratio relationship between the input voltage offset and a resistance value to be trimmed; a second trimming circuit coupled to the quasi-bit shifter and the error amplifier for determining the trimming code Trimming a second resistance value to adjust the quasi-displacement bit feed voltage; and a compensation current absorbing device coupled to the first trimming circuit and the second trimming circuit for absorbing the first trimming circuit and The second trimming circuit has a plurality of currents. The compensation circuit of claim 1, wherein the first trimming circuit outputs a trimming reference voltage to an input terminal of the error amplifier when the input voltage offset is positive, and the second trimming circuit outputs the level The shift feedback voltage is applied to the other input of the error amplifier. The compensation circuit of claim 1, wherein when the input voltage offset is negative, the first trimming circuit outputs a reference voltage to an input terminal of the error amplifier, and the second trimming circuit outputs a trimming feedback voltage. The other input of the error amplifier is provided, wherein the reference voltage is equal to the quasi-shift bit reference voltage. The compensation circuit of claim 1, wherein the quasi-displacer further comprises: a first current source; a second current source; a first PMOS transistor, a gate terminal for receiving the predetermined reference voltage a source terminal connected to the first current source and the first trimming circuit, and a terminal connected to a ground voltage; and a second PMOS transistor having a gate terminal for receiving the feedback voltage, A source terminal is coupled to the second current source and the second trimming circuit, one terminal of which is connected to the ground voltage. The compensation circuit of claim 1, wherein the first trimming circuit comprises a plurality of first resistors connected in series and a plurality of first fuses connected in parallel to the first resistors, wherein the first fuses The trimming code is blown according to the trimming code. The compensation circuit of claim 5, wherein the second trimming circuit comprises a plurality of second resistors connected in series and a plurality of second fuses connected in parallel to the second resistors, wherein the second fuses The trimming code is blown according to the trimming code. The compensation circuit of claim 6, wherein the compensation current absorbing device further comprises: an operational amplifier having an input for receiving the predetermined reference voltage; and a third resistor having one end connected to the other of the operational amplifier An input end, the other end of which is connected to a ground voltage; a first NMOS transistor having a gate terminal connected to an output terminal of the operational amplifier, a terminal connected to the second trimming circuit, and a source terminal connected To the one end of the third resistor; and a second NMOS transistor having a gate terminal connected to the output terminal of the operational amplifier, one terminal connected to the first trimming circuit, and one source connected to the source The one end of the third resistor. The compensation circuit of claim 7, wherein the first to the third resistors are designed to match each other, and the first and second NMOS transistors are designed to match each other. The compensation circuit of claim 1, further comprising: a bandgap voltage generator for generating a bandgap voltage; and a voltage divider connected to the bandgap voltage generator and the quasi-displacer And dividing the bandgap voltage to generate the predetermined reference voltage. The compensation circuit of claim 9, wherein the voltage divider comprises a plurality of resistors connected in series, and a connection point of the two resistors is used to output the predetermined reference voltage. An error amplifier circuit comprising: a compensation circuit as in one of claims 1 to 10; and the error amplifier.