TWI542968B - Current mirror with tunable mirror ratio - Google Patents

Description

Adjustable mirror ratio current mirror 【0001】

The present invention relates to a current mirror, and more particularly to a current mirror having an adjustable mirror ratio.

【0002】

Current mirrors have been widely used in analog integrated circuits. The current mirror produces an output current that is mirrored by a reference current. The present invention contemplates that the mirror ratio between the output current and the reference current can be adjusted to provide an accurate value for the output current.

[0003]

According to an embodiment of the invention, a current mirror circuit is proposed. The current mirror circuit includes a current source, a mirror circuit, a feedback circuit and an adjustable component. The current source is configured to generate a reference current; the mirror circuit has a first node and a second node, the first node is for passing a first mirror current, and the second node is for passing a second mirror current The feedback circuit is coupled to the mirror circuit for equalizing the voltages on the first node and the second node; and the adjustable component is coupled to the mirror circuit and driven by the output of one of the feedback circuits to provide a target output Current.

[0004]

In accordance with another embodiment of the present invention, a method for generating a target output current through a current mirror is presented. The method of generating a target output current through a current mirror includes providing a current mirror, the current mirror including a current source, a mirror circuit, a feedback circuit, and an adjustable component. The current source is configured to generate a reference current; the mirror circuit has a first node and a second node, the first node is for passing a first mirror current, and the second node is for passing a second mirror current a feedback circuit coupled to the mirror circuit for equalizing voltages on the first node and the second node; and an adjustable component coupled to the mirror circuit and driven by an output of the feedback circuit To provide a target output current.

[0005]

According to a further embodiment of the invention, a current mirror circuit is provided. The current mirror circuit includes a current source, a mirror circuit, a feedback circuit and an output transistor. The current source is configured to generate a reference current; the mirror circuit has a first node and a second node, the first node is for passing a first mirror current, and the second node is for passing a second mirror current The feedback circuit is coupled to the mirror circuit for equalizing the voltages on the first node and the second node; and the output transistor is coupled to the mirror circuit and driven by the output of one of the feedback circuits to provide a target output Current.

[0006]

In order to provide a better understanding of the above and other aspects of the present invention, the embodiments are described in detail below.

[0076]

100, 300, 500, 700, 900, 1200, 1400‧‧‧ circuits
110, 310, 510, 910‧‧‧ current source
120, 130, 330, 340, 350, 360, 540, 550‧‧‧ nodes
210, 410, 610, 640, 810, 1010, 1110, 1310‧‧‧ cross-width coordinates
220, 420, 620, 650, 820, 1020, 1120, 1320‧‧ ‧ ordinates
Lines 230, 240, 430, 440, 630, 660‧‧
312, 512‧‧ ‧ mirror circuit
314, 514‧‧‧ feedback circuit
316‧‧‧Output transistor
320, 520, 1430‧‧‧Operational Amplifier
516‧‧‧Adjustable components
530‧‧‧Adjustable voltage source
710‧‧‧ Temperature independent voltage source
720‧‧‧temperature dependent voltage source
831, 832, 833, 834, 835, 1031, 1032, 1033, 1034, 1035, 1131, 1132, 1133, 1134, 1135, 1331, 1332, 1333, 1334, 1335‧‧
930‧‧‧voltage source
1410‧‧‧Voltage counting circuit
1420‧‧‧Zina diode
N0, N1, N2‧‧‧N type MOS transistor
P0, P1, P2, P3, P4, P5, D1, D2‧‧‧P type MOS transistor
R1‧‧‧first resistance
R2‧‧‧second resistance
V _DD ‧‧‧ supply voltage
I _REF ‧‧‧Reference current
I _OUT ‧‧‧Output current
M‧‧‧M factor
V _OS ‧‧‧ offset voltage

【0007】

FIG. 1 is a circuit diagram of a conventional current mirror circuit in accordance with an embodiment.
Figure 2 is a computer simulation of the mirroring characteristics of the conventional current mirror circuit of Figure 1.
FIG. 3 is a circuit diagram of a current mirror circuit in accordance with an embodiment.
Figure 4 is a computer simulation of the mirroring characteristics of the current mirror circuit of Figure 3.
FIG. 5 is a circuit diagram of a current mirror circuit in accordance with an embodiment.
6A is a graph showing the relationship between the offset voltage of FIG. 5 and the 汲-source current of the P-type MOS transistor according to an embodiment.
Fig. 6B is a diagram showing the error of the relationship shown in Fig. 6A.
FIG. 7 is a circuit diagram of a current mirror circuit in accordance with an embodiment.
Figure 8 is a computer simulation of the temperature compensation characteristics of the current mirror circuit of Figure 7.
FIG. 9 is a circuit diagram of a current mirror circuit in accordance with an embodiment.
Figure 10 is a computer simulation of the temperature compensation characteristics of the current mirror circuit of Figure 9.
Figure 11 is a computer simulation of the temperature compensation characteristics of the current mirror circuit of Figure 9 when the room temperature reference current is shifted.
Figure 12 is a circuit diagram of a current mirror circuit in accordance with an embodiment.
Figure 13 is a computer simulation of the temperature compensation characteristics of the current mirror circuit of Figure 12 when the room temperature reference current is shifted.
Figure 14 is a circuit diagram of a current mirror circuit in accordance with an embodiment.

[0008]

The invention will be more apparent from the following detailed description of the appended claims. In the drawings and embodiments, the same or similar reference numerals are used to refer to the same or similar parts.

【0009】

1 is a circuit diagram of a conventional current mirror circuit 100 (hereinafter referred to as "circuit 100") in accordance with an embodiment. The circuit 100 includes a current source 110, N-type metal oxide semiconductor (NMOS) transistors N0 to N2, and P-type metal oxide semiconductor (PMOS) transistors P0 to P5. The N-type MOS transistor N0 includes a 汲 terminal, a gate terminal and a source terminal, wherein the 汲 terminal is coupled to the reference current I _REF generated by the current source 110, the gate terminal is coupled to the 汲 terminal, and the source terminal is coupled to the reference voltage ( For example, grounding). The N-type MOS transistor N1 includes a 汲 terminal, a gate terminal and a source terminal, wherein the 汲 terminal is coupled to the node 120, the gate terminal is coupled to the gate terminal of the N-type MOS transistor N0, and the source terminal is coupled to the ground. . The N-type MOS transistor N2 includes a 汲 terminal, a gate terminal and a source terminal, wherein the 汲 terminal is coupled to the node 130, the gate terminal is coupled to the gate terminal of the N-type MOS transistor N0, and the source terminal is coupled to ground. The P-type MOS transistor P0 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the supply voltage V _DD , the gate terminal is coupled to the node 120 , and the 汲 terminal is coupled to the P-type MOS transistor P 2 . . The P-type MOS transistor P1 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the supply voltage V _DD , the gate terminal is coupled to the node 120 , and the 汲 terminal is coupled to the P-type MOS transistor P3 . . The P-type MOS transistor P2 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the 汲 terminal of the P-type MOS transistor P0, the gate terminal is coupled to the node 130, and the 汲 terminal is coupled to the node. 120. The P-type MOS transistor P3 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the 汲 terminal of the P-type MOS transistor P1, the gate terminal is coupled to the node 130, and the 汲 terminal is coupled to the node. 130. The P-type MOS transistor P4 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the supply voltage V _DD , the gate terminal is coupled to the node 120, and the 汲 terminal is coupled to the P-type MOS transistor P5. . The P-type MOS transistor P5 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the 汲 terminal of the P-type MOS transistor P4, the gate terminal is coupled to the node 130, and the 汲 terminal is coupled to the external portion. A circuit (not shown) outputs an output current I _OUT .

[0010]

In the circuit 100, each of the N-type MOS transistors N0 to N2 and the P-type MOS transistors P0 to P5 has a gate width to length ratio of 10 μm / μm (μm) (W/ L), and the M factor are all 1. Wherein, the M factor is the number of unit transistors connected in parallel in one transistor.

[0011]

Ideally, all of the N-type MOS transistors N0 to N2 and P-type MOS transistors P0 to P5 operate in the saturation region. In the saturation region, the 汲-source current I _DS of the transistor is determined by the following equation:
(1)
Where V _GS is the gate-source voltage of the transistor, V _TH is the threshold voltage of the transistor, μ is the charge-carrier mobility, and C _ox is the gate oxidized capacitance per unit area. (gate oxide capacitance per unit area), M is the M factor, W is the gate width, and L is the gate length.

[0012]

Therefore, when all of the N-type MOS transistors N0 to N2 and the P-type MOS transistors P0 to P5 operate in the saturation region, due to the gate-source of the N-type MOS transistors N0 to N2 The voltages V _GS are all the same, so the 汲-source currents I _{DS of the} N-type MOS transistors N0 to N2 are the same. Similarly, since the gate-source voltages V _{GS of the} P-type MOS transistors P0, P1, and P4 are the same, the 汲-source currents I _{DS of the} P-type MOS transistors P0, P1, and P4 are the same. . P-type MOS transistor P2, P3 and P5 of the drain - source current I _DS are identical to the P-type MOS transistors P0, P1 and P4 of the drain - source current I _DS. Therefore, each of the N-type MOS transistors N0 to N2 and the P-type MOS transistors P0 to P5 has a 汲-source current I _DS equivalent to the reference current I _REF . As such, the mirror ratio of the circuit 100 is 1:1, that is, the ratio between the output current I _OUT and the reference current I _REF is 1:1.

[0013]

However, when the reference current I _{REF is} small (for example, microamperes or less), the P-type MOS transistors P0 to P4 can leave the saturation region and enter the linear region. In the linear region, the 汲-source current I _DS of the transistor is determined by the following equation:
(2)

[0014]

According to equation (2), in the linear region, the 汲-source current I _{DS of the} transistor is related not only to the gate-source voltage V _GS but also to the 汲-source voltage V _DS . Thus, the difference between the P-type MOS transistor P0, _V DS_P0 the P-type MOS electric crystal and P4 _V DS_P4, _I DS_P0 will cause the P-type MOS P-type metal-oxide-semiconductor power transistor P0, The difference between I _{DS_P4 of} crystal P4. Such a difference is an error in the mirror ratio of the circuit 100.

[0015]

Figure 2 is a computer simulation of the mirroring characteristics of circuit 100. In Fig. 2, the abscissa 210 represents the reference current I _REF (amperes (A)), and the ordinate 220 represents the ratio error (e.g., the error of the mirror ratio is compared to its ideal case). Line 230 is a result simulated by a fast-fast (MOS_FF) corner model and represents the I _{REF of the} ratio error corresponding circuit 100. The fast-fast corner module (hereinafter referred to as "low-V _TH skew corner") assumes that all P-type MOS transistors and N-type MOS transistors in circuit 100 are fabricated using the lowest _VTH 's. Line 240 is the result of the simulation simulated by the slow-slow (MOS_SS) corner module, representing the I _{REF of the} ratio error corresponding circuit 100. The slow-slow corner module assumes that all P-type MOS transistors and N-type MOS transistors in circuit 100 are fabricated using the highest V _TH 's. As shown in Figure 2, when the reference current I _{REF is} less than 1.24 microamperes (μA), the ratio error of the low-V _TH skew corner module is greater than 0.8%.

[0016]

FIG. 3 is a circuit diagram of a current mirror circuit 300 (hereinafter referred to as "circuit 300") in accordance with an embodiment. The circuit 300 includes a feedback path that equalizes the 汲-source currents of the P-type MOS transistors P0 and P1 to reduce the ratio error.

[0017]

Referring to FIG. 3, the circuit 300 includes a current source 310, a mirror circuit 312, a feedback circuit 314, and an output transistor 316. The mirror circuit 312 includes N-type MOS transistors N0 to N2 and P-type MOS transistors P0 to P3, and the functions of the P-type MOS transistors P0 to P3 are mirror transistors of the circuit 300. . The feedback circuit 314 includes an operational amplifier 320. The output transistor 316 includes a P-type MOS transistor P4. The N-type MOS transistor N0 includes a 汲 terminal, a gate terminal and a source terminal, wherein the 汲 terminal is coupled to the reference current I _REF generated by the current source 310, the gate terminal is coupled to the 汲 terminal, and the source terminal is coupled to the reference voltage ( For example, grounding). The N-type MOS transistor N1 includes a 汲 terminal, a gate terminal and a source terminal, wherein the 汲 terminal is coupled to the node 330, the gate terminal is coupled to the gate terminal of the N-type MOS transistor N0, and the source terminal is coupled to the ground. . The N-type MOS transistor N2 includes a 汲 terminal, a gate terminal and a source terminal, wherein the 汲 terminal is coupled to the node 340, the gate terminal is coupled to the gate terminal of the N-type MOS transistor N0, and the source terminal is coupled to the ground. . The P-type MOS transistor P0 includes a 汲 terminal, a gate terminal, and a source terminal, wherein the source terminal is coupled to the supply voltage V _DD , the gate terminal is coupled to the node 330 , and the NMOS terminal is coupled to the node 350 . The P-type MOS transistor P1 includes a 汲 terminal, a gate terminal, and a source terminal, wherein the source terminal is coupled to the supply voltage V _DD , the gate terminal is coupled to the node 330 , and the NMOS terminal is coupled to the node 360 . The P-type MOS transistor P2 includes a 汲 terminal, a gate terminal, and a source terminal, wherein the source terminal is coupled to the node 350, the gate terminal is coupled to the node 340, and the NMOS terminal is coupled to the node 330. The P-type MOS transistor P3 includes a 汲 terminal, a gate terminal, and a source terminal, wherein the source terminal is coupled to the node 360, the gate terminal is coupled to the node 340, and the NMOS terminal is coupled to the node 340. The P-type MOS transistor P4 includes a 汲 terminal, a gate terminal and a source terminal, wherein the source terminal is coupled to the node 360, the gate terminal is coupled to the operational amplifier 320, and the 汲 terminal is coupled to an external circuit (not shown) for output. Output current IOUT. The operational amplifier 320 includes a non-inverting terminal (symbol "+"), an inverting terminal (symbol "-"), and an output terminal, wherein the non-inverting terminal is coupled to the node 360, and the inverting terminal is coupled to the coupling end. The node 350 and the output end are coupled to the gate terminal of the P-type MOS transistor P4.

[0018]

Each of the N-type MOS transistors N0 to N2 and the P-type MOS transistors P0 to P4 has a width (W/L) ratio of 10 μm / 10 μm. The M factor M _P1 of the P-type MOS transistor _P1 is 2. The other factors have an M factor of 1, for example, N-type oxynitride transistors N0 to N2 and P-type MOS transistors P0, P2 to P4 have an M factor of 1. In some embodiments, the P-type MOS transistor P1 includes two unit transistors in parallel, and each of the N-type MOS transistors N0 to N2 and the P-type MOS transistors P0, P2 to P4 Only one unit transistor component is included. In other embodiments, the P-type MOS transistor P1 has a gate width W at the time of manufacture, and the gate width W is other N-type MOS transistors N0 to N2 and P-type MOS transistors P0, The gate width of P2 to P4 is twice as large.

[0019]

The operational amplifier 320 and the P-type MOS transistor P4 constitute a feedback path of the circuit 300. Specifically, the non-inverting terminal of the operational amplifier 320 receives the 汲_-source voltage V _{DS_P1 of the} P-type MOS transistor P1. The inverting terminal of the operational amplifier 320 receives the 汲_-source voltage V _{DS_P0 of the} P-type _MOS transistor P0. The operational amplifier 320 generates an output voltage to drive the P-type MOS transistor P4. Output voltage MOS transistor P0 of the P-type drain - source voltage _V DS_P0 MOS transistor and a P-type drain of P1 - proportional to a difference between the source voltage _V DS_P1. When V _{DS_P1} >V _{DS_P0} , the output voltage is equal to G·(V _{DS_P1} -V _{DS_P0} ), where G is the amplification of the operational amplifier 320. The output voltage of the operational amplifier 320 is applied to the gate terminal of the P-type MOS transistor P4, thereby lowering the voltage at the source terminal of the P-type MOS transistor P4. The output voltage of operational amplifier 320 can be adjusted by the difference between V _{DS_P1} and V _{DS_P0} until V _{DS_P1} = V _{DS_P0} . Therefore, the operational amplifier 320 makes V _{DS_P1} and V _{DS_P0} equal.

[0020]

In practice, node 350 passes a first mirror current through which the first mirror current is the 汲_-source current I _{DS_P0} of P-type _MOS transistor P0. Since the M factor of the transistors N0, N1, P0, and P2 is 1, the first mirror current is the same as the reference current I _REF . Further, node 360 passes a second mirror current through which the second mirror current is the 汲_-source current I _{DS_P1} of the P-type MOS transistor P1. When the reference current I _{REF is} small, the P-type MOS transistors P0 and P1 operate in the linear region, and M _P1 /M _P0 = 2, according to the equation (2), the second mirror current is the first mirror The current is twice as large. That is, I _{DS_P1} = 2·I _{DS_P0} = 2·I _REF . Since the P-type MOS transistor P4 is coupled to the node 360, the output current I _OUT provided by the P-type MOS transistor P4 is related to the second mirror current. According to Kirchhoff's current law, at node 360, the second mirror current is equal to the 汲_-source current I _{DS_N2 of the} N-type _MOS transistor N2 and the P-type _MOS transistor P4 汲- The sum of the source currents I _{DS_P4} (that is, the output current I _OUT ). That is, I _{DS_P1} = I _{DS_N2} + I _OUT . Since I _{DS_N2} = I _REF , I _OUT = I _{DS_P1} -I _{DS_N2} = I _REF . Therefore, even when the P-type MOS transistors P0 and P1 operate in the linear region, the output current I _OUT and the reference current I _REF are the same.

[0021]

Figure 4 is a computer simulation of the mirroring characteristics of circuit 300. In Fig. 4, the abscissa 410 represents the reference current I _REF (amperes (A)), and the ordinate 420 represents the ratio error. Line 430 is the result of the simulation using the fast-fast corner module and represents the I _{REF of the} ratio error corresponding circuit 300. Line 440 is the result of the simulation using the slow-slow corner module and represents the I _{REF of the} ratio error corresponding circuit 300. As shown in Figure 4, the ratio error of the low-V _TH skew corner module is greater than 0.8% only when the reference current I _{REF is} less than 550 nanoamperes (nA).

[0022]

FIG. 5 is a circuit diagram of a current mirror circuit 500 (hereinafter referred to as "circuit 500") in accordance with an embodiment. The circuit 500 includes an adjustable component that is within the feedback path such that the mirror ratio of the circuit 500 can be adjusted to a target value, and the target value is not entirely determined by the M factor of the MOS transistor.

[0023]

Referring to FIG. 5, circuit 500 includes current source 510, mirror circuit 512, feedback circuit 514, and adjustable component 516. The mirror circuit 512 includes N-type MOS transistors N0 to N2 and P-type MOS transistors P0 to P3, and the P-type MOS transistors P0 to P3 function as a mirror transistor of the circuit 500. The feedback circuit 514 includes an operational amplifier 520. The adjustable component 516 includes P-type MOS transistors D1 and D2 and an adjustable voltage source 530. The P-type MOS transistors D1 and D2 function as output transistors of the circuit 500. The current source 510, the N-type MOS transistors N0 to N2, the P-type MOS transistors P0 to P3, and the operational amplifier 520 are coupled in a manner similar to the current source 310 and the N-type MOS semiconductor in the circuit 300. The coupling manner of the crystals N0 to N2, the P-type MOS transistors P0 to P3, and the operational amplifier 320. Therefore, the detailed description of the coupling relationship will not be repeated here.

[0024]

In contrast to circuit 300, circuit 500 includes an adjustable component 516 at a location of P-type MOS transistor P4 of circuit 300. The adjustable component 516 is coupled to the feedback path of the circuit 500 to provide a target output current. Specifically, the operational amplifier 520 includes a non-inverting terminal (symbol "+"), an inverting terminal (symbol "-"), and an output terminal, wherein the non-inverting terminal is coupled to the node 540, and the node 540 is a P-type. The source terminal and the opposite end of the MOS transistor P3 are coupled to the node 550. The node 550 is the 汲 terminal of the P-type MOS transistor P0, and the output terminal is coupled to the P-type MOS transistor D2. The P-type MOS transistor D1 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the node 540, the gate terminal is coupled to the adjustable voltage source 530, and the 汲 terminal is coupled to an external circuit (not shown). To output the output current I _OUT . The P-type MOS transistor D2 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the node 540, the gate terminal is coupled to the output of the operational amplifier 520, and the NMOS terminal is coupled to the external circuit. P-type MOS transistors D1 and D2 are all driven by an operational amplifier 520. The adjustable voltage source 530 includes a positive terminal (symbol "+") and a negative terminal (symbol "-"), wherein the positive terminal is coupled to the gate terminal of the P-type MOS transistor P2, and the negative terminal is coupled to the P terminal. The gate terminal of the MOS transistor D1.

[0025]

Each of the N-type MOS transistors N0 to N2 and the P-type MOS transistors P0 to P3 has a width (W/L) ratio of 10 μm / 10 μm. The M factor M _N0 of the N-type MOS transistor _N0 is 4. The M factor M _P1 of the P-type MOS transistor _P1 is 5. The M factor M _D1 of the P-type MOS transistor _D1 is 7. The M factor M _D2 of the P-type MOS transistor _D2 is 4. The M factor of the other transistors is 1, that is, the M-factors of the N-type MOS transistors N1 and N2, and the P-type MOS transistors P0, P2, and P3 are 1.

[0026]

In practice, node 550 passes a first mirror current through which the first mirror current is the 汲_-source current I _{DS_P0} of P-type _MOS transistor P0 and I _{DS_P0} = I _REF /4. The node 540 passes the second mirror current, and the second mirror current is the 汲_-source current I _{DS_P1} of the P-type MOS transistor P1, and I _{DS_P1} = 5·I _REF /4. According to Kirchhoff's current law, at node 540, the second mirror current is equal to the 汲_-source current I _{DS_N2 of the} N-type _MOS transistor N2 and the 汲_-source current I of the P-type _MOS transistor D1 _{The sum of DS_D1} (that is, the output current I _OUT ) and the 汲_-source current I _{DS_D2} of the P-type _MOS transistor D2. That is, I _{DS_P1} = I _{DS_N2} + I _{DS_D1} + I _{DS_D2} . Because, I _{DS_N2} = I _REF /4, I _{DS_D1} + I _{DS_D2} = I _{DS_P1} -I _{DS_N2} = 5·I _REF /4−I _REF /4 = I _REF .

[0027]

An adjustable voltage source 530 generates an offset voltage V _OS, the offset voltage V _OS used in the P-type MOS transistor D2 of the gate - source voltage _V GS_D2 gate MOS transistor and the P-type D1 - source voltage Between V _{GS_D1} . The offset voltage V _OS can be adjusted to obtain a target output current I _target . The relationship between the offset voltage V _OS and the target output current I _target can be obtained as follows.

[0028]

First, it is assumed that the P-type MOS transistors D1 and D2 operate in a saturation region. Therefore, according to formula (1), each of the P-type MOS transistors D1 and D2,
(3)
among them .

[0029]

Offset voltage V _OS at the gate the P-type MOS transistor D1 - Establishing a difference between the source voltage _V GS_D2 - source voltage _V GS_D1 MOS transistor and a P-type gate D2. Therefore, the offset voltage V _OS can be expressed as follows.
(4)

[0030]

In order to make the output current (that is, the gate-source of the P-type MOS transistor D1)

The stream I _{DS_D1} ) is equal to I _target and I _{DS_D1} should be equal to I _target .

Since I _{DS_D2} = I _REF -I _{DS_D1} , I _{DS_D2} = I _REF -I _target . Thus, equation (4) can be converted into,
(5)

[0031]

Therefore, according to equation (5), by adjusting V _OS , circuit 500 can generate target output power

Stream I _target . For example, when I _REF = 12.6 microamperes (μA), the V _OS can be adjusted such that the output current I _OUT = I _target = 10 microamps (μA) by the configuration of the adjustable component 516 as described above. Therefore, by adjusting the offset voltage V _OS , the desired mirror ratio can be achieved.

[0032]

In circuit 500, the M factors of P-type MOS transistors D1 and D2 are not limited to 7 and 4, respectively, and may be any integer depending on the application of circuit 500. When the M factor of the P-type MOS transistors D1 and D2 changes, the offset voltage V _OS must also be adjusted accordingly.

[0033]

In circuit 500, the polarity of the adjustable voltage source 530 (ie, the coupling of the positive and negative terminals of the adjustable voltage source 530 in the circuit 500) can be based on the reference current I _REF , the target output current I _target , and P The M factor of the MOS transistors D1 and D2 is determined. in case The positive terminal of the adjustable voltage source 530 is coupled to the gate terminal of the P-type MOS transistor D2, and the negative terminal of the adjustable voltage source 530 is coupled to the gate terminal of the P-type MOS transistor D1, such as Figure 5 shows. On the other hand, if The polarity of the adjustable voltage source 530 is reversed. That is, the positive terminal of the adjustable voltage source 530 is coupled to the gate terminal of the P-type MOS transistor D1, and the negative terminal of the adjustable voltage source 530 is coupled to the gate terminal of the P-type MOS transistor D2. . in case Then, the output current I _{DS_D1 is} the target output current I _target . In this embodiment, the offset voltage V _OS generated by the adjustable voltage source 530 is zero. Therefore, the polarity of the adjustable voltage source 530 can be configured by one of the two methods described above.

[0034]

FIG. 6A is a diagram showing the relationship between the offset voltage V _OS and the 汲_-source current I _DS — D1 of the P-type _MOS transistor D1 according to an embodiment. In FIG. 6A, the abscissa 610 represents the offset voltage V _OS (millivolts (mV)), and the ordinate 620 represents the 汲_-source current I _{DS_D1 of the} P-type _MOS transistor D1 (microamperes (μA) ). Line 630 represents the relationship between the offset voltage V _OS and the 汲_-source current I _DS — D1 of the P-type _MOS transistor D1, which is obtained by a first-order linear approximation. FIG. 6B illustrates an error in a linear approximation of the relationship between the offset voltage V _OS and the 汲_-source current I _DS — D1 of the P-type _MOS transistor D1 in accordance with an embodiment. In Fig. 6B, the abscissa 640 represents the offset voltage V _OS (mV), and the ordinate 650 represents the error of the 汲-source current I _{DS_D1} obtained by the first-order linear approximation (nai pei (nA) )). Line 660 represents the relationship between the offset voltage V _OS and the error of the _汲-source current I _DS — D1 of the P-type _MOS transistor D1 obtained by a first-order linear approximation.

[0035]

FIG. 7 is a circuit diagram of a current mirror circuit 700 (hereinafter referred to as "circuit 700") in accordance with an embodiment. Circuit 700 includes a temperature dependent voltage source such that output current I _OUT of circuit 700 is temperature independent. That is, the output current I _OUT does not change with the operating temperature of the circuit 700 (ie, the temperature when the circuit 700 is operating).

[0036]

Referring to FIG. 7, the circuit 700 includes a current source 510, N-type MOS transistors N0 to N2, P-type MOS transistors P0 to P3, D1 and D2, and an operational amplifier 520. The above components are similar to circuits. 500. Unlike circuit 500, circuit 700 includes a temperature independent voltage source 710 and a temperature dependent voltage source 720. Temperature independent voltage source 710 and temperature dependent voltage source 720 are located between P-type MOS transistors D1 and D2. The temperature independent voltage source 710 produces a room temperature offset voltage that is adjustable at room temperature to achieve a target output current. The temperature dependent voltage source 720 produces a temperature dependent voltage that is used to compensate for variations in the output current due to changes in room temperature and operating temperature of the circuit 700.

[0037]

In circuit 700, current source 510 is a temperature independent source. That is, the I _REF generated by current source 510 does not change with the operating temperature of circuit 700. However, some of the device parameters of the transistor of circuit 700, such as threshold voltage _VTH and carrier mobility [mu], may vary with operating temperature. In the absence of the temperature dependent voltage source 720, even if the output current I _OUT reaches the target value at room temperature, the output current I _OUT may be offset from the target value when the operating temperature is shifted from room temperature. To maintain I _OUT temperature independence, the temperature dependent voltage source 720 generates a temperature dependent voltage to compensate for changes in the fabrication parameters of the transistor due to temperature variations. The relationship between the room temperature offset voltage, the temperature dependent voltage, and the operating temperature T can be derived from the following.

[0038]

First, the carrier mobility μ is temperature dependent, which can be expressed as,
(6)
Where T ₀ is room temperature, μ ₀ is the carrier mobility when the operating temperature is room temperature T ₀ , μ is the carrier mobility of the operating temperature T, and α is the loading of the MOS transistor of the present invention The mobility index of the mobility of the mobility μ.

[0039]

The carrier mobility μ can be estimated using a first-order Taylor expansion.

(7)
among them .

[0040]

When combined with formula (4) and formula (7),
(8)
Where V _OS is an offset voltage, which is generated in conjunction with a temperature independent voltage source 710 and a temperature dependent voltage source 720.

[0041]

It is assumed that the target 汲-source current of the P-type MOS transistor D1 (that is, the target output current of the circuit 700) is I ₁₀ at room temperature, and the target 汲-source current of the P-type MOS transistor D2. I ₂₀ at room temperature. That is, at room temperature, And . Make And . Then, the formula (8) can be represented by
(9)

[0042]

The offset voltage V _OS can be represented by a room temperature offset voltage V _OS0 and a temperature coefficient TC, as follows
(10)
Where V _OS0 is the room temperature offset voltage generated by the temperature independent voltage source 710, V _OS0 · TC · ΔT is the temperature dependent voltage generated by the degree dependent voltage source 720, and TC is the temperature coefficient of the offset voltage V _OS .

[0043]

Comparing equations (9) and (10), the room temperature offset voltage V _OS0 and the temperature coefficient TC can be expressed by the following equation.
(11)
(12)

[0044]

According to equation (11), the reference current I _{REF is} known, and the room temperature offset voltage V _OS0 can be determined according to equation (11) to obtain a known target output current I ₁₀ at room temperature. That is, the room temperature deviation can be determined according to the target output current I ₁₀ , the reference current I _REF , the gate oxidizing capacitance C _ox per unit area, the aspect ratio (W/L), and the room temperature carrier mobility μ0. Shift voltage V _OS0 . In an embodiment, when the room temperature offset voltage V _OS0 is determined, it is assumed that C _ox and μ0 do not change with the device, that is, C _ox and μ0 are consistent, and will not be due to different process corners. (process corners) change, such as typical-typical corner (MOS_TT corner), all N-type MOS transistors and P-type MOS transistors have typical V _TH's , typical V _TH's at the highest V _TH's and lowest

Between the V _TH's and the fast-fast corner (MOS_FF corner), all of the N-type MOS transistors and P-type MOS transistors have the lowest V _TH's and the slow-slow corners (MOS_SS corner), all of which N-type MOS transistors and P-type MOS transistors have the highest V _TH's and fast-slow corners (MOS_FS corner). All N-type MOS transistors have the lowest V _TH's and all P-types. Metal oxide semiconductor transistors have the highest V _TH's and slow-fast corners (MOS_SF corner), all N-type MOS transistors have the highest V _TH's , and all P-type MOS transistors have the lowest V _TH's . Once the room temperature is shifted

After the voltage V _{OS0 is} determined, the room temperature offset voltage V _OS0 will be fixed and will not change as the temperature during operation of the circuit 700 changes. Further, according to the equation (12), since the temperature coefficient TC is not related to the temperature change, V _OS0 · TC does not change with temperature. Thus, during operation of circuit 700, the offset voltage V _OS = V _OS0 + V _OS0 · TC ΔT, the only variable is the temperature difference ΔT, which ΔT is between the operating temperature T and the room temperature T0. Therefore, the offset voltage V _OS changes with the temperature difference ΔT, which can be used to compensate for changes in the process parameters of the transistor due to temperature variations.

[0045]

Figure 8 is a computer simulation of the temperature compensation characteristics of circuit 700. In Fig. 8, the abscissa 810 represents the operating temperature T (oC), and the ordinate 820 represents the output current error I _error (naiamper (nA)) between the actual output current I _OUT and the target output current I ₁₀ . Curve 831 represents the output current error I _error corresponding to the operating temperature (hereinafter referred to as "temperature compensation error"), which is the result of simulation using the slow-slow (MOS_SS) corner model, which assumes all P-type MOS semiconductors in circuit 700. Crystal and N-type MOS transistors have the highest V _TH's . Curve 832 represents the temperature compensation error, which is the result of the simulation using the fast-slow (MOS_FS) corner model, which assumes that all of the N-type MOS transistors have the lowest V _TH's and the P-type MOS transistors have the highest V _TH's . Curve 833 represents the temperature compensation error, which is the result of a typical-typical (MOS_TT) corner model, which assumes that all N-type MOS transistors and P-type MOS transistors have typical V _TH's , with typical V _TH's At the highest V _TH's and most

Between low V _TH's . Curve 834 represents the temperature compensation error, which is the result of a slow-fast (MOS_SF) corner model, which assumes that all N-type MOS transistors have the highest V _TH's and all P-type MOS transistors have the lowest V _TH's . Curve 835 represents the temperature compensation error, which is the result of simulation using a fast-fast (MOS_FF) corner model, which assumes that all N-type MOS transistors and P-type MOS transistors have the lowest V _TH's .

[0046]

During the simulation to produce the result as shown in Fig. 8, I _REF is set to 12.6 microamperes (μA), and V _OS0 is determined according to equation (11) to satisfy I _out = I ₁₀ = 10uA at T ₀ , T ₀ is the intermediate temperature point at the temperature simulation range of each process corner. Further, the temperature dependent voltage V _OS0 · TC · ΔT is assumed to be unadjustable. To determine when the fast - fast corner, Slow - Slow rotation angle, fast - slow corner, and slow - when fast corner, typical - and the parameter μ C _ox is typically used as corner model μ C _ox and these corners. However, the temperature dependent voltage V _OS0 · TC · ΔT determined in this manner does not track the process variables of the P-type _MOS transistor and the N-type _MOS transistor. That is, device parameters such as C _ox and μ vary with the device manufacturing process and are also different at different corner processes, such as fast-fast corners, slow-slow corners, fast-slow corners, and slow-fast corners. In these process corners, the difference between C _ox and μ may cause a change in temperature compensation error. Therefore, as shown in Fig. 8, the curves 831 to 835 indicate that the temperature compensation errors are different in different process corners. For example, when the operating temperature is 120oC, the temperature-compensation error produced by the fast-fast corner model is almost twice the temperature compensation error produced by other corner models. In other examples, when the operating temperature is -40oC, the temperature compensation error produced by the slow-slow corner model is higher than the temperature compensation error generated by other corner models.

[0047]

During the simulation to produce the results as shown in Fig. 8, both C _ox and μ will change with different process angles. However, the invention is not limited thereto. If C _ox changes with different process angles and μ does not change with different process angles, the temperature dependent voltage V _OS0 · TC·ΔT determined based on the typical-typical corner model still does not track process variables. . Therefore, the temperature compensation error is different at these process angles.

[0048]

FIG. 9 is a circuit diagram of a current mirror circuit 900 (hereinafter referred to as "circuit 900") in accordance with an embodiment. Circuit 900 includes a temperature dependent voltage source to compensate for temperature variations.

[0049]

Referring to FIG. 9, the circuit 900 includes a current source 910, N-type MOS transistors N0 to N2, P-type MOS transistors P0 to P3, D1 and D2, an operational amplifier 520, and a voltage source 930. The current source 910 of the circuit 900, the N-type MOS transistors N0 to N2, the P-type MOS transistors P0 to P3, D1 and D2, the operational amplifier 520 and the voltage source 930 are coupled in a similar manner to the components of the circuit 500. . Each of the N-type MOS transistors N0 to N2 and the P-type MOS transistors P0 to P3, D1 and D2 has a width (W/L) ratio of 10 μm / 10 μm. The M factor M _N0 of the N-type MOS transistor _N0 is 4. The M factor M _P1 of the P-type MOS transistor _P1 is 5. The M factor M _D1 of the P-type MOS transistor _D1 is 7. The M factor M _D2 of the P-type MOS transistor _D2 is 4. The M factor of the other transistors is 1, that is, the M-factors of the N-type MOS transistors N1 and N2, and the P-type MOS transistors P0, P2, and P3 are 1.

[0050]

In circuit 900, current source 910 is a temperature dependent current source that produces a reference current I _REF that varies with operating temperature T. The voltage source 930 is a temperature independent voltage source whose offset voltage V _OS does not change as the operating temperature T changes. To maintain I _OUT temperature independence, current source 910 is configured to provide a reference current I _REF to compensate for process parameter changes in the transistor due to temperature variations, wherein reference current I _REF can be adjusted based on operating temperature T. The reference current I _REF and the operating temperature T can be derived from the following equations.

[0051]

First, assume that the temperature dependent reference current I _REF can be expressed as
(13)
Where I ₀ is the reference current at room temperature T ₀ , and I ₀ ·ΔT·TC is the temperature dependent portion of the reference current I ₀ , And TC is the temperature coefficient of the reference current I _REF .

[0052]

At room temperature, I _{DS_D1} = I ₁₀ , I _{DS_D2} = I ₂₀ , and I _REF = I _{DS_D1} + I _{DS_D2} = I ₁₀ +I ₂₀ . Therefore, I _{DS_D2} can be expressed as,
(14)

[0053]

Combining equations (4) and (14), the offset voltage V _OS can be expressed as

(15)
among them And .

[0054]

Combining equations (7) and (15), the offset voltage V _OS can be expressed as
(16)

[0055]

In order to exhibit the offset voltage V _OS temperature independence, the equation relating to the first order ΔT in equation (16) must be eliminated. In order to eliminate the equation related to the first order ΔT in the equation (16), the temperature coefficient TC can be set to
(17)

[0056]

Therefore, the offset voltage V _OS can be expressed as,
(18)

[0057]

Therefore, in the circuit 900, the reference current I _REF can be determined according to the equations (13) and (17), and the offset voltage V _OS can be determined according to the equation (18). As seen in equations (13) and (17), I _REF includes temperature independent current I ₀ and temperature dependent I ₀ · ΔT · TC current, wherein temperature independent current I _{0 is} used to generate target output current at room temperature, temperature dependent The I ₀ ·ΔT·TC current is used to compensate for the temperature.

[0058]

Similar to circuit 700 of Figure 7, current source 910 can be implemented by a temperature independent current source and a temperature dependent current source. At room temperature T ₀ , the temperature independent current source produces a reference current I ₀ . The temperature dependent current source produces a temperature dependent current I ₀ ·ΔT·TC.

[0059]

Figure 10 is a computer simulation of the temperature compensation characteristics of circuit 900. In Fig. 10, the abscissa 1010 represents the operating temperature T (oC), and the ordinate 1020 represents the output current error I _error (naiamper (nA)) between the actual output current I _OUT and the target output current I ₁₀ . Curve 1031 represents the temperature compensation error, which is the result of the simulation using the fast-fast (MOS_FF) corner model. Curve 1032 represents the temperature compensation error, which is the result of the simulation using the fast-slow (MOS_FS) corner model. Curve 1033 represents the temperature compensation error, which is the result of simulation using a typical-typical (MOS_TT) corner model. Curve 1034 represents the temperature compensation error and is the result of the simulation using the slow-fast (MOS_SF) corner model. Curve 1035 represents the temperature compensation error and is the result of the simulation using the slow-slow (MOS_SS) corner model.

[0060]

During the simulation to produce the result as shown in Fig. 10, the room temperature reference current I ₀ is set to 12.6 microamperes (uA), and the offset voltage V _OS is determined according to equation (18) to the temperature at each process corner. The intermediate temperature point of the simulation range satisfies I _out = I ₁₀ = 10uA. Further, it is assumed that the temperature dependent voltage I ₀ ·ΔT·TC is not adjustable. According to equation (17), the temperature coefficient TC of I _REF is not related to C _ox and μ, and is only related to known parameters such as B1, B2, I ₀ , I ₂₀ , T ₀ and α. That is to say, the temperature dependent portion I ₀ ·ΔT·TC of I _REF is less affected by the process variable. Therefore, as shown in Figure 10, the temperature compensation error does not change with different process angles (as shown in Figure 8). As such, the circuit 900 includes a temperature dependent current source 910 that reduces variations in temperature compensation errors at different process corners.

[0061]

Figure 11 is a computer simulation of the temperature compensation characteristics of the circuit 900 when the room temperature reference current I _{0 is} shifted to I ₀ ' = 90% · I ₀ . In Fig. 11, the abscissa 1110 represents the operating temperature T (oC), and the ordinate 1120 represents the output current error.

Difference I _error = I _OUT - I ₁₀ (Nai'an (nA)), where I ₁₀ is 10 microamperes (μA), and I _OUT is determined according to I _REF based on equations (13) and (17). Wherein the TC of the formula (17) is determined according to the original I ₀ = 12.6 μA, but I _{0 of} the formula (13) is I ₀ '=90%·I ₀ . Curve 1131 represents the temperature compensation error, which is the result of the simulation using the fast-fast (MOS_FF) corner model. Curve 1132 represents the temperature compensation error, which is the result of the simulation using the fast-slow (MOS_FS) corner model. Curve 1133 represents the temperature compensation error, which is the result of simulation using a typical-typical (MOS_TT) corner model. Curve 1134 represents the temperature compensation error and is the result of the simulation using the slow-fast (MOS_SF) corner model. Curve 1135 represents the temperature compensation error and is the result of the simulation using the slow-slow (MOS_SS) corner model.

[0062]

When I ₀ = 12.6 uA is shifted to I ₀ ' = 90% · I ₀ = 11.3 uA, I ₀ ' is greater than the target output current I ₁₀ = 10μA. Although the polarity of V _OS and the values of I ₁₀ and B _{1 in} equations (17) and (18) remain unchanged. However, I ₂₀ ' has changed from 2.6 uA to 1.3 uA resulting in a corresponding B ₂ ' value ( ) becomes smaller. Substituting I ₂₀ 'and B ₂ ' into equations (17) and (18) yields V _OS ' corresponding to I ₀ ' With TC' . However, V _OS 'and TC' are both greater than V _OS and TC corresponding to I ₀ . This phenomenon explains the output current error I _error shown in Fig. 11 from a temperature range of -40oC to 40oC, which is a negative temperature dependent characteristic. And the output current error I _error corresponding to the five process corners at 125oC is diverged to the maximum.

[0063]

FIG. 12 is a circuit diagram of a current mirror circuit 1200 (hereinafter referred to as "circuit 1200") in accordance with an embodiment. The circuit 1200 includes P-type MOS transistors P0 and P1, and the MOS transistors P0 and P1 have an adjusted M factor to compensate for the offset I ₀ .

[0064]

Referring to FIG. 12, the circuit 1200 includes a current source 910, N-type MOS transistors N0 to N2, P-type MOS transistors P0 to P3, D1 and D2, an operational amplifier 520, and a voltage source 930. The components of circuit 900. Unlike the circuit 900, the M factor M _P0 of the P-type MOS transistor _P0 is 3, and the M factor M _P1 of the P-type MOS transistor _P1 is 16.

[0065]

The circuit 1200 is applied in the case where the room temperature reference current I _{0 is} shifted to I ₀ '=90%·I ₀ . As previously described, when I _{0 is} offset to I ₀ '=90%·I ₀ , the temperature dependent portion of I _REF is also offset by a factor of 90%. This will result in temperature compensation errors for different process corners, especially in high temperature zones. However, in circuit 1200, the ratio of M _P1 /M _P0 is adjusted to 5/1 instead of 16/3, so that the offset current I ₀ ' is amplified by 1.083 (=(16/3-1)/4) times. . Therefore, 1.083 I ₀ 'is equal to 97.49% (=1.083x0.9) of the original I ₀ .

[0066]

In the circuit 1200, the M factors of the P-type MOS transistors P0 and P1 are 3 and 16, respectively. However, the present invention is not limited thereto, and the M factor of the P-type MOS transistors P0 and P1 can be determined according to the room temperature reference current I ₀ . For example, to adjust the M factor of the P-type MOS transistors P0 and P1, the circuit 1200 may include a MOS switch (not shown) connected to each of the P-type MOS transistors P0 and P1. When the offset of I ₀ is detected, the MOS switch can adjust the M factor of the P-type MOS transistors P0 and P1 according to the offset of I ₀ .

[0067]

Figure 13 is a computer simulation of the temperature compensation characteristics of circuit 1200 when room temperature reference current I _{0 is} shifted to I ₀ ' = 90% · I ₀ . In Fig. 13, the abscissa 1310 represents the operating temperature T (oC), and the ordinate 1320 represents the output current error.

Difference I _error = I _OUT -I ₁₀ (Nai'an (nA)), where I ₁₀ is 10 microamperes (μA), and I _OUT is determined according to I _REF based on equations (13) and (17). Wherein the TC of the formula (17) is determined according to the original I ₀ = 12.6 μA, but I _{0 of} the formula (13) is I ₀ '=90%·I ₀ . Curve 1331 represents the temperature compensation error, which is the result of the simulation using the fast-fast (MOS_FF) corner model. Curve 1332 represents the temperature compensation error, which is the result of the simulation using the fast-slow (MOS_FS) corner model. Curve 1333 represents the temperature compensation error, which is the result of simulation using a typical-typical (MOS_TT) corner model. Curve 1334 represents the temperature compensation error and is the result of the simulation using the slow-fast (MOS_SF) corner model. Curve 1335 represents the temperature compensation error and is the result of the simulation using the slow-slow (MOS_SS) corner model.

[0068]

As described above, in the circuit 1200, since the M factor of the P-type MOS transistors P0 and P1 is adjusted and amplified to the offset I ₀ ', the output current I _{OUT is} maintained even when I _{0 is} shifted. At I ₁₀ . Therefore, the curves 1331 to 1335 of Fig. 13 are similar to the curves 1031 to 1035 of Fig. 10. That is to say, compared with Fig. 11, the temperature compensation errors of the five process angles of Fig. 13 at -40oC and 125oC are relatively close in value. For example, the maximum temperature compensation difference at -40oC and at 125oC is reduced from 97.82 nanoamperes in Figure 11 to 36.22 nanoamperes in Figure 13.

[0069]

FIG. 14 is a circuit diagram of a current mirror circuit 1400 (hereinafter referred to as "circuit 1400") in accordance with an embodiment. Circuit 1400 includes a voltage counting circuit to implement voltage source 530 of circuit 500.

[0070]

Referring to FIG. 14, the circuit 1400 includes a current source 510, N-type MOS transistors N0 to N2, P-type MOS transistors P0 to P3, D1 and D2, an operational amplifier 520, and a voltage counting circuit 1410. The current source 510, the N-type MOS transistors N0 to N2, the P-type MOS transistors P0 to P3, D1 and D2, and the operational amplifier 520 are similar to the similar elements of the circuit 500 of FIG.

[0071]

The voltage counter circuit 1410 is connected between the gate terminal of the P-type MOS transistor D2 and the gate terminal of the P-type MOS transistor D1. The voltage counting circuit 1410 includes a Zener diode 1420, a first resistor R1, a second resistor R2, and an operational amplifier 1430. The Zener diode 1420 includes a first end and a second end, wherein the first end is coupled to the gate terminal of the P-type MOS transistor D2, and the second end is coupled to the first resistor R1. The first resistor R1 includes a first end and a second end, wherein the first end is coupled to the second end of the Zener diode 1420, and the second end is coupled to the second resistor R2. The second resistor R2 is an adjustable resistor, and includes a first end and a second end, wherein the first end is coupled to the first resistor R1 and the second end is coupled to the gate terminal of the P-type MOS transistor D1. The operational amplifier 1430 includes a non-inverting terminal (symbol "+"), an inverting terminal (symbol "-"), and an output terminal, wherein the non-inverting terminal is coupled to the gate terminal of the P-type MOS transistor D2, The opposite end is coupled to the second end of the first resistor R1 and the output end is coupled to the gate terminal of the P-type MOS transistor D1.

[0072]

The function of the voltage counter circuit 1410 is an adjustable voltage source that produces an offset voltage V _OS applied between the P-type MOS transistors D1 and D2. The offset voltage V _OS can be expressed by the following.

Wherein R ₁ is the impedance of the first resistor R1, R ₂ is the impedance of the second resistor R2, and V _Z is the breakdown voltage of the Zener diode 1420. Since the second resistor R2 is an adjustable resistor, the V _OS can be adjusted by adjusting the impedance of the second resistor R2. For example, the V _OS can be adjusted according to equation (5), so that the output current I _{OUT of the} circuit 1400 can be the target

The value I _target .

[0073]

Circuits 300, 500, 700, 900, 1200, and 1400 are MOS circuits. However, the present invention is not limited to a MOS circuit and can be applied to a field effect transistor (FET) circuit, a bipolar junction transistor (BJT) circuit, and a bipolar complementary metal oxide semiconductor (BiCMOS) circuit.

[0074]

The current mirror disclosed in the embodiments of the present invention can be applied to a circuit system of accurate source current, such as a relaxation oscillator circuit and a current comparator.

[0075]

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. The scope of the present invention is not limited by the description of the embodiments, which are defined by the scope of the appended claims.

500‧‧‧ circuits

510‧‧‧current source

520‧‧‧Operational Amplifier

530‧‧‧Adjustable voltage source

540, 550‧‧‧ nodes

N0, N1, N2‧‧‧N type MOS transistor

P0, P1, P2, P3, D1, D2‧‧‧P type MOS transistor

V _DD ‧‧‧ supply voltage

I _REF ‧‧‧Reference current

I _OUT ‧‧‧Output current

M‧‧‧M factor

V _OS ‧‧‧ offset voltage

Claims (12)

[Item 1] A current mirror comprising:
a current source for generating a reference current;
a mirror circuit having a first node and a second node, the first node for passing a first mirror current, and the second node for passing a second mirror current;
a feedback circuit coupled to the mirror circuit for equalizing voltages on the first node and the second node; and an adjustable component coupled to the mirror circuit and configured by the feedback circuit The output is driven to provide a target output current. [Item 2] The current mirror of claim 1, wherein the adjustable component comprises:
a first output transistor coupled to the second node for outputting the target output current;
a second output transistor coupled to the second node and driven by the output of the operational amplifier; and an adjustable voltage source coupled to the gate terminal of the first output transistor and the second output Between the gate terminals of the transistor, an offset voltage is generated to provide the target output current. [Item 3] The current mirror of claim 2, wherein the adjustable voltage source is based on a carrier mobility, a gate oxide capacitor of a unit area, the first output transistor, and the second output transistor a width-to-length ratio, the target output current, the reference current, and an M factor of the first output transistor and an M factor of the second output transistor generate the offset voltage, and output current according to the target, the reference current The M factor of the first output transistor and the M factor of the second output transistor configure one polarity of the adjustable voltage source,
Wherein the adjustable voltage source generates a room temperature offset voltage, the room temperature offset voltage provides the target output current at room temperature, and a temperature dependent offset voltage to compensate for the output current due to a temperature change Change. [Item 4] The current mirror of claim 3, wherein the adjustable voltage source is based on a gate oxide capacitor of a unit area, a width ratio of the first output transistor and the second output transistor, and a chamber The temperature carrier mobility, the target output current, the reference current, the M factor of the first output transistor, and the M factor of the second output transistor generate the room temperature offset voltage, and the gate oxidation of the unit region At least one of a capacitance and the room temperature carrier mobility varies with different process angles, and the adjustable voltage source is based on the room temperature offset voltage, an operating temperature, and a room temperature difference, and a The temperature coefficient produces the temperature dependent offset voltage, wherein the temperature coefficient is determined based on a temperature index of one of the carrier mobility and the room temperature. [Item 5] The current mirror of claim 2, wherein the offset voltage generated by the adjustable voltage source is temperature independent,
The reference current generated by the current source is temperature dependent to compensate for the change in the output current due to a temperature change.
And wherein the current source generates a room temperature reference current and a temperature dependent reference current,
The current source generates the temperature dependent reference current according to the room temperature reference current, a difference between an operating temperature and a room temperature, and a temperature coefficient, and the temperature coefficient is related to a temperature index of one carrier mobility, The room temperature, the reference current, the target output current, the carrier mobility, the gate oxidation capacitance of one unit region, the M factor of the first output transistor, and the M factor of the second output transistor. [Item 6] The current mirror of claim 1, wherein the mirror circuit comprises a first mirror transistor and a second mirror transistor, the first mirror transistor being coupled to the first node, the second The mirrored transistor is coupled to the second node,
The M factor of the first mirror transistor and the M factor of the second mirror transistor are used to compensate for a shift in the reference current at room temperature. [Item 7] A method of generating a target output current through a current mirror, comprising:
The current mirror is provided and includes:
a current source for generating a reference current;
a mirror circuit having a first node and a second node, the first node for passing a first mirror current, and the second node for passing a second mirror current;
a feedback circuit coupled to the mirror circuit for equalizing voltages on the first node and the second node; and an adjustable component coupled to the mirror circuit and configured by the feedback circuit The output is driven to provide a target output current. [Item 8] A method for generating a target output current through a current mirror according to claim 7 of the patent application, wherein the adjustable component further comprises:
Providing a first output transistor coupled to the second node for outputting the target output current;
Providing a second output transistor coupled to the second node and driven by the output of the operational amplifier; and providing an adjustable voltage source coupled to the gate terminal of the first output transistor and the first Between the gate terminals of the two output transistors, an offset voltage is generated. [Item 9] The method for generating a target output current through a current mirror according to claim 8 of the patent application, further comprising: a carrier mobility, a gate oxide capacitor of a unit area, the first output transistor, and the first The width-to-length ratio of the two output transistors, the target output current, the reference current, and the M factor of the first output transistor and the M factor of the second output transistor generate the offset voltage,
And the method for generating a target output current through a current mirror, further comprising: configuring the current according to the target output current, the reference current, the M factor of the first output transistor, and the M factor of the second output transistor Adjust one polarity of the voltage source,
The method for generating a target output current through a current mirror further includes adjusting the offset voltage to compensate for a change in the output current due to a temperature change. [Item 10] A method for generating a target output current through a current mirror according to claim 8 of the patent application, wherein adjusting the offset voltage further comprises:
Adjusting a room temperature offset voltage to provide the target output current at room temperature; and adjusting a temperature dependent offset voltage to compensate for variations in the output current due to the temperature change. [Item 11] The method for generating a target output current through a current mirror according to claim 8 of the patent application, further comprising adjusting the reference current generated by the current source to compensate for the change of the output current due to a temperature change;
The current source includes a room temperature reference current and a temperature dependent reference current.
Adjusting the reference current includes adjusting the temperature dependent reference current based on the room temperature reference current, a difference between an operating temperature and a room temperature, and a temperature coefficient. [Item 12] A current mirror circuit comprising:
a current source for generating a reference current;
a mirror circuit having a first node and a second node, the first node for passing a first mirror current, and the second node for passing a second mirror current;
a feedback circuit coupled to the mirror circuit for equalizing voltages on the first node and the second node; and an output transistor coupled to the mirror circuit and configured by the mirror circuit An output is driven to provide a target output current.