TW201642067A - Current mirror with tunable mirror ratio - Google Patents
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Abstract
Description
本發明是關於一種電流鏡,特別是一種可調式鏡射比率之電流鏡。The present invention relates to a current mirror, and more particularly to a current mirror having an adjustable mirror ratio.
電流鏡已廣泛使用於類比積體電路中。電流鏡產生輸出電流,此輸出電流係鏡射參考電流而得。本發明希望可調整輸出電流與參考電流之間的鏡射比率,以使輸出電流具有精確的數值。Current mirrors have been widely used in analog integrated circuits. The current mirror produces an output current that is mirrored by a reference current. The present invention contemplates that the mirror ratio between the output current and the reference current can be adjusted to provide an accurate value for the output current.
根據本發明之一實施例,提出一種電流鏡電路。電流鏡電路包括一電流源、一鏡射電路、一回饋電路及一可調整元件。電流源用以產生一參考電流;鏡射電路具有一第一節點及一第二節點,第一節點用以使一第一鏡射電流通過,第二節點用以使一第二鏡射電流通過;回饋電路耦接至鏡射電路,用以使第一節點及第二節點上之電壓相等;以及可調整元件耦接至鏡射電路,並由回饋電路之一輸出所驅動以提供一目標輸出電流。According to an embodiment of the invention, a current mirror circuit is proposed. The current mirror circuit includes a current source, a mirror circuit, a feedback circuit and an adjustable component. The current source is configured to generate a reference current; the mirror circuit has a first node and a second node, the first node is for passing a first mirror current, and the second node is for passing a second mirror current The feedback circuit is coupled to the mirror circuit for equalizing the voltages on the first node and the second node; and the adjustable component is coupled to the mirror circuit and driven by the output of one of the feedback circuits to provide a target output Current.
根據本發明之另一實施例,提出一種用以透過一電流鏡產生一目標輸出電流的方法。透過電流鏡產生目標輸出電流的方法包括提供電流鏡,電流鏡包含一電流源、一鏡射電路、一回饋電路及一可調整元件。電流源用以產生一參考電流;鏡射電路具有一第一節點及一第二節點,第一節點用以使一第一鏡射電流通過,第二節點用以使一第二鏡射電流通過;回饋電路耦接至該鏡射電路,用以使該第一節點及該第二節點上之電壓相等;以及可調整元件耦接至該鏡射電路,並由該回饋電路之一輸出所驅動以提供一目標輸出電流。In accordance with another embodiment of the present invention, a method for generating a target output current through a current mirror is presented. The method of generating a target output current through a current mirror includes providing a current mirror, the current mirror including a current source, a mirror circuit, a feedback circuit, and an adjustable component. The current source is configured to generate a reference current; the mirror circuit has a first node and a second node, the first node is for passing a first mirror current, and the second node is for passing a second mirror current a feedback circuit coupled to the mirror circuit for equalizing voltages on the first node and the second node; and an adjustable component coupled to the mirror circuit and driven by an output of the feedback circuit To provide a target output current.
根據本發明之進一步之一實施例,提出一種電流鏡電路。電流鏡電路包括一電流源、一鏡射電路、一回饋電路及一輸出電晶體。電流源用以產生一參考電流;鏡射電路具有一第一節點及一第二節點,第一節點用以使一第一鏡射電流通過,第二節點用以使一第二鏡射電流通過;回饋電路耦接至鏡射電路,用以使第一節點及第二節點上之電壓相等;以及輸出電晶體耦接至鏡射電路,並由回饋電路之一輸出所驅動以提供一目標輸出電流。According to a further embodiment of the invention, a current mirror circuit is provided. The current mirror circuit includes a current source, a mirror circuit, a feedback circuit and an output transistor. The current source is configured to generate a reference current; the mirror circuit has a first node and a second node, the first node is for passing a first mirror current, and the second node is for passing a second mirror current The feedback circuit is coupled to the mirror circuit for equalizing the voltages on the first node and the second node; and the output transistor is coupled to the mirror circuit and driven by the output of one of the feedback circuits to provide a target output Current.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式作詳細說明。In order to provide a better understanding of the above and other aspects of the present invention, the embodiments are described in detail below.
100、300、500、700、900、1200、1400‧‧‧電路
110、310、510、910‧‧‧電流源
120、130、330、340、350、360、540、550‧‧‧節點
210、410、610、640、810、1010、1110、1310‧‧‧橫座標
220、420、620、650、820、1020、1120、1320‧‧‧縱座標
230、240、430、440、630、660‧‧‧線
312、512‧‧‧鏡射電路
314、514‧‧‧回饋電路
316‧‧‧輸出電晶體
320、520、1430‧‧‧運算放大器
516‧‧‧可調整元件
530‧‧‧可調整電壓源
710‧‧‧溫度獨立電壓源
720‧‧‧溫度相依電壓源
831、832、833、834、835、1031、1032、1033、1034、1035、1131、1132、1133、1134、1135、1331、1332、1333、1334、1335‧‧‧曲線
930‧‧‧電壓源
1410‧‧‧電壓計數電路
1420‧‧‧齊納二極體
N0、N1、N2‧‧‧N型金氧半導體電晶體
P0、P1、P2、P3、P4、P5、D1、D2‧‧‧P型金氧半導體電晶體
R1‧‧‧第一電阻
R2‧‧‧第二電阻
VDD‧‧‧供應電壓
IREF‧‧‧參考電流
IOUT‧‧‧輸出電流
M‧‧‧M因子
VOS‧‧‧偏移電壓100, 300, 500, 700, 900, 1200, 1400‧‧‧ circuits
110, 310, 510, 910‧‧‧ current source
120, 130, 330, 340, 350, 360, 540, 550‧‧‧ nodes
210, 410, 610, 640, 810, 1010, 1110, 1310‧‧‧ cross-width coordinates
220, 420, 620, 650, 820, 1020, 1120, 1320‧‧ ‧ ordinates
Lines 230, 240, 430, 440, 630, 660‧‧
312, 512‧‧ ‧ mirror circuit
314, 514‧‧‧ feedback circuit
316‧‧‧Output transistor
320, 520, 1430‧‧‧Operational Amplifier
516‧‧‧Adjustable components
530‧‧‧Adjustable voltage source
710‧‧‧ Temperature independent voltage source
720‧‧‧temperature dependent voltage source
831, 832, 833, 834, 835, 1031, 1032, 1033, 1034, 1035, 1131, 1132, 1133, 1134, 1135, 1331, 1332, 1333, 1334, 1335‧‧
930‧‧‧voltage source
1410‧‧‧Voltage counting circuit
1420‧‧‧Zina diode
N0, N1, N2‧‧‧N type MOS transistor
P0, P1, P2, P3, P4, P5, D1, D2‧‧‧P type MOS transistor
R1‧‧‧first resistance
R2‧‧‧second resistance
V DD ‧‧‧ supply voltage
I REF ‧‧‧Reference current
I OUT ‧‧‧Output current
M‧‧‧M factor
V OS ‧‧‧ offset voltage
第1圖繪示依照一實施例的傳統電流鏡電路的電路圖。
第2圖為第1圖之傳統電流鏡電路的鏡射特徵之電腦模擬結果。
第3圖繪示依照一實施例的電流鏡電路的電路圖。
第4圖為第3圖之電流鏡電路的鏡射特徵之電腦模擬結果。
第5圖繪示依照一實施例的電流鏡電路的電路圖。
第6A圖繪示依照一實施例之第5圖之偏移電壓與P型金氧半導體電晶體的汲-源極電流之間的關係圖。
第6B圖繪示第6A圖所示之關係的誤差。
第7圖繪示依照一實施例的電流鏡電路的電路圖。
第8圖為第7圖之電流鏡電路的溫度補償特徵之電腦模擬結果。
第9圖繪示依照一實施例的電流鏡電路的電路圖。
第10圖為第9圖之電流鏡電路的溫度補償特徵之電腦模擬結果。
第11圖為當室溫參考電流偏移時之第9圖之電流鏡電路的溫度補償特徵之電腦模擬結果。
第12圖繪示依照一實施例的電流鏡電路的電路圖。
第13圖為當室溫參考電流偏移時之第12圖之電流鏡電路的溫度補償特徵之電腦模擬結果。
第14圖繪示依照一實施例的電流鏡電路的電路圖。
FIG. 1 is a circuit diagram of a conventional current mirror circuit in accordance with an embodiment.
Figure 2 is a computer simulation of the mirroring characteristics of the conventional current mirror circuit of Figure 1.
FIG. 3 is a circuit diagram of a current mirror circuit in accordance with an embodiment.
Figure 4 is a computer simulation of the mirroring characteristics of the current mirror circuit of Figure 3.
FIG. 5 is a circuit diagram of a current mirror circuit in accordance with an embodiment.
6A is a graph showing the relationship between the offset voltage of FIG. 5 and the 汲-source current of the P-type MOS transistor according to an embodiment.
Fig. 6B is a diagram showing the error of the relationship shown in Fig. 6A.
FIG. 7 is a circuit diagram of a current mirror circuit in accordance with an embodiment.
Figure 8 is a computer simulation of the temperature compensation characteristics of the current mirror circuit of Figure 7.
FIG. 9 is a circuit diagram of a current mirror circuit in accordance with an embodiment.
Figure 10 is a computer simulation of the temperature compensation characteristics of the current mirror circuit of Figure 9.
Figure 11 is a computer simulation of the temperature compensation characteristics of the current mirror circuit of Figure 9 when the room temperature reference current is shifted.
Figure 12 is a circuit diagram of a current mirror circuit in accordance with an embodiment.
Figure 13 is a computer simulation of the temperature compensation characteristics of the current mirror circuit of Figure 12 when the room temperature reference current is shifted.
Figure 14 is a circuit diagram of a current mirror circuit in accordance with an embodiment.
本發明可藉由以下實施例並配合所附圖式之詳細說明而更為清楚。於圖式與實施方式中,相同或相似的參考標號係用以表示相同或類似的部分。The invention will be more apparent from the following detailed description of the appended claims. In the drawings and embodiments, the same or similar reference numerals are used to refer to the same or similar parts.
第1圖繪示依照一實施例的傳統電流鏡電路100(以下稱為“電路100”)的電路圖。電路100包括電流源110、N型金氧半導體(NMOS)電晶體N0至N2、及P型金氧半導體(PMOS)電晶體P0至P5。N型金氧半導體電晶體N0包括汲極端、閘極端及源極端,其中汲極端耦接至電流源110產生的參考電流IREF 、閘極端耦接至汲極端、源極端耦接至參考電壓(例如接地)。N型金氧半導體電晶體N1包括汲極端、閘極端及源極端,其中汲極端耦接至節點120、閘極端耦接至N型金氧半導體電晶體N0的閘極端、源極端耦接至地面。N型金氧半導體電晶體N2包括汲極端、閘極端及源極端,其中汲極端耦接至節點130、閘極端耦接至N型金氧半導體電晶體N0的閘極端、及源極端耦接至地面。P型金氧半導體電晶體P0包括源極端、閘極端及汲極端,其中源極端耦接至供應電壓VDD 、閘極端耦接至節點120、汲極端耦接至P型金氧半導體電晶體P2。P型金氧半導體電晶體P1包括源極端、閘極端及汲極端,其中源極端耦接至供應電壓VDD 、閘極端耦接至節點120、汲極端耦接至P型金氧半導體電晶體P3。P型金氧半導體電晶體P2包括源極端、閘極端及汲極端,其中源極端耦接至P型金氧半導體電晶體P0的汲極端、閘極端耦接至節點130、汲極端耦接至節點120。P型金氧半導體電晶體P3包括源極端、閘極端及汲極端,其中源極端耦接至P型金氧半導體電晶體P1的汲極端、閘極端耦接至節點130、汲極端耦接至節點130。P型金氧半導體電晶體P4包括源極端、閘極端及汲極端,其中源極端耦接至供應電壓VDD 、閘極端耦接至節點120、汲極端耦接至P型金氧半導體電晶體P5。P型金氧半導體電晶體P5包括源極端、閘極端及汲極端,其中源極端耦接至P型金氧半導體電晶體P4的汲極端、閘極端耦接至節點130、汲極端耦接至外部電路(未繪示)以輸出輸出電流IOUT 。1 is a circuit diagram of a conventional current mirror circuit 100 (hereinafter referred to as "circuit 100") in accordance with an embodiment. The circuit 100 includes a current source 110, N-type metal oxide semiconductor (NMOS) transistors N0 to N2, and P-type metal oxide semiconductor (PMOS) transistors P0 to P5. The N-type MOS transistor N0 includes a 汲 terminal, a gate terminal and a source terminal, wherein the 汲 terminal is coupled to the reference current I REF generated by the current source 110, the gate terminal is coupled to the 汲 terminal, and the source terminal is coupled to the reference voltage ( For example, grounding). The N-type MOS transistor N1 includes a 汲 terminal, a gate terminal and a source terminal, wherein the 汲 terminal is coupled to the node 120, the gate terminal is coupled to the gate terminal of the N-type MOS transistor N0, and the source terminal is coupled to the ground. . The N-type MOS transistor N2 includes a 汲 terminal, a gate terminal and a source terminal, wherein the 汲 terminal is coupled to the node 130, the gate terminal is coupled to the gate terminal of the N-type MOS transistor N0, and the source terminal is coupled to ground. The P-type MOS transistor P0 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the supply voltage V DD , the gate terminal is coupled to the node 120 , and the 汲 terminal is coupled to the P-type MOS transistor P 2 . . The P-type MOS transistor P1 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the supply voltage V DD , the gate terminal is coupled to the node 120 , and the 汲 terminal is coupled to the P-type MOS transistor P3 . . The P-type MOS transistor P2 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the 汲 terminal of the P-type MOS transistor P0, the gate terminal is coupled to the node 130, and the 汲 terminal is coupled to the node. 120. The P-type MOS transistor P3 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the 汲 terminal of the P-type MOS transistor P1, the gate terminal is coupled to the node 130, and the 汲 terminal is coupled to the node. 130. The P-type MOS transistor P4 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the supply voltage V DD , the gate terminal is coupled to the node 120, and the 汲 terminal is coupled to the P-type MOS transistor P5. . The P-type MOS transistor P5 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the 汲 terminal of the P-type MOS transistor P4, the gate terminal is coupled to the node 130, and the 汲 terminal is coupled to the external portion. A circuit (not shown) outputs an output current I OUT .
在電路100中,每個N型金氧半導體電晶體N0至N2及P型金氧半導體電晶體P0至P5皆具有10微米(μm)/10微米(μm)的閘極寬長比(W/L),及M因子皆為1。其中,M因子係為一個電晶體中單位電晶體並聯的個數。In the circuit 100, each of the N-type MOS transistors N0 to N2 and the P-type MOS transistors P0 to P5 has a gate width to length ratio of 10 μm / μm (μm) (W/ L), and the M factor are all 1. Wherein, the M factor is the number of unit transistors connected in parallel in one transistor.
理想地,所有的N型金氧半導體電晶體N0至N2、及P型金氧半導體電晶體P0至P5在飽和區中工作。在飽和區中,電晶體的汲-源極電流IDS
係由下列式子所決定:
(1)
其中VGS
為電晶體的閘-源極電壓,VTH
為電晶體的門檻電壓(threshold voltage),μ為載流子遷移率(charge-carrier mobility),Cox
為單位區域的閘極氧化電容(gate oxide capacitance per unit area),M為M因子,W為閘極寬度,以及L為閘極長度。Ideally, all of the N-type MOS transistors N0 to N2 and P-type MOS transistors P0 to P5 operate in the saturation region. In the saturation region, the 汲-source current I DS of the transistor is determined by the following equation:
(1)
Where V GS is the gate-source voltage of the transistor, V TH is the threshold voltage of the transistor, μ is the charge-carrier mobility, and C ox is the gate oxidized capacitance per unit area. (gate oxide capacitance per unit area), M is the M factor, W is the gate width, and L is the gate length.
因此,當所有的N型金氧半導體電晶體N0至N2、及P型金氧半導體電晶體P0至P5在飽和區中工作時,由於N型金氧半導體電晶體N0至N2的閘-源極電壓VGS 都相同,所以N型金氧半導體電晶體N0至N2的汲-源極電流IDS 都相同。相似地,由於P型金氧半導體電晶體P0、P1及P4的閘-源極電壓VGS 都相同,所以P型金氧半導體電晶體P0、P1及P4的汲-源極電流IDS 都相同。P型金氧半導體電晶體P2、P3及P5的汲-源極電流IDS 分別相同於P型金氧半導體電晶體P0、P1及P4的汲-源極電流IDS 。因此,每一個N型金氧半導體電晶體N0至N2及P型金氧半導體電晶體P0至P5皆具有等同於參考電流IREF 的汲-源極電流IDS 。如此,電路100的鏡射比率為1:1,也就是輸出電流IOUT 與參考電流IREF 之間的比率為1:1。Therefore, when all of the N-type MOS transistors N0 to N2 and the P-type MOS transistors P0 to P5 operate in the saturation region, due to the gate-source of the N-type MOS transistors N0 to N2 The voltages V GS are all the same, so the 汲-source currents I DS of the N-type MOS transistors N0 to N2 are the same. Similarly, since the gate-source voltages V GS of the P-type MOS transistors P0, P1, and P4 are the same, the 汲-source currents I DS of the P-type MOS transistors P0, P1, and P4 are the same. . P-type MOS transistor P2, P3 and P5 of the drain - source current I DS are identical to the P-type MOS transistors P0, P1 and P4 of the drain - source current I DS. Therefore, each of the N-type MOS transistors N0 to N2 and the P-type MOS transistors P0 to P5 has a 汲-source current I DS equivalent to the reference current I REF . As such, the mirror ratio of the circuit 100 is 1:1, that is, the ratio between the output current I OUT and the reference current I REF is 1:1.
然而,當參考電流IREF
小的時候(例如微安培等級或更小),P型金氧半導體電晶體P0至P4可離開飽和區及進入線性區。在線性區中,電晶體的汲-源極電流IDS
係由下列式子所決定:
(2)However, when the reference current I REF is small (for example, microamperes or less), the P-type MOS transistors P0 to P4 can leave the saturation region and enter the linear region. In the linear region, the 汲-source current I DS of the transistor is determined by the following equation:
(2)
根據式(2),在線性區中,電晶體的汲-源極電流IDS 不僅和閘-源極電壓VGS 相關,也與汲-源極電壓VDS 相關。因此,P型金氧半導體電晶體P0的VDS_P0 與P型金氧半導體電晶體P4的VDS_P4 之間的差異,將導致P型金氧半導體電晶體P0的IDS_P0 與P型金氧半導體電晶體P4的IDS_P4 之間的差異。這樣的差異在電路100的鏡射比率中係為誤差。According to equation (2), in the linear region, the 汲-source current I DS of the transistor is related not only to the gate-source voltage V GS but also to the 汲-source voltage V DS . Thus, the difference between the P-type MOS transistor P0, V DS_P0 the P-type MOS electric crystal and P4 V DS_P4, I DS_P0 will cause the P-type MOS P-type metal-oxide-semiconductor power transistor P0, The difference between I DS_P4 of crystal P4. Such a difference is an error in the mirror ratio of the circuit 100.
第2圖為電路100的鏡射特徵之電腦模擬結果。在第2圖中,橫座標210表示參考電流IREF (安培(A)),縱座標220表示比率誤差(例如鏡射比率的誤差與其理想情況相比)。線230係使用快-快(MOS_FF)轉角模組(corner model)所模擬的結果,表示比率誤差對應電路100之IREF 。快-快轉角模組(以下稱為“low-VTH 偏斜轉角”)假設電路100中所有P型金氧半導體電晶體及N型金氧半導體電晶體使用最低VTH ’s所製造。線240係使用慢-慢(MOS_SS)轉角模組所模擬的結果,表示比率誤差對應電路100之IREF 。慢-慢轉角模組假設電路100中所有P型金氧半導體電晶體及N型金氧半導體電晶體使用最高VTH ’s所製造。如第2圖所示,當參考電流IREF 小於1.24微安培(µA)時,使用low-VTH 偏斜轉角模組之比率誤差大於0.8%。Figure 2 is a computer simulation of the mirroring characteristics of circuit 100. In Fig. 2, the abscissa 210 represents the reference current I REF (amperes (A)), and the ordinate 220 represents the ratio error (e.g., the error of the mirror ratio is compared to its ideal case). Line 230 is a result simulated by a fast-fast (MOS_FF) corner model and represents the I REF of the ratio error corresponding circuit 100. The fast-fast corner module (hereinafter referred to as "low-V TH skew corner") assumes that all P-type MOS transistors and N-type MOS transistors in circuit 100 are fabricated using the lowest VTH 's. Line 240 is the result of the simulation simulated by the slow-slow (MOS_SS) corner module, representing the I REF of the ratio error corresponding circuit 100. The slow-slow corner module assumes that all P-type MOS transistors and N-type MOS transistors in circuit 100 are fabricated using the highest V TH 's. As shown in Figure 2, when the reference current I REF is less than 1.24 microamperes (μA), the ratio error of the low-V TH skew corner module is greater than 0.8%.
第3圖繪示依照一實施例的電流鏡電路300(以下稱為“電路300”)的電路圖。電路300包括回饋路徑,使P型金氧半導體電晶體P0及P1的汲-源極電流相等,以降低比率誤差。FIG. 3 is a circuit diagram of a current mirror circuit 300 (hereinafter referred to as "circuit 300") in accordance with an embodiment. The circuit 300 includes a feedback path that equalizes the 汲-source currents of the P-type MOS transistors P0 and P1 to reduce the ratio error.
請參考第3圖,電路300包括電流源310、鏡射電路312、回饋電路314、及輸出電晶體316。鏡射電路312包括N型金氧半導體電晶體N0至N2、P型金氧半導體電晶體P0至P3,P型金氧半導體電晶體P0至P3的功用為電路300的鏡射電晶體(mirroring transistor)。回饋電路314包括運算放大器320。輸出電晶體316包括P型金氧半導體電晶體P4。N型金氧半導體電晶體N0包括汲極端、閘極端及源極端,其中汲極端耦接至電流源310產生的參考電流IREF 、閘極端耦接至汲極端、源極端耦接至參考電壓(例如接地)。N型金氧半導體電晶體N1包括汲極端、閘極端及源極端,其中汲極端耦接至節點330、閘極端耦接至N型金氧半導體電晶體N0的閘極端、源極端耦接至地面。N型金氧半導體電晶體N2包括汲極端、閘極端及源極端,其中汲極端耦接至節點340、閘極端耦接至N型金氧半導體電晶體N0的閘極端、源極端耦接至地面。P型金氧半導體電晶體P0包括汲極端、閘極端及源極端,其中源極端耦接至供應電壓VDD 、閘極端耦接至節點330、汲極端耦接至節點350。P型金氧半導體電晶體P1包括汲極端、閘極端及源極端,其中源極端耦接至供應電壓VDD 、閘極端耦接至節點330、汲極端耦接至節點360。P型金氧半導體電晶體P2包括汲極端、閘極端及源極端,其中源極端耦接至節點350、閘極端耦接至節點340、汲極端耦接至節點330。P型金氧半導體電晶體P3包括汲極端、閘極端及源極端,其中源極端耦接至節點360、閘極端耦接至節點340、汲極端耦接至節點340。P型金氧半導體電晶體P4包括汲極端、閘極端及源極端,其中源極端耦接至節點360、閘極端耦接至運算放大器320、汲極端耦接至外部電路(未繪示)以輸出輸出電流IOUT。運算放大器320包括非反向端(符號為“+”)、反向端(符號為“-”)及輸出端,其中非反向端耦接至節點360、反向端耦接至耦接至節點350、輸出端耦接至P型金氧半導體電晶體P4的閘極端。Referring to FIG. 3, the circuit 300 includes a current source 310, a mirror circuit 312, a feedback circuit 314, and an output transistor 316. The mirror circuit 312 includes N-type MOS transistors N0 to N2 and P-type MOS transistors P0 to P3, and the functions of the P-type MOS transistors P0 to P3 are mirror transistors of the circuit 300. . The feedback circuit 314 includes an operational amplifier 320. The output transistor 316 includes a P-type MOS transistor P4. The N-type MOS transistor N0 includes a 汲 terminal, a gate terminal and a source terminal, wherein the 汲 terminal is coupled to the reference current I REF generated by the current source 310, the gate terminal is coupled to the 汲 terminal, and the source terminal is coupled to the reference voltage ( For example, grounding). The N-type MOS transistor N1 includes a 汲 terminal, a gate terminal and a source terminal, wherein the 汲 terminal is coupled to the node 330, the gate terminal is coupled to the gate terminal of the N-type MOS transistor N0, and the source terminal is coupled to the ground. . The N-type MOS transistor N2 includes a 汲 terminal, a gate terminal and a source terminal, wherein the 汲 terminal is coupled to the node 340, the gate terminal is coupled to the gate terminal of the N-type MOS transistor N0, and the source terminal is coupled to the ground. . The P-type MOS transistor P0 includes a 汲 terminal, a gate terminal, and a source terminal, wherein the source terminal is coupled to the supply voltage V DD , the gate terminal is coupled to the node 330 , and the NMOS terminal is coupled to the node 350 . The P-type MOS transistor P1 includes a 汲 terminal, a gate terminal, and a source terminal, wherein the source terminal is coupled to the supply voltage V DD , the gate terminal is coupled to the node 330 , and the NMOS terminal is coupled to the node 360 . The P-type MOS transistor P2 includes a 汲 terminal, a gate terminal, and a source terminal, wherein the source terminal is coupled to the node 350, the gate terminal is coupled to the node 340, and the NMOS terminal is coupled to the node 330. The P-type MOS transistor P3 includes a 汲 terminal, a gate terminal, and a source terminal, wherein the source terminal is coupled to the node 360, the gate terminal is coupled to the node 340, and the NMOS terminal is coupled to the node 340. The P-type MOS transistor P4 includes a 汲 terminal, a gate terminal and a source terminal, wherein the source terminal is coupled to the node 360, the gate terminal is coupled to the operational amplifier 320, and the 汲 terminal is coupled to an external circuit (not shown) for output. Output current IOUT. The operational amplifier 320 includes a non-inverting terminal (symbol "+"), an inverting terminal (symbol "-"), and an output terminal, wherein the non-inverting terminal is coupled to the node 360, and the inverting terminal is coupled to the coupling end. The node 350 and the output end are coupled to the gate terminal of the P-type MOS transistor P4.
每個N型金氧半導體電晶體N0至N2及P型金氧半導體電晶體P0至P4皆具有10微米(μm)/10微米(μm)的寬長(W/L)比。P型金氧半導體電晶體P1的M因子MP1 為2。其他電晶體的M因子為1,例如N型金氧半導體電晶體N0至N2及P型金氧半導體電晶體P0、P2至P4的M因子為1。在一些實施例中,P型金氧半導體電晶體P1包括兩個並聯的單位電晶體元件,且每個N型金氧半導體電晶體N0至N2及P型金氧半導體電晶體P0、P2至P4只包括一個單位電晶體元件。在其他實施例中,P型金氧半導體電晶體P1在製造時具有閘極寬度W,其閘極寬度W為其他N型金氧半導體電晶體N0至N2及P型金氧半導體電晶體P0、P2至P4的閘極寬度的兩倍大。Each of the N-type MOS transistors N0 to N2 and the P-type MOS transistors P0 to P4 has a width (W/L) ratio of 10 μm / 10 μm. The M factor M P1 of the P-type MOS transistor P1 is 2. The other factors have an M factor of 1, for example, N-type oxynitride transistors N0 to N2 and P-type MOS transistors P0, P2 to P4 have an M factor of 1. In some embodiments, the P-type MOS transistor P1 includes two unit transistors in parallel, and each of the N-type MOS transistors N0 to N2 and the P-type MOS transistors P0, P2 to P4 Only one unit transistor component is included. In other embodiments, the P-type MOS transistor P1 has a gate width W at the time of manufacture, and the gate width W is other N-type MOS transistors N0 to N2 and P-type MOS transistors P0, The gate width of P2 to P4 is twice as large.
運算放大器320及P型金氧半導體電晶體P4組成電路300的回饋路徑。具體來說,運算放大器320的非反向端接收P型金氧半導體電晶體P1的汲-源極電壓VDS_P1 。運算放大器320的反向端接收P型金氧半導體電晶體P0的汲-源極電壓VDS_P0 。運算放大器320產生輸出電壓以驅動P型金氧半導體電晶體P4。輸出電壓與P型金氧半導體電晶體P0的汲-源極電壓VDS_P0 與P型金氧半導體電晶體P1的汲-源極電壓VDS_P1 之間的差異成正比。當VDS_P1 >VDS_P0 ,輸出電壓等於G·(VDS_P1 -VDS_P0 ),其中G為運算放大器320的放大率。運算放大器320的輸出電壓應用至P型金氧半導體電晶體P4的閘極端,藉此降低P型金氧半導體電晶體P4之源極端的電壓。運算放大器320的輸出電壓可透過VDS_P1 與VDS_P0 之間的差異而被調整,直到VDS_P1 =VDS_P0 。因此,運算放大器320使VDS_P1 及VDS_P0 相等。The operational amplifier 320 and the P-type MOS transistor P4 constitute a feedback path of the circuit 300. Specifically, the non-inverting terminal of the operational amplifier 320 receives the 汲-source voltage V DS_P1 of the P-type MOS transistor P1. The inverting terminal of the operational amplifier 320 receives the 汲-source voltage V DS_P0 of the P-type MOS transistor P0. The operational amplifier 320 generates an output voltage to drive the P-type MOS transistor P4. Output voltage MOS transistor P0 of the P-type drain - source voltage V DS_P0 MOS transistor and a P-type drain of P1 - proportional to a difference between the source voltage V DS_P1. When V DS_P1 >V DS_P0 , the output voltage is equal to G·(V DS_P1 -V DS_P0 ), where G is the amplification of the operational amplifier 320. The output voltage of the operational amplifier 320 is applied to the gate terminal of the P-type MOS transistor P4, thereby lowering the voltage at the source terminal of the P-type MOS transistor P4. The output voltage of operational amplifier 320 can be adjusted by the difference between V DS_P1 and V DS_P0 until V DS_P1 = V DS_P0 . Therefore, the operational amplifier 320 makes V DS_P1 and V DS_P0 equal.
在實施上,節點350使第一鏡射電流通過,第一鏡射電流為P型金氧半導體電晶體P0的汲-源極電流IDS_P0 。由於電晶體N0、N1、P0及P2的M因子為1,因此第一鏡射電流與參考電流IREF 相同。此外,節點360使第二鏡射電流通過,第二鏡射電流為P型金氧半導體電晶體P1的汲-源極電流IDS_P1 。當參考電流IREF 小的時候,P型金氧半導體電晶體P0及P1在線性區中工作,且MP1 /MP0 = 2,根據式(2),第二鏡射電流為第一鏡射電流的兩倍大。也就是說,IDS_P1 = 2·IDS_P0 = 2·IREF 。由於P型金氧半導體電晶體P4耦接至節點360,P型金氧半導體電晶體P4所提供的輸出電流IOUT 與第二鏡射電流相關。根據克希荷夫電流定律(Kirchhoff’s current law),在節點360,第二鏡射電流等於N型金氧半導體電晶體N2的汲-源極電流IDS_N2 與P型金氧半導體電晶體P4汲-源極電流IDS_P4 (也就是輸出電流IOUT )的總和。也就是說,IDS_P1 = IDS_N2 + IOUT 。由於IDS_N2 = IREF , IOUT = IDS_P1 -IDS_N2 = IREF 。因此,即使當P型金氧半導體電晶體P0及P1在線性區中工作,輸出電流IOUT 與參考電流IREF 也會相同。In practice, node 350 passes a first mirror current through which the first mirror current is the 汲-source current I DS_P0 of P-type MOS transistor P0. Since the M factor of the transistors N0, N1, P0, and P2 is 1, the first mirror current is the same as the reference current I REF . Further, node 360 passes a second mirror current through which the second mirror current is the 汲-source current I DS_P1 of the P-type MOS transistor P1. When the reference current I REF is small, the P-type MOS transistors P0 and P1 operate in the linear region, and M P1 /M P0 = 2, according to the equation (2), the second mirror current is the first mirror The current is twice as large. That is, I DS_P1 = 2·I DS_P0 = 2·I REF . Since the P-type MOS transistor P4 is coupled to the node 360, the output current I OUT provided by the P-type MOS transistor P4 is related to the second mirror current. According to Kirchhoff's current law, at node 360, the second mirror current is equal to the 汲-source current I DS_N2 of the N-type MOS transistor N2 and the P-type MOS transistor P4 汲- The sum of the source currents I DS_P4 (that is, the output current I OUT ). That is, I DS_P1 = I DS_N2 + I OUT . Since I DS_N2 = I REF , I OUT = I DS_P1 -I DS_N2 = I REF . Therefore, even when the P-type MOS transistors P0 and P1 operate in the linear region, the output current I OUT and the reference current I REF are the same.
第4圖為電路300的鏡射特徵之電腦模擬結果。在第4圖中,橫座標410表示參考電流IREF (安培(A)),縱座標420表示比率誤差。線430係使用快-快轉角模組所模擬的結果,表示比率誤差對應電路300之IREF 。線440係使用慢-慢轉角模組所模擬的結果,表示比率誤差對應電路300之IREF 。如第4圖所示,只有當參考電流IREF 小於550奈安培(nA)時,使用low-VTH 偏斜轉角模組之比率誤差大於0.8%。Figure 4 is a computer simulation of the mirroring characteristics of circuit 300. In Fig. 4, the abscissa 410 represents the reference current I REF (amperes (A)), and the ordinate 420 represents the ratio error. Line 430 is the result of the simulation using the fast-fast corner module and represents the I REF of the ratio error corresponding circuit 300. Line 440 is the result of the simulation using the slow-slow corner module and represents the I REF of the ratio error corresponding circuit 300. As shown in Figure 4, the ratio error of the low-V TH skew corner module is greater than 0.8% only when the reference current I REF is less than 550 nanoamperes (nA).
第5圖繪示依照一實施例的電流鏡電路500(以下稱為“電路500”)的電路圖。電路500包括可調整元件,可調整元件在回饋路徑內,使電路500的鏡射比率可調整至目標值,且目標值不完全由金氧半導體電晶體的M因子所決定。FIG. 5 is a circuit diagram of a current mirror circuit 500 (hereinafter referred to as "circuit 500") in accordance with an embodiment. The circuit 500 includes an adjustable component that is within the feedback path such that the mirror ratio of the circuit 500 can be adjusted to a target value, and the target value is not entirely determined by the M factor of the MOS transistor.
請參考第5圖,電路500包括電流源510、鏡射電路512、回饋電路514以及可調整元件516。鏡射電路512包括N型金氧半導體電晶體N0至N2以及P型金氧半導體電晶體P0至P3,P型金氧半導體電晶體P0至P3的功用為電路500的鏡射電晶體。回饋電路514包括運算放大器520。可調整元件516包括P型金氧半導體電晶體D1及D2及可調整電壓源530。P型金氧半導體電晶體D1及D2的作用為電路500的輸出電晶體。電流源510、N型金氧半導體電晶體N0至N2、P型金氧半導體電晶體P0至P3、及運算放大器520的耦接方式類似於電路300中之電流源310、N型金氧半導體電晶體N0至N2、P型金氧半導體電晶體P0至P3、及運算放大器320的耦接方式。因此,耦接關係的詳細描述在此不多贅述。Referring to FIG. 5, circuit 500 includes current source 510, mirror circuit 512, feedback circuit 514, and adjustable component 516. The mirror circuit 512 includes N-type MOS transistors N0 to N2 and P-type MOS transistors P0 to P3, and the P-type MOS transistors P0 to P3 function as a mirror transistor of the circuit 500. The feedback circuit 514 includes an operational amplifier 520. The adjustable component 516 includes P-type MOS transistors D1 and D2 and an adjustable voltage source 530. The P-type MOS transistors D1 and D2 function as output transistors of the circuit 500. The current source 510, the N-type MOS transistors N0 to N2, the P-type MOS transistors P0 to P3, and the operational amplifier 520 are coupled in a manner similar to the current source 310 and the N-type MOS semiconductor in the circuit 300. The coupling manner of the crystals N0 to N2, the P-type MOS transistors P0 to P3, and the operational amplifier 320. Therefore, the detailed description of the coupling relationship will not be repeated here.
相較於電路300,電路500包括可調整元件516位於電路300之P型金氧半導體電晶體P4的位置。可調整元件516耦接至電路500的回饋路徑內,以提供目標輸出電流。具體來說,運算放大器520包括非反向端(符號為“+”)、反向端(符號為“-”)以及輸出端,其中非反向端耦接至節點540,節點540為P型金氧半導體電晶體P3的源極端、反向端耦接至節點550,節點550為P型金氧半導體電晶體P0的汲極端、輸出端耦接至P型金氧半導體電晶體D2。P型金氧半導體電晶體D1包括源極端、閘極端及汲極端,其中源極端耦接至節點540、閘極端耦接至可調整電壓源530、汲極端耦接至外部電路(未繪示)以輸出輸出電流IOUT 。P型金氧半導體電晶體D2包括源極端、閘極端及汲極端,其中源極端耦接至節點540、閘極端耦接至可運算放大器520的輸出端、汲極端耦接至外部電路。P型金氧半導體電晶體D1及D2皆由運算放大器520來驅動。可調整電壓源530包括正端(符號為“+”)及負端(符號為“-”),其中正端耦接至P型金氧半導體電晶體P2的閘極端、負端耦接至P型金氧半導體電晶體D1的閘極端。In contrast to circuit 300, circuit 500 includes an adjustable component 516 at a location of P-type MOS transistor P4 of circuit 300. The adjustable component 516 is coupled to the feedback path of the circuit 500 to provide a target output current. Specifically, the operational amplifier 520 includes a non-inverting terminal (symbol "+"), an inverting terminal (symbol "-"), and an output terminal, wherein the non-inverting terminal is coupled to the node 540, and the node 540 is a P-type. The source terminal and the opposite end of the MOS transistor P3 are coupled to the node 550. The node 550 is the 汲 terminal of the P-type MOS transistor P0, and the output terminal is coupled to the P-type MOS transistor D2. The P-type MOS transistor D1 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the node 540, the gate terminal is coupled to the adjustable voltage source 530, and the 汲 terminal is coupled to an external circuit (not shown). To output the output current I OUT . The P-type MOS transistor D2 includes a source terminal, a gate terminal and a 汲 terminal, wherein the source terminal is coupled to the node 540, the gate terminal is coupled to the output of the operational amplifier 520, and the NMOS terminal is coupled to the external circuit. P-type MOS transistors D1 and D2 are all driven by an operational amplifier 520. The adjustable voltage source 530 includes a positive terminal (symbol "+") and a negative terminal (symbol "-"), wherein the positive terminal is coupled to the gate terminal of the P-type MOS transistor P2, and the negative terminal is coupled to the P terminal. The gate terminal of the MOS transistor D1.
每個N型金氧半導體電晶體N0至N2及P型金氧半導體電晶體P0至P3具有10微米(μm)/10微米(μm)的寬長(W/L)比。N型金氧半導體電晶體N0的M因子MN0 為4。P型金氧半導體電晶體P1的M因子MP1 為5。P型金氧半導體電晶體D1的M因子MD1 為7。P型金氧半導體電晶體D2的M因子MD2 為4。其他電晶體的M因子為1,也就是N型金氧半導體電晶體N1及N2、以及P型金氧半導體電晶體P0、P2及P3的M因子為1。Each of the N-type MOS transistors N0 to N2 and the P-type MOS transistors P0 to P3 has a width (W/L) ratio of 10 μm / 10 μm. The M factor M N0 of the N-type MOS transistor N0 is 4. The M factor M P1 of the P-type MOS transistor P1 is 5. The M factor M D1 of the P-type MOS transistor D1 is 7. The M factor M D2 of the P-type MOS transistor D2 is 4. The M factor of the other transistors is 1, that is, the M-factors of the N-type MOS transistors N1 and N2, and the P-type MOS transistors P0, P2, and P3 are 1.
在實施上,節點550使第一鏡射電流通過,第一鏡射電流為P型金氧半導體電晶體P0的汲-源極電流IDS_P0 ,且IDS_P0 = IREF /4。節點540使第二鏡射電流通過,第二鏡射電流為P型金氧半導體電晶體P1的汲-源極電流IDS_P1 ,且IDS_P1 = 5·IREF /4。根據克希荷夫電流定律,在節點540,第二鏡射電流等於N型金氧半導體電晶體N2的汲-源極電流IDS_N2 、P型金氧半導體電晶體D1的汲-源極電流IDS_D1 (也就是輸出電流IOUT )、以及P型金氧半導體電晶體D2的汲-源極電流IDS_D2 的總和。也就是說,IDS_P1 = IDS_N2 + IDS_D1 + IDS_D2 。因為,IDS_N2 = IREF /4, IDS_D1 + IDS_D2 = IDS_P1 -IDS_N2 = 5·IREF /4−IREF /4 = IREF 。In practice, node 550 passes a first mirror current through which the first mirror current is the 汲-source current I DS_P0 of P-type MOS transistor P0 and I DS_P0 = I REF /4. The node 540 passes the second mirror current, and the second mirror current is the 汲-source current I DS_P1 of the P-type MOS transistor P1, and I DS_P1 = 5·I REF /4. According to Kirchhoff's current law, at node 540, the second mirror current is equal to the 汲-source current I DS_N2 of the N-type MOS transistor N2 and the 汲-source current I of the P-type MOS transistor D1 The sum of DS_D1 (that is, the output current I OUT ) and the 汲-source current I DS_D2 of the P-type MOS transistor D2. That is, I DS_P1 = I DS_N2 + I DS_D1 + I DS_D2 . Because, I DS_N2 = I REF /4, I DS_D1 + I DS_D2 = I DS_P1 -I DS_N2 = 5·I REF /4−I REF /4 = I REF .
可調整電壓源530產生偏移電壓VOS ,偏移電壓VOS 應用在P型金氧半導體電晶體D2的閘-源極電壓VGS_D2 與P型金氧半導體電晶體D1的閘-源極電壓VGS_D1 之間。偏移電壓VOS 可被調整以得到目標輸出電流Itarget 。偏移電壓VOS 與目標輸出電流Itarget 之間的關係可由以下得到。An adjustable voltage source 530 generates an offset voltage V OS, the offset voltage V OS used in the P-type MOS transistor D2 of the gate - source voltage V GS_D2 gate MOS transistor and the P-type D1 - source voltage Between V GS_D1 . The offset voltage V OS can be adjusted to obtain a target output current I target . The relationship between the offset voltage V OS and the target output current I target can be obtained as follows.
首先,假設P型金氧半導體電晶體D1及D2在飽和區中工作。因此,根據式(1),每個P型金氧半導體電晶體D1及D2,
(3)
其中。First, it is assumed that the P-type MOS transistors D1 and D2 operate in a saturation region. Therefore, according to formula (1), each of the P-type MOS transistors D1 and D2,
(3)
among them .
偏移電壓VOS
在P型金氧半導體電晶體D1的閘-源極電壓VGS_D1
與P型金氧半導體電晶體D2的閘-源極電壓VGS_D2
之間建立差異。因此,偏移電壓VOS
可以下列表示,
(4)Offset voltage V OS at the gate the P-type MOS transistor D1 - Establishing a difference between the source voltage V GS_D2 - source voltage V GS_D1 MOS transistor and a P-type gate D2. Therefore, the offset voltage V OS can be expressed as follows.
(4)
為了使輸出電流(也就是P型金氧半導體電晶體D1的閘-源極電In order to make the output current (that is, the gate-source of the P-type MOS transistor D1)
流IDS_D1 )等於Itarget ,IDS_D1 應等於Itarget 。The stream I DS_D1 ) is equal to I target and I DS_D1 should be equal to I target .
由於IDS_D2
= IREF
-IDS_D1
,IDS_D2
= IREF
-Itarget
。如此,式(4)可被轉換成,
(5)Since I DS_D2 = I REF -I DS_D1 , I DS_D2 = I REF -I target . Thus, equation (4) can be converted into,
(5)
因此,根據式(5),藉由調整VOS ,電路500可產生目標輸出電Therefore, according to equation (5), by adjusting V OS , circuit 500 can generate target output power
流Itarget 。舉例來說,當IREF = 12.6微安培(µA),藉由如上所述的可調整元件516的配置,VOS 可被調整以使輸出電流IOUT = Itarget = 10微安培(µA)。因此,藉由調整偏移電壓VOS ,可達成想要的鏡射比率。Stream I target . For example, when I REF = 12.6 microamperes (μA), the V OS can be adjusted such that the output current I OUT = I target = 10 microamps (μA) by the configuration of the adjustable component 516 as described above. Therefore, by adjusting the offset voltage V OS , the desired mirror ratio can be achieved.
在電路500中,P型金氧半導體電晶體D1及D2的M因子不分別限制為7及4,且根據電路500的應用,其可為任何整數。當P型金氧半導體電晶體D1及D2的M因子改變時,偏移電壓VOS 也必須對應調整。In circuit 500, the M factors of P-type MOS transistors D1 and D2 are not limited to 7 and 4, respectively, and may be any integer depending on the application of circuit 500. When the M factor of the P-type MOS transistors D1 and D2 changes, the offset voltage V OS must also be adjusted accordingly.
在電路500中,可調整電壓源530的極性(也就是可調整電壓源530的正端及負端在電路500中的耦接關係)可基於參考電流IREF 、目標輸出電流Itarget 、及P型金氧半導體電晶體D1及D2的M因子而被決定。如果,則可調整電壓源530的正端耦接至P型金氧半導體電晶體D2的閘極端,以及可調整電壓源530的負端耦接至P型金氧半導體電晶體D1的閘極端,如第5圖所示。另一方面,如果,則可調整電壓源530的極性是相反的。也就是說,可調整電壓源530的正端耦接至P型金氧半導體電晶體D1的閘極端,以及可調整電壓源530的負端耦接至P型金氧半導體電晶體D2的閘極端。如果,則輸出電流IDS_D1 即為目標輸出電流Itarget 。在此實施例中,即由可調整電壓源530所產生的偏移電壓VOS 為0。因此,可調整電壓源530的極性可由上述兩種方式其中之一來配置。In circuit 500, the polarity of the adjustable voltage source 530 (ie, the coupling of the positive and negative terminals of the adjustable voltage source 530 in the circuit 500) can be based on the reference current I REF , the target output current I target , and P The M factor of the MOS transistors D1 and D2 is determined. in case The positive terminal of the adjustable voltage source 530 is coupled to the gate terminal of the P-type MOS transistor D2, and the negative terminal of the adjustable voltage source 530 is coupled to the gate terminal of the P-type MOS transistor D1, such as Figure 5 shows. On the other hand, if The polarity of the adjustable voltage source 530 is reversed. That is, the positive terminal of the adjustable voltage source 530 is coupled to the gate terminal of the P-type MOS transistor D1, and the negative terminal of the adjustable voltage source 530 is coupled to the gate terminal of the P-type MOS transistor D2. . in case Then, the output current I DS_D1 is the target output current I target . In this embodiment, the offset voltage V OS generated by the adjustable voltage source 530 is zero. Therefore, the polarity of the adjustable voltage source 530 can be configured by one of the two methods described above.
第6A圖繪示依照一實施例之偏移電壓VOS 與P型金氧半導體電晶體D1的汲-源極電流IDS_D1 之間的關係圖。在第6A圖中,橫座標610表示偏移電壓VOS (毫伏特(mV)),以及縱座標620表示P型金氧半導體電晶體D1的汲-源極電流IDS_D1 (微安培(μA))。線630表示偏移電壓VOS 與P型金氧半導體電晶體D1的汲-源極電流IDS_D1 之間的關係,其係由一階線性近似(first-order linear approximation)所獲得。第6B圖繪示依照一實施例之偏移電壓VOS 與P型金氧半導體電晶體D1的汲-源極電流IDS_D1 之間的關係之一階線性近似之誤差。在第6B圖中,橫座標640表示偏移電壓VOS (毫伏特(mV)),以及縱座標650表示由一階線性近似所獲得之汲-源極電流IDS_D1 的誤差(奈安培(nA))。線660表示偏移電壓VOS 與由一階線性近似所獲得之P型金氧半導體電晶體D1的汲-源極電流IDS_D1 的誤差之間的關係。FIG. 6A is a diagram showing the relationship between the offset voltage V OS and the 汲-source current I DS — D1 of the P-type MOS transistor D1 according to an embodiment. In FIG. 6A, the abscissa 610 represents the offset voltage V OS (millivolts (mV)), and the ordinate 620 represents the 汲-source current I DS_D1 of the P-type MOS transistor D1 (microamperes (μA) ). Line 630 represents the relationship between the offset voltage V OS and the 汲-source current I DS — D1 of the P-type MOS transistor D1, which is obtained by a first-order linear approximation. FIG. 6B illustrates an error in a linear approximation of the relationship between the offset voltage V OS and the 汲-source current I DS — D1 of the P-type MOS transistor D1 in accordance with an embodiment. In Fig. 6B, the abscissa 640 represents the offset voltage V OS (mV), and the ordinate 650 represents the error of the 汲-source current I DS_D1 obtained by the first-order linear approximation (nai pei (nA) )). Line 660 represents the relationship between the offset voltage V OS and the error of the 汲-source current I DS — D1 of the P-type MOS transistor D1 obtained by a first-order linear approximation.
第7圖繪示依照一實施例的電流鏡電路700(以下稱為“電路700”)的電路圖。電路700包括溫度相依電壓源(temperature dependent voltage source),以使電路700的輸出電流IOUT 為溫度獨立(temperature independent)。也就是說,輸出電流IOUT 不隨著電路700的操作溫度(也就是當電路700操作時的溫度)而改變。FIG. 7 is a circuit diagram of a current mirror circuit 700 (hereinafter referred to as "circuit 700") in accordance with an embodiment. Circuit 700 includes a temperature dependent voltage source such that output current I OUT of circuit 700 is temperature independent. That is, the output current I OUT does not change with the operating temperature of the circuit 700 (ie, the temperature when the circuit 700 is operating).
請參考第7圖,電路700包括電流源510、N型金氧半導體電晶體N0至N2、P型金氧半導體電晶體P0至P3、D1以及D2、及運算放大器520,以上的元件類似於電路500。不同於電路500的是,電路700包括溫度獨立電壓源710及溫度相依電壓源720,溫度獨立電壓源710及溫度相依電壓源720位於P型金氧半導體電晶體D1及D2之間。溫度獨立電壓源710產生室溫偏移電壓,室溫偏移電壓在室溫下為可調整的,以獲得目標輸出電流。溫度相依電壓源720產生溫度相依電壓,溫度相依電壓用以補償輸出電流的變化,其輸出電流變化係由於室溫與電路700操作溫度之間的變化所造成。Referring to FIG. 7, the circuit 700 includes a current source 510, N-type MOS transistors N0 to N2, P-type MOS transistors P0 to P3, D1 and D2, and an operational amplifier 520. The above components are similar to circuits. 500. Unlike circuit 500, circuit 700 includes a temperature independent voltage source 710 and a temperature dependent voltage source 720. Temperature independent voltage source 710 and temperature dependent voltage source 720 are located between P-type MOS transistors D1 and D2. The temperature independent voltage source 710 produces a room temperature offset voltage that is adjustable at room temperature to achieve a target output current. The temperature dependent voltage source 720 produces a temperature dependent voltage that is used to compensate for variations in the output current due to changes in room temperature and operating temperature of the circuit 700.
在電路700中,電流源510為溫度獨立源。也就是說,電流源510所產生的IREF 不會隨著電路700的操作溫度而改變。然而,電路700的電晶體的一些裝置參數,例如門檻電壓VTH 及載流子遷移率μ,可能隨著操作溫度而改變。在缺少溫度相依電壓源720的情況,即使在室溫下輸出電流IOUT 到達目標值,當操作溫度自室溫偏移時,輸出電流IOUT 可能也會從目標值偏移。為了保持IOUT 溫度獨立,溫度相依電壓源720產生溫度相依電壓以補償因為溫度變化所造成的電晶體的製成參數的改變。室溫偏移電壓、溫度相依電壓、及操作溫度T之間的關係,可由下列得出。In circuit 700, current source 510 is a temperature independent source. That is, the I REF generated by current source 510 does not change with the operating temperature of circuit 700. However, some of the device parameters of the transistor of circuit 700, such as threshold voltage VTH and carrier mobility [mu], may vary with operating temperature. In the absence of the temperature dependent voltage source 720, even if the output current I OUT reaches the target value at room temperature, the output current I OUT may be offset from the target value when the operating temperature is shifted from room temperature. To maintain I OUT temperature independence, the temperature dependent voltage source 720 generates a temperature dependent voltage to compensate for changes in the fabrication parameters of the transistor due to temperature variations. The relationship between the room temperature offset voltage, the temperature dependent voltage, and the operating temperature T can be derived from the following.
首先,載流子遷移率μ為溫度相依,其可表示為,
(6)
其中T0
為室溫,µ0
為當操作溫度為室溫T0
之載流子遷移率,µ為操作溫度T之載流子遷移率,以及α為本發明之金氧半導體電晶體的載流子遷移率µ之遷移率溫度指數。First, the carrier mobility μ is temperature dependent, which can be expressed as,
(6)
Where T 0 is room temperature, μ 0 is the carrier mobility when the operating temperature is room temperature T 0 , μ is the carrier mobility of the operating temperature T, and α is the loading of the MOS transistor of the present invention The mobility index of the mobility of the mobility μ.
載流子遷移率µ可使用一階泰勒展開式(first-order Taylor expansion)估計,
(7)
其中。The carrier mobility μ can be estimated using a first-order Taylor expansion.
(7)
among them .
當結合式(4)及式(7)可得到,
(8)
其中VOS
為偏移電壓,其係結合溫度獨立電壓源710及溫度相
依電壓源720所產生。When combined with formula (4) and formula (7),
(8)
Where V OS is an offset voltage, which is generated in conjunction with a temperature independent voltage source 710 and a temperature dependent voltage source 720.
假設P型金氧半導體電晶體D1的目標汲-源極電流(也就是電路700的目標輸出電流)在室溫下為I10
,以及P型金氧半導體電晶體D2的目標汲-源極電流在室溫下為I20
。也就是說,在室溫下,且。使得且。接著,式(8)可由下表示,
(9)It is assumed that the target 汲-source current of the P-type MOS transistor D1 (that is, the target output current of the circuit 700) is I 10 at room temperature, and the target 汲-source current of the P-type MOS transistor D2. I 20 at room temperature. That is, at room temperature, And . Make And . Then, the formula (8) can be represented by
(9)
偏移電壓VOS
可由室溫偏移電壓VOS0
及溫度係數TC表示,如下
(10)
其中VOS0
為溫度獨立電壓源710所產生之室溫偏移電壓,VOS0
·TC·ΔT為度相依電壓源720所產生之溫度相依電壓,以及TC為偏移電壓VOS
之溫度係數。The offset voltage V OS can be represented by a room temperature offset voltage V OS0 and a temperature coefficient TC, as follows
(10)
Where V OS0 is the room temperature offset voltage generated by the temperature independent voltage source 710, V OS0 · TC · ΔT is the temperature dependent voltage generated by the degree dependent voltage source 720, and TC is the temperature coefficient of the offset voltage V OS .
比較式(9)及式(10),室溫偏移電壓VOS0
及溫度係數TC可下列式子表示,
(11)
(12)Comparing equations (9) and (10), the room temperature offset voltage V OS0 and the temperature coefficient TC can be expressed by the following equation.
(11)
(12)
根據式(11),已知參考電流IREF ,根據式(11)可決定室溫偏移電壓VOS0 以得到室溫下之已知目標輸出電流I10 。也就是說,根據目標輸出電流I10 、參考電流IREF 、單位區域的閘極氧化電容Cox 、寬常比(W/L)、以及室溫載流子遷移率µ0,可決定室溫偏移電壓VOS0 。在一實施例中,當決定室溫偏移電壓VOS0 時,假設Cox 及µ0不隨著裝置製成而改變,也就是,Cox 及µ0都是一致的,不會因為不同的製程轉角(process corners)而改變,例如典型-典型轉角(MOS_TT corner),其所有的N型金氧半導體電晶體及P型金氧半導體電晶體具有典型VTH’s ,典型VTH’s 在最高VTH’s 及最低According to equation (11), the reference current I REF is known, and the room temperature offset voltage V OS0 can be determined according to equation (11) to obtain a known target output current I 10 at room temperature. That is, the room temperature deviation can be determined according to the target output current I 10 , the reference current I REF , the gate oxidizing capacitance C ox per unit area, the aspect ratio (W/L), and the room temperature carrier mobility μ0. Shift voltage V OS0 . In an embodiment, when the room temperature offset voltage V OS0 is determined, it is assumed that C ox and μ0 do not change with the device, that is, C ox and μ0 are consistent, and will not be due to different process corners. (process corners) change, such as typical-typical corner (MOS_TT corner), all N-type MOS transistors and P-type MOS transistors have typical V TH's , typical V TH's at the highest V TH's and lowest
的VTH’s 之間、快-快轉角(MOS_FF corner),其所有的N型金氧半導體電晶體及P型金氧半導體電晶體具有最低的VTH’s 、慢-慢轉角(MOS_SS corner),其所有的N型金氧半導體電晶體及P型金氧半導體電晶體具有最高的VTH’s 、快-慢轉角(MOS_FS corner),所有的N型金氧半導體電晶體具有最低的VTH’s ,及所有P型金氧半導體電晶體具有最高的VTH’s 、以及慢-快轉角(MOS_SF corner),所有的N型金氧半導體電晶體具有最高的VTH’s ,及所有P型金氧半導體電晶體具有最低的VTH’s 。一旦室溫偏移電Between the V TH's and the fast-fast corner (MOS_FF corner), all of the N-type MOS transistors and P-type MOS transistors have the lowest V TH's and the slow-slow corners (MOS_SS corner), all of which N-type MOS transistors and P-type MOS transistors have the highest V TH's and fast-slow corners (MOS_FS corner). All N-type MOS transistors have the lowest V TH's and all P-types. Metal oxide semiconductor transistors have the highest V TH's and slow-fast corners (MOS_SF corner), all N-type MOS transistors have the highest V TH's , and all P-type MOS transistors have the lowest V TH's . Once the room temperature is shifted
壓VOS0 決定後,室溫偏移電壓VOS0 就會是固定的且不會隨著電路700的操作期間的溫度變化而改變。此外,根據式(12),由於溫度係數TC不相關於溫度變化,VOS0 ·TC也不會隨著溫度改變。因此,在電路700的操作期間,偏移電壓VOS = VOS0 + VOS0 ·TC ΔT中,唯一的變數為溫度差異ΔT,其ΔT在操作溫度T與室溫T0之間。因此,偏移電壓VOS 會隨著溫度差異ΔT而改變,其可用來補償因為溫度變化所造成的電晶體的製程參數的改變。After the voltage V OS0 is determined, the room temperature offset voltage V OS0 will be fixed and will not change as the temperature during operation of the circuit 700 changes. Further, according to the equation (12), since the temperature coefficient TC is not related to the temperature change, V OS0 · TC does not change with temperature. Thus, during operation of circuit 700, the offset voltage V OS = V OS0 + V OS0 · TC ΔT, the only variable is the temperature difference ΔT, which ΔT is between the operating temperature T and the room temperature T0. Therefore, the offset voltage V OS changes with the temperature difference ΔT, which can be used to compensate for changes in the process parameters of the transistor due to temperature variations.
第8圖為電路700的溫度補償特徵之電腦模擬結果。在第8圖中,橫座標810表示操作溫度T (ºC),以及縱座標820表示實際輸出電流IOUT 與目標輸出電流I10 之間的輸出電流誤差Ierror (奈安培(nA))。曲線831表示輸出電流誤差Ierror 對應操作溫度(以下稱為“溫度補償誤差”),係使用慢-慢(MOS_SS)轉角模型所模擬之結果,其假設電路700中所有的P型金氧半導體電晶體及N型金氧半導體電晶體具有最高VTH’s 。曲線832表示溫度補償誤差,係使用快-慢(MOS_FS)轉角模型所模擬之結果,其假設所有的N型金氧半導體電晶體具有最低VTH’s 及P型金氧半導體電晶體具有最高VTH’s 。曲線833表示溫度補償誤差,係使用典型-典型(MOS_TT)轉角模型所模擬之結果,其假設所有的N型金氧半導體電晶體及P型金氧半導體電晶體具有典型VTH’s ,其中典型VTH’s 在最高VTH’s 與最Figure 8 is a computer simulation of the temperature compensation characteristics of circuit 700. In Fig. 8, the abscissa 810 represents the operating temperature T (oC), and the ordinate 820 represents the output current error I error (naiamper (nA)) between the actual output current I OUT and the target output current I 10 . Curve 831 represents the output current error I error corresponding to the operating temperature (hereinafter referred to as "temperature compensation error"), which is the result of simulation using the slow-slow (MOS_SS) corner model, which assumes all P-type MOS semiconductors in circuit 700. Crystal and N-type MOS transistors have the highest V TH's . Curve 832 represents the temperature compensation error, which is the result of the simulation using the fast-slow (MOS_FS) corner model, which assumes that all of the N-type MOS transistors have the lowest V TH's and the P-type MOS transistors have the highest V TH's . Curve 833 represents the temperature compensation error, which is the result of a typical-typical (MOS_TT) corner model, which assumes that all N-type MOS transistors and P-type MOS transistors have typical V TH's , with typical V TH's At the highest V TH's and most
低VTH’s 之間。曲線834表示溫度補償誤差,係使用慢-快(MOS_SF)轉角模型所模擬之結果,其假設所有的N型金氧半導體電晶體具有最高VTH’s ,及所有的P型金氧半導體電晶體具有最低VTH’s 。曲線835表示溫度補償誤差,係使用快-快(MOS_FF)轉角模型所模擬之結果,其假設所有的N型金氧半導體電晶體及P型金氧半導體電晶體具有最低VTH’s 。Between low V TH's . Curve 834 represents the temperature compensation error, which is the result of a slow-fast (MOS_SF) corner model, which assumes that all N-type MOS transistors have the highest V TH's and all P-type MOS transistors have the lowest V TH's . Curve 835 represents the temperature compensation error, which is the result of simulation using a fast-fast (MOS_FF) corner model, which assumes that all N-type MOS transistors and P-type MOS transistors have the lowest V TH's .
在模擬以產生如第8圖所示之結果的期間,IREF 被設定為12.6微安培(μA),以及根據式(11)決定VOS0 以在T0 時滿足Iout = I10 = 10uA,T0 為在每個製程轉角的溫度模擬範圍之中間溫度點。此外,溫度相依電壓VOS0 ·TC·ΔT假設為不可被調整。當要決定快-快轉角、慢-慢轉角、快-慢轉角、及慢-快轉角時,在典型-典型轉角模型的參數Cox 及 μ被用來當作這些轉角的Cox 及 μ。然而,以這樣的方式決定的溫度相依電壓VOS0 ·TC·ΔT不會追蹤P型金氧半導體電晶體及N型金氧半導體電晶體的製程變數。也就是說,裝置參數例如Cox 及 μ隨著裝置製造程序而改變,且在不同轉角製程也不相同,例如快-快轉角、慢-慢轉角、快-慢轉角、及慢-快轉角。在這些製程轉角中,Cox 及 μ的差異可能造成溫度補償誤差的變化。因此,如第8圖所示,曲線831至835表示在不同的製程轉角中之溫度補償誤差都不同。舉例來說,當操作溫度為120ºC時,快-快轉角模型所產生的溫度補償誤差幾乎是其他轉角模型所產生的溫度補償誤差的兩倍。以其他的例子來看,當操作溫度為-40ºC時,慢-慢轉角模型所產生的溫度補償誤差則高於其他轉角模型所產生的溫度補償誤差。During the simulation to produce the result as shown in Fig. 8, I REF is set to 12.6 microamperes (μA), and V OS0 is determined according to equation (11) to satisfy I out = I 10 = 10uA at T 0 , T 0 is the intermediate temperature point at the temperature simulation range of each process corner. Further, the temperature dependent voltage V OS0 · TC · ΔT is assumed to be unadjustable. To determine when the fast - fast corner, Slow - Slow rotation angle, fast - slow corner, and slow - when fast corner, typical - and the parameter μ C ox is typically used as corner model μ C ox and these corners. However, the temperature dependent voltage V OS0 · TC · ΔT determined in this manner does not track the process variables of the P-type MOS transistor and the N-type MOS transistor. That is, device parameters such as C ox and μ vary with the device manufacturing process and are also different at different corner processes, such as fast-fast corners, slow-slow corners, fast-slow corners, and slow-fast corners. In these process corners, the difference between C ox and μ may cause a change in temperature compensation error. Therefore, as shown in Fig. 8, the curves 831 to 835 indicate that the temperature compensation errors are different in different process corners. For example, when the operating temperature is 120oC, the temperature-compensation error produced by the fast-fast corner model is almost twice the temperature compensation error produced by other corner models. In other examples, when the operating temperature is -40oC, the temperature compensation error produced by the slow-slow corner model is higher than the temperature compensation error generated by other corner models.
在模擬產生如第8圖所示之結果的期間,Cox 及 μ皆會隨著不同的製程轉角而改變。然而本發明並不限於此。如果Cox 隨著不同的製程轉角而改變,而μ不會隨著不同的製程轉角而改變,則基於典型-典型轉角模型所決定的溫度相依電壓VOS0 ·TC·ΔT仍然不會追蹤製程變數。因此,溫度補償誤差在這些製程轉角都不同。During the simulation to produce the results as shown in Fig. 8, both C ox and μ will change with different process angles. However, the invention is not limited thereto. If C ox changes with different process angles and μ does not change with different process angles, the temperature dependent voltage V OS0 · TC·ΔT determined based on the typical-typical corner model still does not track process variables. . Therefore, the temperature compensation error is different at these process angles.
第9圖繪示依照一實施例的電流鏡電路900(以下稱為“電路900”)的電路圖。電路900包括溫度相依電壓源,以補償溫度變異。FIG. 9 is a circuit diagram of a current mirror circuit 900 (hereinafter referred to as "circuit 900") in accordance with an embodiment. Circuit 900 includes a temperature dependent voltage source to compensate for temperature variations.
請參考第9圖,電路900包括電流源910、N型金氧半導體電晶體N0至N2、P型金氧半導體電晶體P0至P3、D1以及D2、運算放大器520及電壓源930。電路900的電流源910、N型金氧半導體電晶體N0至N2、P型金氧半導體電晶體P0至P3、D1以及D2、運算放大器520及電壓源930的耦接方式類似於電路500的元件。每個N型金氧半導體電晶體N0至N2以及P型金氧半導體電晶體P0至P3、D1及D2具有10微米(μm)/10微米(μm)的寬長(W/L)比。N型金氧半導體電晶體N0的M因子MN0 為4。P型金氧半導體電晶體P1的M因子MP1 為5。P型金氧半導體電晶體D1的M因子MD1 為7。P型金氧半導體電晶體D2的M因子MD2 為4。其他電晶體的M因子為1,也就是N型金氧半導體電晶體N1及N2、以及P型金氧半導體電晶體P0、P2及P3的M因子為1。Referring to FIG. 9, the circuit 900 includes a current source 910, N-type MOS transistors N0 to N2, P-type MOS transistors P0 to P3, D1 and D2, an operational amplifier 520, and a voltage source 930. The current source 910 of the circuit 900, the N-type MOS transistors N0 to N2, the P-type MOS transistors P0 to P3, D1 and D2, the operational amplifier 520 and the voltage source 930 are coupled in a similar manner to the components of the circuit 500. . Each of the N-type MOS transistors N0 to N2 and the P-type MOS transistors P0 to P3, D1 and D2 has a width (W/L) ratio of 10 μm / 10 μm. The M factor M N0 of the N-type MOS transistor N0 is 4. The M factor M P1 of the P-type MOS transistor P1 is 5. The M factor M D1 of the P-type MOS transistor D1 is 7. The M factor M D2 of the P-type MOS transistor D2 is 4. The M factor of the other transistors is 1, that is, the M-factors of the N-type MOS transistors N1 and N2, and the P-type MOS transistors P0, P2, and P3 are 1.
在電路900中,電流源910為溫度相依電流源,其產生之參考電流IREF 會隨著操作溫度T的變化而改變。電壓源930為溫度獨立電壓源,其所產生的偏移電壓VOS 不會隨著操作溫度T的變化而改變。為了保持IOUT 溫度獨立,電流源910被配置用來提供參考電流IREF 以補償由於溫度變化所產生電晶體的製程參數改變,其中參考電流IREF 可基於操作溫度T而調整。參考電流IREF 與操作溫度T可由下列式子得出。In circuit 900, current source 910 is a temperature dependent current source that produces a reference current I REF that varies with operating temperature T. The voltage source 930 is a temperature independent voltage source whose offset voltage V OS does not change as the operating temperature T changes. To maintain I OUT temperature independence, current source 910 is configured to provide a reference current I REF to compensate for process parameter changes in the transistor due to temperature variations, wherein reference current I REF can be adjusted based on operating temperature T. The reference current I REF and the operating temperature T can be derived from the following equations.
首先,假設溫度相依參考電流IREF
可表示為,
(13)
其中I0
為在室溫T0
之參考電流,I0
·ΔT·TC為參考電流I0
之溫度相依部
分,及TC為參考電流IREF
之溫度係數。First, assume that the temperature dependent reference current I REF can be expressed as
(13)
Where I 0 is the reference current at room temperature T 0 , and I 0 ·ΔT·TC is the temperature dependent portion of the reference current I 0 , And TC is the temperature coefficient of the reference current I REF .
在室溫下,IDS_D1
= I10
,IDS_D2
= I20
,及IREF
= IDS_D1
+ IDS_D2
= I10
+I20
。因此,IDS_D2
可表示為,
(14)At room temperature, I DS_D1 = I 10 , I DS_D2 = I 20 , and I REF = I DS_D1 + I DS_D2 = I 10 +I 20 . Therefore, I DS_D2 can be expressed as,
(14)
結合式(4)及式(14),偏移電壓VOS
可表示為,
Combining equations (4) and (14), the offset voltage V OS can be expressed as
(15)
其中, 且。 (15)
among them And .
結合式(7)及式(15),偏移電壓VOS
可表示為,
(16)Combining equations (7) and (15), the offset voltage V OS can be expressed as
(16)
為了呈現偏移電壓VOS
溫度獨立,式(16)中與一階ΔT有關的式子必須消去。為了消去式(16)中與一階ΔT有關的式子,溫度係數TC可設為,
(17)In order to exhibit the offset voltage V OS temperature independence, the equation relating to the first order ΔT in equation (16) must be eliminated. In order to eliminate the equation related to the first order ΔT in the equation (16), the temperature coefficient TC can be set to
(17)
因此,偏移電壓VOS
可表示為,
(18)Therefore, the offset voltage V OS can be expressed as,
(18)
因此,在電路900中,根據式(13)及式(17)可決定參考電流IREF ,且根據式(18)可決定偏移電壓VOS 。如式(13)及式(17)所見,IREF 包括溫度獨立電流I0 及溫度相依I0 ·ΔT·TC電流,其中溫度獨立電流I0 用以在室溫下產生目標輸出電流,溫度相依I0 ·ΔT·TC電流用以補償溫度。Therefore, in the circuit 900, the reference current I REF can be determined according to the equations (13) and (17), and the offset voltage V OS can be determined according to the equation (18). As seen in equations (13) and (17), I REF includes temperature independent current I 0 and temperature dependent I 0 · ΔT · TC current, wherein temperature independent current I 0 is used to generate target output current at room temperature, temperature dependent The I 0 ·ΔT·TC current is used to compensate for the temperature.
類似於第7圖之電路700,電流源910可由溫度獨立電流源及溫度相依電流源來實現。在室溫T0 下,溫度獨立電流源產生參考電流I0 。溫度相依電流源產生溫度相依電流I0 ·ΔT·TC。Similar to circuit 700 of Figure 7, current source 910 can be implemented by a temperature independent current source and a temperature dependent current source. At room temperature T 0 , the temperature independent current source produces a reference current I 0 . The temperature dependent current source produces a temperature dependent current I 0 ·ΔT·TC.
第10圖為電路900的溫度補償特徵之電腦模擬結果。在第10圖中,橫座標1010表示操作溫度T (ºC),以及縱座標1020表示實際輸出電流IOUT 與目標輸出電流I10 之間的輸出電流誤差Ierror (奈安培(nA))。曲線1031表示溫度補償誤差,其係使用快-快(MOS_FF)轉角模型所模擬之結果。曲線1032表示溫度補償誤差,其係使用快-慢(MOS_FS)轉角模型所模擬之結果。曲線1033表示溫度補償誤差,其係使用典型-典型(MOS_TT)轉角模型所模擬之結果。曲線1034表示溫度補償誤差,係使用慢-快(MOS_SF)轉角模型所模擬之結果。曲線1035表示溫度補償誤差,係使用慢-慢(MOS_SS)轉角模型所模擬之結果。Figure 10 is a computer simulation of the temperature compensation characteristics of circuit 900. In Fig. 10, the abscissa 1010 represents the operating temperature T (oC), and the ordinate 1020 represents the output current error I error (naiamper (nA)) between the actual output current I OUT and the target output current I 10 . Curve 1031 represents the temperature compensation error, which is the result of the simulation using the fast-fast (MOS_FF) corner model. Curve 1032 represents the temperature compensation error, which is the result of the simulation using the fast-slow (MOS_FS) corner model. Curve 1033 represents the temperature compensation error, which is the result of simulation using a typical-typical (MOS_TT) corner model. Curve 1034 represents the temperature compensation error and is the result of the simulation using the slow-fast (MOS_SF) corner model. Curve 1035 represents the temperature compensation error and is the result of the simulation using the slow-slow (MOS_SS) corner model.
在模擬產生如第10圖所示之結果的期間,室溫參考電流I0 被設為12.6微安培(uA),以及根據式(18)決定偏移電壓VOS 以在每個製程轉角的溫度模擬範圍之中間溫度點滿足Iout = I10 = 10uA。此外,假設溫度相依電壓I0 ·ΔT·TC為不可被調整。根據式(17),IREF 之溫度係數TC與Cox 及 μ不相關,只與已知參數例如B1、B2、I0 、 I20 、 T0 及α相關。也就是說,IREF 之溫度相依部分I0 ·ΔT·TC較不受製程變數影響。因此,如第10圖,溫度補償誤差不會隨著不同的製程轉角而改變(如第8圖所示)。如此,電路900包括溫度相依電流源910,可減少溫度補償誤差在不同製程轉角的變化。During the simulation to produce the result as shown in Fig. 10, the room temperature reference current I 0 is set to 12.6 microamperes (uA), and the offset voltage V OS is determined according to equation (18) to the temperature at each process corner. The intermediate temperature point of the simulation range satisfies I out = I 10 = 10uA. Further, it is assumed that the temperature dependent voltage I 0 ·ΔT·TC is not adjustable. According to equation (17), the temperature coefficient TC of I REF is not related to C ox and μ, and is only related to known parameters such as B1, B2, I 0 , I 20 , T 0 and α. That is to say, the temperature dependent portion I 0 ·ΔT·TC of I REF is less affected by the process variable. Therefore, as shown in Figure 10, the temperature compensation error does not change with different process angles (as shown in Figure 8). As such, the circuit 900 includes a temperature dependent current source 910 that reduces variations in temperature compensation errors at different process corners.
第11圖為當室溫參考電流I0 偏移至I0 ’=90%·I0 時之電路900的溫度補償特徵之電腦模擬結果。在第11圖中,橫座標1110表示操作溫度T (ºC),以及縱座標1120表示輸出電流誤Figure 11 is a computer simulation of the temperature compensation characteristics of the circuit 900 when the room temperature reference current I 0 is shifted to I 0 ' = 90% · I 0 . In Fig. 11, the abscissa 1110 represents the operating temperature T (oC), and the ordinate 1120 represents the output current error.
差Ierror = IOUT - I10 (奈安培(nA)),其中I10 為10微安培(μA),且IOUT 係根據IREF 基於式(13)及式(17)所決定。其中式(17)之TC根據原始I0 = 12.6μA所決定,但式(13)之I0 則為I0 ’=90%·I0 。曲線1131表示溫度補償誤差,其係使用快-快(MOS_FF)轉角模型所模擬之結果。曲線1132表示溫度補償誤差,其係使用快-慢(MOS_FS)轉角模型所模擬之結果。曲線1133表示溫度補償誤差,其係使用典型-典型(MOS_TT)轉角模型所模擬之結果。曲線1134表示溫度補償誤差,係使用慢-快(MOS_SF)轉角模型所模擬之結果。曲線1135表示溫度補償誤差,係使用慢-慢(MOS_SS)轉角模型所模擬之結果。Difference I error = I OUT - I 10 (Nai'an (nA)), where I 10 is 10 microamperes (μA), and I OUT is determined according to I REF based on equations (13) and (17). Wherein the TC of the formula (17) is determined according to the original I 0 = 12.6 μA, but I 0 of the formula (13) is I 0 '=90%·I 0 . Curve 1131 represents the temperature compensation error, which is the result of the simulation using the fast-fast (MOS_FF) corner model. Curve 1132 represents the temperature compensation error, which is the result of the simulation using the fast-slow (MOS_FS) corner model. Curve 1133 represents the temperature compensation error, which is the result of simulation using a typical-typical (MOS_TT) corner model. Curve 1134 represents the temperature compensation error and is the result of the simulation using the slow-fast (MOS_SF) corner model. Curve 1135 represents the temperature compensation error and is the result of the simulation using the slow-slow (MOS_SS) corner model.
當I0 = 12.6 uA偏移至I0 ’ = 90%·I0 = 11.3 uA時,I0 ’ 大於目標輸出電流I10 = 10μA。雖然VOS 之極性及式(17)及式(18)裡I10 及B1 值均維持不變。然而I20 ’已由2.6 uA變為1.3 uA造成對應之B2 ’值()變小。將I20 ’與B2 ’代入式(17)及式(18)可得到對應I0 ’ 之VOS ’與TC’。然而VOS ’與TC’都大於對應I0 之VOS 與TC。這現象解釋第11圖所示之輸出電流誤差Ierror 從-40ºC到40ºC溫度區間範圍內係一負溫度相依特性。並且在125ºC對應五個製程轉角之輸出電流誤差Ierror 發散至最大。When I 0 = 12.6 uA is shifted to I 0 ' = 90% · I 0 = 11.3 uA, I 0 ' is greater than the target output current I 10 = 10μA. Although the polarity of V OS and the values of I 10 and B 1 in equations (17) and (18) remain unchanged. However, I 20 ' has changed from 2.6 uA to 1.3 uA resulting in a corresponding B 2 ' value ( ) becomes smaller. Substituting I 20 'and B 2 ' into equations (17) and (18) yields V OS ' corresponding to I 0 ' With TC' . However, V OS 'and TC' are both greater than V OS and TC corresponding to I 0 . This phenomenon explains the output current error I error shown in Fig. 11 from a temperature range of -40oC to 40oC, which is a negative temperature dependent characteristic. And the output current error I error corresponding to the five process corners at 125oC is diverged to the maximum.
第12圖繪示依照一實施例的電流鏡電路1200(以下稱為“電路1200”)的電路圖。電路1200包括P型金氧半導體電晶體P0及P1,其金氧半導體電晶體P0及P1具調整之M因子以補償偏移之I0 。FIG. 12 is a circuit diagram of a current mirror circuit 1200 (hereinafter referred to as "circuit 1200") in accordance with an embodiment. The circuit 1200 includes P-type MOS transistors P0 and P1, and the MOS transistors P0 and P1 have an adjusted M factor to compensate for the offset I 0 .
請參考第12圖,電路1200包括電流源910、N型金氧半導體電晶體N0至N2、P型金氧半導體電晶體P0至P3、D1以及D2、運算放大器520及電壓源930,其元件類似於電路900的元件。不同於電路900的是,P型金氧半導體電晶體P0的M因子MP0 為3、以及P型金氧半導體電晶體P1的M因子MP1 為16。Referring to FIG. 12, the circuit 1200 includes a current source 910, N-type MOS transistors N0 to N2, P-type MOS transistors P0 to P3, D1 and D2, an operational amplifier 520, and a voltage source 930. The components of circuit 900. Unlike the circuit 900, the M factor M P0 of the P-type MOS transistor P0 is 3, and the M factor M P1 of the P-type MOS transistor P1 is 16.
電路1200被應用在室溫參考電流I0 偏移至I0 ’=90%·I0 的情況中。如前所描述,當I0 偏移至I0 ’=90%·I0 時,IREF 之溫度相依部分也會根據90%的因子偏移。這將會導致不同製程轉角之溫度補償誤差,特別是在高溫區。然而,在電路1200中,MP1 /MP0 的比率被調整至5/1而不是16/3,以至於偏移電流I0 ’被放大1.083(=(16/3-1)/4)倍。因此,1.083 I0 ’等於97.49% (=1.083x0.9)的原始I0 。The circuit 1200 is applied in the case where the room temperature reference current I 0 is shifted to I 0 '=90%·I 0 . As previously described, when I 0 is offset to I 0 '=90%·I 0 , the temperature dependent portion of I REF is also offset by a factor of 90%. This will result in temperature compensation errors for different process corners, especially in high temperature zones. However, in circuit 1200, the ratio of M P1 /M P0 is adjusted to 5/1 instead of 16/3, so that the offset current I 0 ' is amplified by 1.083 (=(16/3-1)/4) times. . Therefore, 1.083 I 0 'is equal to 97.49% (=1.083x0.9) of the original I 0 .
在電路1200中,P型金氧半導體電晶體P0及P1的M因子分別為3及16。然而,本發明並不限於此,P型金氧半導體電晶體P0及P1的M因子可根據室溫參考電流I0 而被決定。舉例來說,為了調整P型金氧半導體電晶體P0及P1的M因子,電路1200可包括金氧半導體開關(未繪示),連接至每個P型金氧半導體電晶體P0及P1。當偵測到I0 的偏移時,金氧半導體開關可根據I0 的偏移調整P型金氧半導體電晶體P0及P1的M因子。In the circuit 1200, the M factors of the P-type MOS transistors P0 and P1 are 3 and 16, respectively. However, the present invention is not limited thereto, and the M factor of the P-type MOS transistors P0 and P1 can be determined according to the room temperature reference current I 0 . For example, to adjust the M factor of the P-type MOS transistors P0 and P1, the circuit 1200 may include a MOS switch (not shown) connected to each of the P-type MOS transistors P0 and P1. When the offset of I 0 is detected, the MOS switch can adjust the M factor of the P-type MOS transistors P0 and P1 according to the offset of I 0 .
第13圖為當室溫參考電流I0 偏移至I0 ’=90%·I0 時之電路1200的溫度補償特徵之電腦模擬結果。在第13圖中,橫座標1310表示操作溫度T (ºC),以及縱座標1320表示輸出電流誤Figure 13 is a computer simulation of the temperature compensation characteristics of circuit 1200 when room temperature reference current I 0 is shifted to I 0 ' = 90% · I 0 . In Fig. 13, the abscissa 1310 represents the operating temperature T (oC), and the ordinate 1320 represents the output current error.
差Ierror = IOUT -I10 (奈安培(nA)),其中I10 為10微安培(μA),且IOUT 係根據IREF 基於式(13)及式(17)所決定。其中式(17)之TC根據原始I0 = 12.6μA所決定,但式(13)之I0 則為I0 ’=90%·I0 。曲線1331表示溫度補償誤差,其係使用快-快(MOS_FF)轉角模型所模擬之結果。曲線1332表示溫度補償誤差,其係使用快-慢(MOS_FS)轉角模型所模擬之結果。曲線1333表示溫度補償誤差,其係使用典型-典型(MOS_TT)轉角模型所模擬之結果。曲線1334表示溫度補償誤差,係使用慢-快(MOS_SF)轉角模型所模擬之結果。曲線1335表示溫度補償誤差,係使用慢-慢(MOS_SS)轉角模型所模擬之結果。Difference I error = I OUT -I 10 (Nai'an (nA)), where I 10 is 10 microamperes (μA), and I OUT is determined according to I REF based on equations (13) and (17). Wherein the TC of the formula (17) is determined according to the original I 0 = 12.6 μA, but I 0 of the formula (13) is I 0 '=90%·I 0 . Curve 1331 represents the temperature compensation error, which is the result of the simulation using the fast-fast (MOS_FF) corner model. Curve 1332 represents the temperature compensation error, which is the result of the simulation using the fast-slow (MOS_FS) corner model. Curve 1333 represents the temperature compensation error, which is the result of simulation using a typical-typical (MOS_TT) corner model. Curve 1334 represents the temperature compensation error and is the result of the simulation using the slow-fast (MOS_SF) corner model. Curve 1335 represents the temperature compensation error and is the result of the simulation using the slow-slow (MOS_SS) corner model.
如前所描述,在電路1200中,由於P型金氧半導體電晶體P0及P1的M因子被調整放大至偏移的I0 ’,故即使當I0 偏移,輸出電流IOUT 也會保持在I10 。因此,第13圖之曲線1331至1335類似於第10圖之曲線1031至1035。也就是說相較於第11圖,第13圖之五個製程轉角於-40ºC及於125ºC的溫度補償誤差在數值上較為接近。例如於-40ºC及於125ºC的最大溫度補償差異,由第11圖之97.82奈安培降低至第13圖之36.22奈安培。As described above, in the circuit 1200, since the M factor of the P-type MOS transistors P0 and P1 is adjusted and amplified to the offset I 0 ', the output current I OUT is maintained even when I 0 is shifted. At I 10 . Therefore, the curves 1331 to 1335 of Fig. 13 are similar to the curves 1031 to 1035 of Fig. 10. That is to say, compared with Fig. 11, the temperature compensation errors of the five process angles of Fig. 13 at -40oC and 125oC are relatively close in value. For example, the maximum temperature compensation difference at -40oC and at 125oC is reduced from 97.82 nanoamperes in Figure 11 to 36.22 nanoamperes in Figure 13.
第14圖繪示依照一實施例的電流鏡電路1400(以下稱為“電路1400”)的電路圖。電路1400包括電壓計數電路,以實現電路500之電壓源530。FIG. 14 is a circuit diagram of a current mirror circuit 1400 (hereinafter referred to as "circuit 1400") in accordance with an embodiment. Circuit 1400 includes a voltage counting circuit to implement voltage source 530 of circuit 500.
請參考第14圖,電路1400包括電流源510、N型金氧半導體電晶體N0至N2、P型金氧半導體電晶體P0至P3、D1以及D2、運算放大器520及電壓計數電路1410。電流源510、N型金氧半導體電晶體N0至N2、P型金氧半導體電晶體P0至P3、D1以及D2、運算放大器520類似於第5圖之電路500的類似元件。Referring to FIG. 14, the circuit 1400 includes a current source 510, N-type MOS transistors N0 to N2, P-type MOS transistors P0 to P3, D1 and D2, an operational amplifier 520, and a voltage counting circuit 1410. The current source 510, the N-type MOS transistors N0 to N2, the P-type MOS transistors P0 to P3, D1 and D2, and the operational amplifier 520 are similar to the similar elements of the circuit 500 of FIG.
電壓計數電路1410連接至P型金氧半導體電晶體D2的閘極端與P型金氧半導體電晶體D1的閘極端之間。電壓計數電路1410包括齊納二極體1420、第一電阻R1、第二電阻R2、及運算放大器1430。齊納二極體1420包括第一端及第二端,其中第一端耦接至P型金氧半導體電晶體D2的閘極端,第二端耦接至第一電阻R1。第一電阻R1包括第一端及第二端,其中第一端耦接至齊納二極體1420的第二端,第二端耦接至第二電阻R2。第二電阻R2為可調整電阻,且包括第一端及第二端,其中第一端耦接至第一電阻R1、第二端耦接至P型金氧半導體電晶體D1的閘極端。運算放大器1430包括非反向端(符號為“+”)、反向端(符號為“-”)及輸出端,其中非反向端耦接至P型金氧半導體電晶體D2的閘極端、反向端耦接至第一電阻R1的第二端、輸出端耦接至P型金氧半導體電晶體D1的閘極端。The voltage counter circuit 1410 is connected between the gate terminal of the P-type MOS transistor D2 and the gate terminal of the P-type MOS transistor D1. The voltage counting circuit 1410 includes a Zener diode 1420, a first resistor R1, a second resistor R2, and an operational amplifier 1430. The Zener diode 1420 includes a first end and a second end, wherein the first end is coupled to the gate terminal of the P-type MOS transistor D2, and the second end is coupled to the first resistor R1. The first resistor R1 includes a first end and a second end, wherein the first end is coupled to the second end of the Zener diode 1420, and the second end is coupled to the second resistor R2. The second resistor R2 is an adjustable resistor, and includes a first end and a second end, wherein the first end is coupled to the first resistor R1 and the second end is coupled to the gate terminal of the P-type MOS transistor D1. The operational amplifier 1430 includes a non-inverting terminal (symbol "+"), an inverting terminal (symbol "-"), and an output terminal, wherein the non-inverting terminal is coupled to the gate terminal of the P-type MOS transistor D2, The opposite end is coupled to the second end of the first resistor R1 and the output end is coupled to the gate terminal of the P-type MOS transistor D1.
電壓計數電路1410的功用為可調整電壓源,其產生偏移電壓VOS ,應用於P型金氧半導體電晶體D1及D2之間。偏移電壓VOS 可由下列表示,The function of the voltage counter circuit 1410 is an adjustable voltage source that produces an offset voltage V OS applied between the P-type MOS transistors D1 and D2. The offset voltage V OS can be expressed by the following.
其中R1
為第一電阻R1的阻抗、R2
為第二電阻R2的阻抗、及VZ
為
齊納二極體1420的崩潰電壓。由於第二電阻R2為可調整電阻,因此可透過調整第二電阻R2的阻抗來調整VOS
。舉例來說,VOS
可根據式(5)而被調整,以至於電路1400的輸出電流IOUT
可為目標
Wherein R 1 is the impedance of the first resistor R1, R 2 is the impedance of the second resistor R2, and V Z is the breakdown voltage of the Zener diode 1420. Since the second resistor R2 is an adjustable resistor, the V OS can be adjusted by adjusting the impedance of the second resistor R2. For example, the V OS can be adjusted according to equation (5), so that the output current I OUT of the circuit 1400 can be the target
值Itarget 。The value I target .
電路300、500、700、900、1200及1400為金氧半導體電路。然而,本發明並不限於金氧半導體電路,可應用至場效電晶體(FET)電路、雙極接面電晶體(BJT)電路、雙極互補金氧半導體(BiCMOS)電路。Circuits 300, 500, 700, 900, 1200, and 1400 are MOS circuits. However, the present invention is not limited to a MOS circuit and can be applied to a field effect transistor (FET) circuit, a bipolar junction transistor (BJT) circuit, and a bipolar complementary metal oxide semiconductor (BiCMOS) circuit.
本發明實施例所揭露之電流鏡可應用至精確來源電流之電路系統,例如弛緩振盪器電路及電流比較儀等。The current mirror disclosed in the embodiments of the present invention can be applied to a circuit system of accurate source current, such as a relaxation oscillator circuit and a current comparator.
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。本發明之保護範圍並不因為實施例的描述而有所限制,當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. The scope of the present invention is not limited by the description of the embodiments, which are defined by the scope of the appended claims.
500‧‧‧電路 500‧‧‧ circuits
510‧‧‧電流源 510‧‧‧current source
520‧‧‧運算放大器 520‧‧‧Operational Amplifier
530‧‧‧可調整電壓源 530‧‧‧Adjustable voltage source
540、550‧‧‧節點 540, 550‧‧‧ nodes
N0、N1、N2‧‧‧N型金氧半導體電晶體 N0, N1, N2‧‧‧N type MOS transistor
P0、P1、P2、P3、D1、D2‧‧‧P型金氧半導體電晶體 P0, P1, P2, P3, D1, D2‧‧‧P type MOS transistor
VDD‧‧‧供應電壓 V DD ‧‧‧ supply voltage
IREF‧‧‧參考電流 I REF ‧‧‧Reference current
IOUT‧‧‧輸出電流 I OUT ‧‧‧Output current
M‧‧‧M因子 M‧‧‧M factor
VOS‧‧‧偏移電壓 V OS ‧‧‧ offset voltage
Claims (12)
一電流源,用以產生一參考電流;
一鏡射電路,具有一第一節點及一第二節點,該第一節點用以使一第一鏡射電流通過,該第二節點用以使一第二鏡射電流通過;
一回饋電路,耦接至該鏡射電路,用以使該第一節點及該第二節點上之電壓相等;以及
一可調整元件,耦接至該鏡射電路,並由該回饋電路之一輸出所驅動以提供一目標輸出電流。A current mirror comprising:
a current source for generating a reference current;
a mirror circuit having a first node and a second node, the first node for passing a first mirror current, and the second node for passing a second mirror current;
a feedback circuit coupled to the mirror circuit for equalizing voltages on the first node and the second node; and an adjustable component coupled to the mirror circuit and configured by the feedback circuit The output is driven to provide a target output current.
一第一輸出電晶體,耦接至該第二節點,用以輸出該目標輸出電流;
一第二輸出電晶體,耦接至該第二節點,並由該運算放大器之該輸出所驅動;以及
一可調整電壓源,耦接至該第一輸出電晶體之閘極端與該第二輸出電晶體之閘極端之間,用以產生一偏移電壓以提供該目標輸出電流。The current mirror of claim 1, wherein the adjustable component comprises:
a first output transistor coupled to the second node for outputting the target output current;
a second output transistor coupled to the second node and driven by the output of the operational amplifier; and an adjustable voltage source coupled to the gate terminal of the first output transistor and the second output Between the gate terminals of the transistor, an offset voltage is generated to provide the target output current.
其中該可調整電壓源產生一室溫偏移電壓,該室溫偏移電壓在室溫下提供該目標輸出電流,以及一溫度相依偏移電壓,以補償由於一溫度變化所產生之該輸出電流之變化。The current mirror of claim 2, wherein the adjustable voltage source is based on a carrier mobility, a gate oxide capacitor of a unit area, the first output transistor, and the second output transistor a width-to-length ratio, the target output current, the reference current, and an M factor of the first output transistor and an M factor of the second output transistor generate the offset voltage, and output current according to the target, the reference current The M factor of the first output transistor and the M factor of the second output transistor configure one polarity of the adjustable voltage source,
Wherein the adjustable voltage source generates a room temperature offset voltage, the room temperature offset voltage provides the target output current at room temperature, and a temperature dependent offset voltage to compensate for the output current due to a temperature change Change.
該可調整電壓源根據該室溫偏移電壓、一操作溫度與一室溫之一差異、及一溫度係數產生該溫度相依偏移電壓,其中該溫度係數係根據一載流子遷移率之一溫度指數及該室溫所決定。The current mirror of claim 3, wherein the adjustable voltage source is based on a gate oxide capacitor of a unit area, a width ratio of the first output transistor and the second output transistor, and a chamber The temperature carrier mobility, the target output current, the reference current, the M factor of the first output transistor, and the M factor of the second output transistor generate the room temperature offset voltage, and the gate oxidation of the unit region At least one of a capacitance and the room temperature carrier mobility varies with different process angles, and the adjustable voltage source is based on the room temperature offset voltage, an operating temperature, and a room temperature difference, and a The temperature coefficient produces the temperature dependent offset voltage, wherein the temperature coefficient is determined based on a temperature index of one of the carrier mobility and the room temperature.
該電流源所產生之該參考電流為溫度相依,以補償由於一溫度變化所產生之該輸出電流之變化,
且其中該電流源產生一室溫參考電流及一溫度相依參考電流,
該電流源根據該室溫參考電流、一操作溫度與一室溫之一差異、及一溫度係數產生該溫度相依參考電流,以及
該溫度係數相關於一載流子遷移率之一溫度指數、該室溫、該參考電流、該目標輸出電流、該載流子遷移率、一單位區域的閘極氧化電容、該第一輸出電晶體之M因子、及該第二輸出電晶體之M因子。The current mirror of claim 2, wherein the offset voltage generated by the adjustable voltage source is temperature independent,
The reference current generated by the current source is temperature dependent to compensate for the change in the output current due to a temperature change.
And wherein the current source generates a room temperature reference current and a temperature dependent reference current,
The current source generates the temperature dependent reference current according to the room temperature reference current, a difference between an operating temperature and a room temperature, and a temperature coefficient, and the temperature coefficient is related to a temperature index of one carrier mobility, The room temperature, the reference current, the target output current, the carrier mobility, the gate oxidation capacitance of one unit region, the M factor of the first output transistor, and the M factor of the second output transistor.
該第一鏡射電晶體之M因子及該第二鏡射電晶體之M因子係用以補償室溫下之該參考電流之一偏移。The current mirror of claim 1, wherein the mirror circuit comprises a first mirror transistor and a second mirror transistor, the first mirror transistor being coupled to the first node, the second The mirrored transistor is coupled to the second node,
The M factor of the first mirror transistor and the M factor of the second mirror transistor are used to compensate for a shift in the reference current at room temperature.
提供該電流鏡,包含:
一電流源,用以產生一參考電流;
一鏡射電路,具有一第一節點及一第二節點,該第一節點用以使一第一鏡射電流通過,該第二節點用以使一第二鏡射電流通過;
一回饋電路,耦接至該鏡射電路,用以使該第一節點及該第二節點上之電壓相等;以及
一可調整元件,耦接至該鏡射電路,並由該回饋電路之一輸出所驅動以提供一目標輸出電流。A method of generating a target output current through a current mirror, comprising:
The current mirror is provided and includes:
a current source for generating a reference current;
a mirror circuit having a first node and a second node, the first node for passing a first mirror current, and the second node for passing a second mirror current;
a feedback circuit coupled to the mirror circuit for equalizing voltages on the first node and the second node; and an adjustable component coupled to the mirror circuit and configured by the feedback circuit The output is driven to provide a target output current.
提供一第一輸出電晶體,耦接至該第二節點,用以輸出該目標輸出電流;
提供一第二輸出電晶體,耦接至該第二節點,並由該運算放大器之該輸出所驅動;以及
提供一可調整電壓源,耦接至該第一輸出電晶體之閘極端與該第二輸出電晶之閘極端之間,用以產生一偏移電壓。A method for generating a target output current through a current mirror according to claim 7 of the patent application, wherein the adjustable component further comprises:
Providing a first output transistor coupled to the second node for outputting the target output current;
Providing a second output transistor coupled to the second node and driven by the output of the operational amplifier; and providing an adjustable voltage source coupled to the gate terminal of the first output transistor and the first Between the gate terminals of the two output transistors, an offset voltage is generated.
且所述之透過一電流鏡產生一目標輸出電流的方法,更包括根據該目標輸出電流、該參考電流、該第一輸出電晶體之M因子及該第二輸出電晶體之M因子配置該可調整電壓源之一極性,
所述之透過一電流鏡產生一目標輸出電流的方法,更包括調整該偏移電壓以補償由於一溫度變化所產生之該輸出電流之變化。The method for generating a target output current through a current mirror according to claim 8 of the patent application, further comprising: a carrier mobility, a gate oxide capacitor of a unit area, the first output transistor, and the first The width-to-length ratio of the two output transistors, the target output current, the reference current, and the M factor of the first output transistor and the M factor of the second output transistor generate the offset voltage,
And the method for generating a target output current through a current mirror, further comprising: configuring the current according to the target output current, the reference current, the M factor of the first output transistor, and the M factor of the second output transistor Adjust one polarity of the voltage source,
The method for generating a target output current through a current mirror further includes adjusting the offset voltage to compensate for a change in the output current due to a temperature change.
調整一室溫偏移電壓,以在室溫下提供該目標輸出電流;以及
調整一溫度相依偏移電壓,以補償由於該溫度變化所產生之該輸出電流之變化。A method for generating a target output current through a current mirror according to claim 8 of the patent application, wherein adjusting the offset voltage further comprises:
Adjusting a room temperature offset voltage to provide the target output current at room temperature; and adjusting a temperature dependent offset voltage to compensate for variations in the output current due to the temperature change.
其中該電流源包含一室溫參考電流及一溫度相依參考電流,
調整該參考電流包括根據該室溫參考電流、一操作溫度與一室溫之一差異、及一溫度係數調整該溫度相依參考電流。The method for generating a target output current through a current mirror according to claim 8 of the patent application, further comprising adjusting the reference current generated by the current source to compensate for the change of the output current due to a temperature change;
The current source includes a room temperature reference current and a temperature dependent reference current.
Adjusting the reference current includes adjusting the temperature dependent reference current based on the room temperature reference current, a difference between an operating temperature and a room temperature, and a temperature coefficient.
一電流源,用以產生一參考電流;
一鏡射電路,具有一第一節點及一第二節點,該第一節點用以使一第一鏡射電流通過,該第二節點用以使一第二鏡射電流通過;
一回饋電路,耦接至該鏡射電路,用以使該第一節點及該第二節點上之電壓相等;以及
一輸出電晶體,耦接至該鏡射電路,並由該鏡射電路之一輸出所驅動以提供一目標輸出電流。
A current mirror circuit comprising:
a current source for generating a reference current;
a mirror circuit having a first node and a second node, the first node for passing a first mirror current, and the second node for passing a second mirror current;
a feedback circuit coupled to the mirror circuit for equalizing voltages on the first node and the second node; and an output transistor coupled to the mirror circuit and configured by the mirror circuit An output is driven to provide a target output current.
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