TWI573124B - Timing controller and method of outputting signal thereof - Google Patents

Description

Timing controller and signal output method thereof

The present invention relates to a timing controller, and more particularly to a timing controller and a signal output method thereof.

In modern times, electronic devices such as computers, televisions, mobile phones, personal digital assistants (PDAs), and digital cameras all transmit information through display control, making displays more and more important to people. Compared with the traditional image tube display, the flat panel display (FPD) has the advantages of light weight, small size, and no radiation, and has become the mainstream of display devices. In general, flat panel displays include timing controllers, source drivers, gate drivers, and panels.

Moreover, with the high resolution and multi-gray scale of the flat panel display, the amount of data between the timing controller and the source driver is rapidly increased, thereby causing data line data transmission, power consumption, and electromagnetic interference (Electromagnetic Interference, EMI) noise has also increased dramatically. Therefore, how to reduce the power consumption of the timing controller and electromagnetic interference becomes an important issue in designing the timing controller.

The invention provides a timing controller and a signal output method thereof, which can reduce power consumption and electromagnetic interference of a timing controller.

The timing controller of the present invention comprises a receiver, a main function circuit and a transmitter. The receiver receives an image differential signal to provide a data enable signal and a data signal. The main function circuit is coupled to the receiver to receive the data enable signal and the data signal, and provides the data enable signal and the data signal. The transmitter is coupled to the main function circuit to receive the data enable signal and the data signal to provide a source differential signal to a source driver according to the data signal, and adjust the swing amplitude of the source differential signal according to the data enable signal.

The signal output method of the timing controller of the present invention includes the following steps. The timing controller generates a data enable signal and a data signal according to an image differential signal. The timing controller provides a source differential signal to a source driver according to the data signal, and adjusts the swing amplitude of the source differential signal according to the data enable signal.

Based on the above, the timing controller and the signal output method thereof according to the embodiment of the present invention adjust the swing amplitude of the source differential signal supplied to the source driver according to the data enable signal to reduce power consumption and electromagnetic interference of the timing controller. .

The above described features and advantages of the invention will be apparent from the following description.

1 is a system diagram of a timing controller in accordance with an embodiment of the present invention. Referring to FIG. 1 , in the embodiment, the timing controller 100 is coupled to the source driver 10 and includes a receiver 110 , a main function circuit 120 , and a transmitter 130 . The receiver 110 receives the image differential signal DF_I from an external host (Host), and provides the data enable signal SDE and the data signal SDA to the main function circuit 120 according to the image differential signal DF_I. The main function circuit 120 is coupled to the receiver 110 to receive the data enable signal SDE and the data signal SDA, and to provide the data enable signal SDE and the data signal SDA to the transmitter 130. The transmitter 130 is coupled to the main function circuit 120 to receive the data enable signal SDE and the data signal SDA, and provides the source differential signal DF_S1 to the source driver 10 according to the data signal SDA, and adjusts the source difference according to the data enable signal SDE. The amplitude of the swing of the motion signal DF_S1.

2 is a schematic diagram of data combination of source differential signals according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2, in the embodiment, the source differential signal DF_S1 is used to sequentially transmit a plurality of clock bits BCK, and between the clock bits BCK, the source differential signal DF_S1 may be A plurality of control bits BC or a plurality of data bits BD or mixed transmission control bits BC and data bits BD are transmitted, which may be determined by those of ordinary skill in the art. Moreover, in the present embodiment, the transmitter 130 and the source driver 10 can be calibrated and synchronized by the clock bit BCK, so that the clock signal can be transmitted.

3 is a waveform diagram of a source differential signal and a data enable signal according to an embodiment of the invention. Referring to FIG. 1 to FIG. 3, in the embodiment, the data enable signal SDE is enabled to represent that the data can be transmitted. At this time, the source differential signal DF_S1 output by the transmitter 130 is meaningful; otherwise, the data enable signal SDE is prohibited. It can represent that the data is not transmitted. At this time, the source differential signal DF_S1 output by the transmitter 130 is meaningless. For example, the data enable signal SDE is disabled during the vertical blanking period VB and horizontal blanking period HB during one picture, and the data enable signal SDE is enabled for other times during this picture.

Therefore, when the data enable signal SDE is enabled, the transmitter 130 sets the swing amplitude of the source differential signal DF_S1 to a predetermined swing amplitude AP1, so that the source driver 10 can receive the data normally, that is, the correct When the data enable signal SDE is disabled, the transmitter 130 sets the swing amplitude of the source differential signal DF_S1 to the reduced swing amplitude AR1. As shown in FIG. 3, in the embodiment, the reduced swing amplitude AR1 is smaller than the preset swing amplitude AP1. In the embodiment of the present invention, the reduced swing amplitude AR1 may be 0 volts, that is, the source differential signal may be stopped. DF_S1.

According to the above, in the vertical blank period VB and the horizontal blank period HB, the swing amplitude of the data enable signal DF_S1 is reduced to reduce the power consumption and electromagnetic interference of the timing controller 100. Moreover, the enabling and disabling of the data enable signal SDE can be determined by a logic circuit, that is, the logic 130 can be configured in the transmitter 130 to determine the state of the data enable signal SDE, and correspondingly reduce the source differential signal DF_S1 The amplitude of the swing or stop output source differential signal DF_S1. The logic circuit can reduce the swing amplitude of the source differential signal DF_S1 or turn off the output buffer by adjusting the power supply voltage of the output buffer.

4 is a waveform diagram of a data enable signal, a vertical sync signal, and a horizontal sync signal according to an embodiment of the invention. Referring to FIG. 1 and FIG. 4, in the embodiment, the receiver 110 can further receive the vertical synchronization signal VS and the horizontal synchronization signal HS from the external host, and generate a data enable signal according to the vertical synchronization signal VS and the horizontal synchronization signal HS. SDE. For example, when one of the vertical synchronizing signal VS and the horizontal synchronizing signal HS is disabled, the receiver 110 disables the data enable signal SDE; when both the vertical synchronizing signal VS and the horizontal synchronizing signal HS are enabled, the receiver 110 enabled data enable signal SDE.

FIG. 5 is a schematic diagram of a system of a timing controller according to another embodiment of the present invention. Referring to FIG. 1, FIG. 4 and FIG. 5, the timing controller 500 is substantially the same as the timing controller 100, except that the transmitter 510 is different. In this embodiment, the transmitter 510 synchronously provides the source differential signal DF_S2 and the time differential signal DF_CK to the source driver 20, that is, the source differential signal DF_S2 is used to transmit the control bit BC and the data bit BD. The clock differential signal DF_CK is used to transmit the clock bit BCK. Moreover, the transmitter 510 also adjusts the amplitude of the swing of the source differential signal DF_S2 and the pulse differential signal DF_CK according to the data enable signal SDE.

FIG. 6 is a waveform diagram of a source differential signal and a data enable signal according to an embodiment of the invention. Referring to FIG. 5 and FIG. 6, in the embodiment, when the data enable signal SDE is enabled, the transmitter 510 sets the swing amplitude of the source differential signal DF_S2 to the preset swing amplitude AP2, and sets the clock. The swing amplitude of the differential signal DF_CK is set to a preset swing amplitude AP3 so that the source driver 50 can receive data normally; conversely, when the data enable signal SDE is disabled, the transmitter 510 sets the source differential signal DF_S2. The swing amplitude is set to reduce the swing amplitude AR2, and the swing amplitude of the clock differential signal DF_CK is set to the reduced swing amplitude AR3.

As shown in FIG. 6, in the present embodiment, the reduced swing amplitude AR2 is smaller than the preset swing amplitude AP2, and in the embodiment of the present invention, the reduced swing amplitude AR2 may be 0 volt. Moreover, in the present embodiment, the reduced swing amplitude AR3 is smaller than the preset swing amplitude AP3, and in the embodiment of the present invention, the reduced swing amplitude AR3 may also be 0 volt.

FIG. 7 is a flow chart of a signal output method of a timing controller according to an embodiment of the invention. Referring to FIG. 7, in the embodiment, the signal output method of the timing controller includes the following steps. First, the timing controller generates a data enable signal and a data signal based on the image differential signal (step S710). Then, the timing controller supplies the source differential signal to the source driver according to the data signal, and adjusts the swing amplitude of the source differential signal according to the data enable signal (step S720). The order of the steps S710 and S720 is used for the description, and the embodiment of the present invention is not limited thereto. The details of the steps S710 and S720 can be referred to the embodiment of FIG. 1 to FIG. 6 , and details are not described herein again.

In summary, the timing controller and the signal output method thereof according to the embodiment of the present invention adjust the swing amplitude of the source differential signal and the pulse differential signal provided to the source driver according to the data enable signal to reduce the timing. Controller power consumption and electromagnetic interference.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10, 50‧‧‧ source driver

100, 500‧‧‧ timing controller

110‧‧‧ Receiver

120‧‧‧ main function circuit

130, 510‧‧‧transmitters

AP1~AP3‧‧‧Preset swing amplitude

AR1~AR3‧‧‧ Reduced swing amplitude

BC‧‧‧ control bit

BCK‧‧‧ clock bits

BD‧‧‧ data bit

DF_CK‧‧‧ clock differential signal

DF_I‧‧‧image differential signal

DF_S1, DF_S2‧‧‧ source differential signal

HB‧‧‧ horizontal blank period

HS‧‧‧ horizontal sync signal

SDA‧‧‧ information signal

SDE‧‧‧ data enable signal

VB‧‧‧ vertical blank period

VS‧‧‧ vertical sync signal

S710, S720‧‧‧ steps

1 is a system diagram of a timing controller in accordance with an embodiment of the present invention. 2 is a schematic diagram of data combination of source differential signals according to an embodiment of the invention. 3 is a waveform diagram of a source differential signal and a data enable signal according to an embodiment of the invention. 4 is a waveform diagram of a data enable signal, a vertical sync signal, and a horizontal sync signal according to an embodiment of the invention. FIG. 5 is a schematic diagram of a system of a timing controller according to another embodiment of the present invention. FIG. 6 is a waveform diagram of a source differential signal and a data enable signal according to an embodiment of the invention. FIG. 7 is a flow chart of a signal output method of a timing controller according to an embodiment of the invention.

S710, S720‧‧‧ steps

Claims (16)

A timing controller includes: a receiver that receives an image differential signal to provide a data enable signal and a data signal; a main function circuit coupled to the receiver to receive the data enable signal and the data And providing a data enable signal and the data signal; and a transmitter coupled to the main function circuit to receive the data enable signal and the data signal to provide a source differential signal according to the data signal to a source driver, and adjusting a swing amplitude of the source differential signal according to the data enable signal; wherein the data enable signal is disabled during a vertical blank period and a plurality of horizontal blank periods during a picture, and the The data enable signal is enabled at other times during the picture. When the data enable signal is enabled, the amplitude of the source differential signal is a predetermined swing amplitude, and when the data enable signal is disabled The amplitude of the swing of the source differential signal is a reduced swing amplitude, wherein the reduced swing amplitude is less than the preset swing amplitude. The timing controller of claim 1, wherein the reduced swing amplitude is 0 volts. The timing controller of claim 1, wherein the source differential signal is used to sequentially transmit a plurality of clock bits, a plurality of control bits, and a plurality of data bits. The timing controller of claim 1, wherein the transmitter synchronously provides the source differential signal and a clock differential signal to the source driver, And the transmitter adjusts the swing amplitude of the clock differential signal according to the data enable signal. The timing controller of claim 4, wherein when the data enable signal is enabled, the swing amplitude of the clock differential signal is the preset swing amplitude, and when the data enable signal is disabled When possible, the swing amplitude of the clock differential signal is the reduced swing amplitude, wherein the reduced swing amplitude is less than the preset swing amplitude. The timing controller of claim 5, wherein the reduced swing amplitude is 0 volts. The timing controller of claim 1, wherein the receiver generates the data enable signal according to a vertical sync signal and a horizontal sync signal. The timing controller of claim 7, wherein when the one of the vertical synchronization signal and the horizontal synchronization signal is disabled, the data enable signal is disabled, and the vertical synchronization signal and the horizontal synchronization are When the signal is enabled, the data enable signal is enabled. A timing output signal output method includes: the timing controller generates a data enable signal and a data signal according to an image differential signal; and the timing controller provides a source differential signal according to the data signal to the first a source driver, and adjusting a swing amplitude of the source differential signal according to the data enable signal, wherein the data enable signal is disabled during a vertical blank period and a plurality of horizontal blank periods during a picture, and the data is caused The signal can be enabled at other times during the picture; The step of adjusting the swing amplitude of the source differential signal according to the data enable signal includes: when the data enable signal is enabled, the swing amplitude of the source differential signal is a preset swing amplitude: When the data enable signal is disabled, the amplitude of the swing of the source differential signal is a reduced swing amplitude, wherein the reduced swing amplitude is less than the preset swing amplitude. The signal output method of the timing controller according to claim 9, wherein the reduced swing amplitude is 0 volt. The signal output method of the timing controller according to claim 10, wherein the source differential signal is used to sequentially transmit a plurality of clock bits, a plurality of control bits, and a plurality of data bits. The signal output method of the timing controller according to claim 9, further comprising: the timing controller synchronously providing the source differential signal and a clock differential signal to the source driver, and according to the data The energy signal adjusts the swing amplitude of the clock differential signal. The signal output method of the timing controller according to claim 12, wherein the step of adjusting the swing amplitude of the clock differential signal according to the data enable signal comprises: when the data enable signal is enabled, The amplitude of the swing of the clock differential signal is the preset swing amplitude; When the data enable signal is disabled, the swing amplitude of the clock differential signal is the reduced swing amplitude, wherein the reduced swing amplitude is less than the preset swing amplitude. The signal output method of the timing controller according to claim 13, wherein the reduced swing amplitude is 0 volt. The signal output method of the timing controller according to claim 9, further comprising: the timing controller generating the data enable signal according to a vertical synchronization signal and a horizontal synchronization signal. The signal output method of the timing controller according to claim 15, wherein the step of the timing controller generating the data enable signal according to a vertical synchronization signal and a horizontal synchronization signal comprises: when the vertical synchronization signal and When one of the horizontal synchronizing signals is disabled, the data enabling signal is disabled: and when the vertical synchronizing signal and the horizontal synchronizing signal are both enabled, the data enabling signal is enabled.