TWI599998B - Display apparatus and operation method of timing controller thereof - Google Patents

Display apparatus and operation method of timing controller thereof Download PDF

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TWI599998B
TWI599998B TW102126130A TW102126130A TWI599998B TW I599998 B TWI599998 B TW I599998B TW 102126130 A TW102126130 A TW 102126130A TW 102126130 A TW102126130 A TW 102126130A TW I599998 B TWI599998 B TW I599998B
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picture
display
data
frequency
signal
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TW201505007A (en
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江啓逞
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奇景光電股份有限公司
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Description

顯示裝置及其時序控制器的運作方法 Display device and its timing controller operation method

本發明是有關於一種顯示裝置及其運作方法,且特別是有關於一種顯示裝置及其時序控制器的其時序控制器的運作方法。 The present invention relates to a display device and a method of operating the same, and more particularly to a method of operating a timing controller of a display device and its timing controller.

顯示裝置一般會依照影音來源所提供的畫面來顯示對應的影像。但在顯示靜態影像的情況下,顯示裝置仍持續接收來自影音來源所傳送的畫面,並且顯示相同的影像。為了降低顯示裝置於顯示靜態影像時接收畫面的耗電量,顯示裝置中可配置儲存一整個畫面的畫面緩衝器。在顯示動態影像的情況下,顯示裝置可依照影音來源所提供的畫面來顯示對應的影像;在顯示靜態影像的情況下,顯示裝置可將靜態畫面儲存於畫面緩衝器中,而顯示裝置依據畫面緩衝器所儲存的靜態畫面來進行顯示。 The display device generally displays the corresponding image according to the screen provided by the video source. However, in the case of displaying a still image, the display device continues to receive the picture transmitted from the video source and displays the same image. In order to reduce the power consumption of the receiving screen when the display device displays the still image, a screen buffer for storing an entire screen can be configured in the display device. In the case of displaying a moving image, the display device can display the corresponding image according to the picture provided by the video source; in the case of displaying the still image, the display device can store the still picture in the picture buffer, and the display device according to the picture The static picture stored in the buffer is displayed.

然而,當顯示裝置中配置畫面緩衝器時,時序控制器會對應地配置存取畫面緩衝器的電路。根據上述,當具有畫面緩衝 器的顯示裝置運作時,電力消耗會相對地提高,因此如何降低具有畫面緩衝器的顯示裝置於運作時的電力消耗則成為此類型顯示裝置的一個設計重點。 However, when the picture buffer is configured in the display device, the timing controller configures the circuit for accessing the picture buffer accordingly. According to the above, when there is a picture buffer When the display device of the device operates, the power consumption is relatively increased. Therefore, how to reduce the power consumption of the display device having the picture buffer during operation becomes a design focus of this type of display device.

本發明提供一種顯示裝置及其時序控制器的其時序控制器的運作方法,可降低顯示裝置的電力消耗。 The invention provides a method for operating a timing controller of a display device and a timing controller thereof, which can reduce power consumption of the display device.

本發明的顯示裝置,包括畫面緩衝器、時序控制器、顯示面板及驅動電路。時序控制器耦接影音來源及畫面緩衝器,以接收來自影像來源的影音控制信號及影音資料信號,且輸出顯示資料。驅動電路耦接時序控制器及顯示面板,以依據顯示資料驅動顯示面板。時序控制器依據影音控制信號決定一操作模式,時序控制器依據操作模式輸出對應影音資料信號的顯示資料或對應儲存於畫面緩衝器的畫面的顯示資料,並且時序控制器依據操作模式調整畫面緩衝器的存取頻率。 The display device of the present invention includes a picture buffer, a timing controller, a display panel, and a driving circuit. The timing controller is coupled to the video source and the picture buffer to receive the video control signal and the video data signal from the image source, and output the display data. The driving circuit is coupled to the timing controller and the display panel to drive the display panel according to the display data. The timing controller determines an operation mode according to the audio and video control signal, and the timing controller outputs the display data corresponding to the audio and video data signal or the display data corresponding to the picture stored in the picture buffer according to the operation mode, and the timing controller adjusts the picture buffer according to the operation mode. Access frequency.

在本發明的一實施例中,當操作模式為標準模式時,時序控制器輸出對應影音資料信號的顯示資料,且設定畫面緩衝器的存取頻率為零。 In an embodiment of the invention, when the operation mode is the standard mode, the timing controller outputs display data corresponding to the audiovisual material signal, and sets the access frequency of the picture buffer to zero.

在本發明的一實施例中,顯示裝置更包括一電源供應單元,耦接時序控制器及畫面緩衝器,用以提供一系統電壓至畫面緩衝器及時序控制器中存取畫面緩衝器的部分電路。當操作模式為標準模式時,時序控制器控制電源供應單元停止提供系統電壓。 In an embodiment of the invention, the display device further includes a power supply unit coupled to the timing controller and the picture buffer for providing a system voltage to the picture buffer and the portion of the timing controller that accesses the picture buffer. Circuit. When the operation mode is the standard mode, the timing controller controls the power supply unit to stop providing the system voltage.

在本發明的一實施例中,當操作模式為快取模式時,時序控制器輸出對應影音資料信號的顯示資料,將影音資料信號所傳送的畫面儲存於畫面緩衝器,並且設定畫面緩衝器的存取頻率為對應影音資料信號的頻率。 In an embodiment of the invention, when the operation mode is the cache mode, the timing controller outputs the display data corresponding to the video data signal, stores the picture transmitted by the video data signal in the picture buffer, and sets the picture buffer. The access frequency is the frequency corresponding to the video data signal.

在本發明的一實施例中,當操作模式為自我更新模式時,時序控制器輸出對應儲存於畫面緩衝器的畫面的顯示資料,且設定畫面緩衝器的存取頻率為對應顯示資料的頻率。 In an embodiment of the invention, when the operation mode is the self-updating mode, the timing controller outputs display data corresponding to the screen stored in the picture buffer, and sets the access frequency of the picture buffer to the frequency corresponding to the display data.

在本發明的一實施例中,當操作模式為畫面更新模式時,時序控制器輸出對應儲存於畫面緩衝器的畫面的顯示資料,將影音資料信號所傳送的畫面儲存於畫面緩衝器,且設定畫面緩衝器的存取頻率為對應影音資料信號的頻率及顯示資料的頻率的總和。 In an embodiment of the present invention, when the operation mode is the screen update mode, the timing controller outputs display data corresponding to the screen stored in the screen buffer, and stores the screen transmitted by the video material signal in the screen buffer, and sets The access frequency of the picture buffer is the sum of the frequency corresponding to the video data signal and the frequency of the displayed data.

在本發明的一實施例中,當操作模式為重新同步模式時,時序控制器輸出對應儲存於畫面緩衝器的畫面的顯示資料,將影音資料信號所傳送的畫面儲存於畫面緩衝器,且設定畫面緩衝器的存取頻率為對應影音資料信號的頻率及顯示資料的頻率的總和。 In an embodiment of the present invention, when the operation mode is the resynchronization mode, the timing controller outputs display data corresponding to the screen stored in the picture buffer, and stores the picture transmitted by the video material signal in the picture buffer, and sets The access frequency of the picture buffer is the sum of the frequency corresponding to the video data signal and the frequency of the displayed data.

在本發明的一實施例中,時序控制器包括資料多工器、畫面控制器、畫面介面電路、畫面時脈產生器及狀態判斷單元。資料多工器,具有第一輸入端、第二輸入端及輸出端,第一輸入端耦接影音來源以接收影音資料信號,輸出端輸出顯示資料。畫面控制器具有第一資料暫存器及第二資料暫存器,第一資料暫存 器的輸入端耦接影音來源以接收影音資料信號,第二資料暫存器的輸出端耦接資料多工器的第二輸入端。畫面介面電路用以耦接畫面控制器的第一資料暫存器的輸出端與畫面緩衝器的輸入端,且耦接畫面控制器的第二資料暫存器的輸入端與畫面緩衝器的輸出端。畫面時脈產生器耦接畫面控制器及畫面介面電路,以提供第一時脈信號至畫面控制器及畫面介面電路,並且耦接畫面緩衝器以提供第二時脈信號至畫面緩衝器。狀態判斷單元耦接影音來源以接收影音控制信號,以依據影音控制信號判斷操作模式,耦接資料多工器以控制資料多工器的輸出端耦接第一輸入端或第二輸入端,耦接畫面時脈產生器以依據操作模式調整第一時脈信號及第二時脈信號的頻率,以及耦接畫面控制器以控制畫面控制器的運作。 In an embodiment of the invention, the timing controller includes a data multiplexer, a picture controller, a picture interface circuit, a picture clock generator, and a state determination unit. The data multiplexer has a first input end, a second input end and an output end. The first input end is coupled to the audio and video source to receive the audio and video data signal, and the output end outputs the display data. The picture controller has a first data register and a second data register, and the first data is temporarily stored. The input end of the device is coupled to the video source to receive the video data signal, and the output end of the second data register is coupled to the second input end of the data multiplexer. The screen interface circuit is configured to be coupled to the output end of the first data buffer of the picture controller and the input end of the picture buffer, and coupled to the input end of the second data buffer of the picture controller and the output of the picture buffer end. The picture clock generator is coupled to the picture controller and the picture interface circuit to provide the first clock signal to the picture controller and the picture interface circuit, and is coupled to the picture buffer to provide the second clock signal to the picture buffer. The state determining unit is coupled to the audio and video source to receive the video and audio control signal to determine the operating mode according to the video and audio control signal, and coupled to the data multiplexer to control the output end of the data multiplexer to be coupled to the first input end or the second input end, coupled The screen clock generator adjusts the frequency of the first clock signal and the second clock signal according to the operation mode, and couples the picture controller to control the operation of the picture controller.

在本發明的一實施例中,第一資料暫存器及第二資料暫存器分別為先進先出(FIFO)暫存器。 In an embodiment of the invention, the first data register and the second data register are respectively a first in first out (FIFO) register.

在本發明的一實施例中,當操作模式為標準模式時,狀態判斷單元控制資料多工器的輸出端耦接第一輸入端,控制畫面控制器為停止狀態,且調整第一時脈信號及第二時脈信號的頻率為零。 In an embodiment of the invention, when the operation mode is the standard mode, the state determining unit controls the output end of the data multiplexer to be coupled to the first input end, the control picture controller is in a stop state, and the first clock signal is adjusted. And the frequency of the second clock signal is zero.

在本發明的一實施例中,顯示裝置更包括一電源供應單元,耦接狀態判斷單元、畫面控制器、畫面介面電路及畫面緩衝器,用以提供系統電壓至畫面控制器、畫面介面電路及畫面緩衝器。當操作模式為標準模式時,狀態判斷單元控制電源供應單元 停止提供系統電壓。 In an embodiment of the invention, the display device further includes a power supply unit, a state determination unit, a picture controller, a picture interface circuit, and a picture buffer for providing system voltage to the picture controller and the picture interface circuit. Picture buffer. The state determination unit controls the power supply unit when the operation mode is the standard mode Stop providing system voltage.

在本發明的一實施例中,當操作模式為快取模式時,狀態判斷單元控制資料多工器的輸出端耦接第一輸入端,控制畫面控制器為運作狀態,且調整第一時脈信號及第二時脈信號的頻率為對應影音資料信號的頻率。 In an embodiment of the invention, when the operation mode is the cache mode, the state determining unit controls the output end of the data multiplexer to be coupled to the first input end, the control picture controller is in an operational state, and the first clock is adjusted. The frequency of the signal and the second clock signal is the frequency corresponding to the video data signal.

在本發明的一實施例中,當操作模式為自我更新模式時,狀態判斷單元控制資料多工器的輸出端耦接第二輸入端,控制畫面控制器為運作狀態,且調整第一時脈信號及第二時脈信號的頻率為對應顯示資料的頻率。 In an embodiment of the invention, when the operation mode is the self-updating mode, the state determining unit controls the output end of the data multiplexer to be coupled to the second input end, controls the picture controller to be in an operational state, and adjusts the first clock. The frequency of the signal and the second clock signal is the frequency corresponding to the displayed data.

在本發明的一實施例中,當操作模式為畫面更新模式時,狀態判斷單元控制資料多工器的輸出端耦接第二輸入端,控制畫面控制器為運作狀態,且調整第一時脈信號及第二時脈信號的頻率為對應影音資料信號的頻率及顯示資料的頻率的總和。 In an embodiment of the present invention, when the operation mode is the picture update mode, the state determining unit controls the output end of the data multiplexer to be coupled to the second input end, and the control picture controller is in an operational state, and adjusts the first clock. The frequency of the signal and the second clock signal is the sum of the frequency of the corresponding audiovisual data signal and the frequency of the displayed data.

在本發明的一實施例中,當操作模式為重新同步模式,狀態判斷單元控制資料多工器的輸出端耦接第二輸入端,控制畫面控制器為運作狀態,且調整第一時脈信號及第二時脈信號的頻率為對應影音資料信號的頻率及顯示資料的頻率的總和。 In an embodiment of the invention, when the operation mode is the resynchronization mode, the state determining unit controls the output end of the data multiplexer to be coupled to the second input end, the control picture controller is in an operational state, and the first clock signal is adjusted. And the frequency of the second clock signal is the sum of the frequency of the corresponding audio and video data signal and the frequency of the displayed data.

在本發明的一實施例中,當操作模式為重新同步模式且影音資料信號傳送第一顯示畫面時,第一資料暫存器受控於狀態判斷單元接收第一顯示畫面且提供所接收的第一顯示畫面。當操作模式為重新同步模式且影音資料信號傳送第二顯示畫面時,第一資料暫存器受控於狀態判斷單元停止接收第二顯示畫面且停止 提供顯示畫面。 In an embodiment of the invention, when the operation mode is the resynchronization mode and the video data signal transmits the first display screen, the first data register is controlled by the state determining unit to receive the first display screen and provide the received A display screen. When the operation mode is the resynchronization mode and the video data signal transmits the second display screen, the first data register is controlled by the state determination unit to stop receiving the second display screen and stops. Provide a display.

在本發明的一實施例中,當操作模式為重新同步模式且影音資料信號傳送第二顯示畫面時,畫面時脈產生器受控於狀態判斷單元停止提供第一時脈信號至第一資料暫存器。 In an embodiment of the invention, when the operation mode is the resynchronization mode and the video data signal is transmitted to the second display screen, the picture clock generator is controlled by the state determining unit to stop providing the first clock signal to the first data temporary. Save.

在本發明的一實施例中,畫面介面電路提供受控於狀態判斷單元提供相位設定信號。當畫面時脈產生器受控於狀態判斷單元調整第一時脈信號及第二時脈信號的頻率時,畫面時脈產生器停止提供第一時脈信號至畫面控制器,調整第一時脈信號及第二時脈信號的頻率至一目標頻率,並且依據相位設定信號同步化第一時脈信號及第二時脈信號,接著將同步化後的第一時脈信號提供至畫面控制器。 In an embodiment of the invention, the picture interface circuit provides control of the state determination unit to provide a phase setting signal. When the picture clock generator is controlled by the state determining unit to adjust the frequency of the first clock signal and the second clock signal, the picture clock generator stops providing the first clock signal to the picture controller, and adjusts the first clock. And synchronizing the first clock signal and the second clock signal according to the phase setting signal, and then providing the synchronized first clock signal to the picture controller.

在本發明的一實施例中,第二資料暫存器的容量大於等於畫面時脈產生器調整第一時脈信號及第二時脈信號的頻率且同步化第一時脈信號及第二時脈信號所需時間所對應的容量。 In an embodiment of the invention, the capacity of the second data buffer is greater than or equal to the frequency of the first clock signal and the second clock signal adjusted by the picture clock generator and the first clock signal is synchronized and the second time is synchronized. The capacity corresponding to the time required for the pulse signal.

在本發明的一實施例中,畫面時脈產生器包括時脈產生電路、相位調整單元及時脈開關單元。時脈產生電路耦接狀態判斷單元及畫面緩衝器,以受控於狀態判斷單元產生第二時脈信號。相位調整單元耦接畫面介面電路及時脈產生電路,以依據相位設定信號及第二時脈信號提供第一時脈信號。時脈開關單元耦接狀態判斷單元、畫面控制器及相位調整單元,以受控於狀態判斷單元將相位調整單元提供的第一時脈信號傳送至畫面控制器。 In an embodiment of the invention, the picture clock generator includes a clock generation circuit, a phase adjustment unit, and a pulse switch unit. The clock generation circuit is coupled to the state determination unit and the picture buffer to control the state determination unit to generate the second clock signal. The phase adjustment unit is coupled to the picture interface circuit and the pulse generation circuit to provide the first clock signal according to the phase setting signal and the second clock signal. The clock switch unit is coupled to the state determining unit, the picture controller and the phase adjusting unit to transmit the first clock signal provided by the phase adjusting unit to the picture controller by the state determining unit.

在本發明的一實施例中,時脈開關單元於第一時脈信號 為接地電壓時傳送或停止傳送第一時脈信號至畫面控制器。 In an embodiment of the invention, the clock switch unit is in the first clock signal When the ground voltage is applied, the first clock signal is transmitted or stopped to the picture controller.

本發明的顯示裝置的時序控制器的運作方法,包括下列步驟。時序控制器依據影音來源提供的影音控制信號決定操作模式。時序控制器依據操作模式輸出對應影音資料信號的顯示資料或對應儲存於畫面緩衝器的畫面的顯示資料。時序控制器依據操作模式調整顯示裝置的畫面緩衝器的存取頻率。 The method of operating the timing controller of the display device of the present invention includes the following steps. The timing controller determines the operation mode according to the video control signal provided by the video source. The timing controller outputs display data corresponding to the video data signal or display data corresponding to the screen stored in the picture buffer according to the operation mode. The timing controller adjusts the access frequency of the picture buffer of the display device according to the operation mode.

在本發明的一實施例中,時序控制器依據操作模式調整顯示裝置的畫面緩衝器的存取頻率的步驟包括:當操作模式為標準模式時,時序控制器輸出對應影音資料信號的顯示資料,且設定畫面緩衝器的存取頻率為零;當操作模式為快取模式時,時序控制器輸出對應影音資料信號的顯示資料,將影音資料信號所傳送的畫面儲存於畫面緩衝器,並且設定畫面緩衝器的存取頻率為對應影音資料信號的頻率;當操作模式為自我更新模式時,時序控制器輸出對應儲存於畫面緩衝器的畫面的顯示資料,且設定畫面緩衝器的存取頻率為對應顯示資料的頻率;當操作模式為畫面更新模式時,時序控制器輸出對應儲存於畫面緩衝器的畫面的顯示資料,將影音資料信號所傳送的畫面儲存於畫面緩衝器,且設定畫面緩衝器的存取頻率為對應影音資料信號的頻率及顯示資料的頻率的總和;當操作模式為重新同步模式時,時序控制器輸出對應儲存於畫面緩衝器的畫面的顯示資料,將影音資料信號所傳送的畫面儲存於畫面緩衝器,且設定畫面緩衝器的存取頻率為對應影音資料信號的頻率及顯示資料的頻率的總和。 In an embodiment of the invention, the step of the timing controller adjusting the access frequency of the picture buffer of the display device according to the operation mode comprises: when the operation mode is the standard mode, the timing controller outputs the display data corresponding to the video data signal, And setting the access frequency of the picture buffer is zero; when the operation mode is the cache mode, the timing controller outputs the display data corresponding to the video data signal, stores the picture transmitted by the video material signal in the picture buffer, and sets the picture. The access frequency of the buffer is the frequency corresponding to the video data signal; when the operation mode is the self-updating mode, the timing controller outputs the display data corresponding to the picture stored in the picture buffer, and sets the access frequency of the picture buffer to correspond. The frequency of the data is displayed; when the operation mode is the screen update mode, the timing controller outputs the display data corresponding to the screen stored in the picture buffer, stores the picture transmitted by the video material signal in the picture buffer, and sets the picture buffer. The access frequency is the frequency of the corresponding audio and video data signal and the display data. When the operation mode is the resynchronization mode, the timing controller outputs the display data corresponding to the screen stored in the picture buffer, stores the picture transmitted by the video material signal in the picture buffer, and sets the picture buffer storage. The frequency is the sum of the frequency of the corresponding audio and video data signal and the frequency of the displayed data.

在本發明的一實施例中,顯示裝置的時序控制器的運作方法,更包括:當操作模式為標準模式時,時序控制器控制一電源供應單元提供的一系統電壓停止提供至畫面緩衝器及時序控制器中存取畫面緩衝器的部分電路。 In an embodiment of the invention, the method for operating the timing controller of the display device further includes: when the operation mode is the standard mode, the timing controller controls a system voltage provided by a power supply unit to stop providing to the picture buffer in time. Part of the circuit that accesses the picture buffer in the sequence controller.

在本發明的一實施例中,顯示裝置的時序控制器的運作方法,更包括:當操作模式為重新同步模式且影音資料信號傳送一第一顯示畫面時,時序控制器將所接收的第一顯示畫面傳送至畫面緩衝器;當操作模式為重新同步模式且影音資料信號傳送一第二顯示畫面時,時序控制器停止接收第二顯示畫面且停止提供所接收顯示畫面至畫面緩衝器。 In an embodiment of the invention, the method for operating the timing controller of the display device further includes: when the operation mode is the resynchronization mode and the video data signal is transmitted to the first display screen, the timing controller will receive the first The display screen is transmitted to the picture buffer; when the operation mode is the resynchronization mode and the video material signal is transmitted to the second display picture, the timing controller stops receiving the second display picture and stops providing the received display picture to the picture buffer.

基於上述,本發明實施例的顯示裝置及其時序控制器的其時序控制器的運作方法,其時序控制器可依據操作模式調整顯示裝置的畫面緩衝器的存取頻率,藉此可在部分操作模式中降低畫面緩衝器的存取頻率,以降低顯示裝置的電力消耗。 Based on the above, the display device of the embodiment of the present invention and the operation method of the timing controller of the timing controller thereof, the timing controller can adjust the access frequency of the picture buffer of the display device according to the operation mode, thereby being partially operable The mode reduces the access frequency of the picture buffer to reduce the power consumption of the display device.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧影音來源 10‧‧‧Video source

100、200、300‧‧‧顯示裝置 100, 200, 300‧‧‧ display devices

110、210、310‧‧‧時序控制器 110, 210, 310‧‧‧ timing controller

120、220‧‧‧畫面緩衝器 120, 220‧‧‧ picture buffer

130‧‧‧驅動電路 130‧‧‧Drive circuit

140‧‧‧顯示面板 140‧‧‧ display panel

150‧‧‧電源供應單元 150‧‧‧Power supply unit

211‧‧‧資料多工器 211‧‧‧Data multiplexer

213‧‧‧畫面控制器 213‧‧‧ Picture Controller

215‧‧‧畫面介面電路 215‧‧‧ Picture interface circuit

217、311‧‧‧畫面時脈產生器 217, 311‧‧‧ Picture Clock Generator

219‧‧‧狀態判斷單元 219‧‧‧State Judgment Unit

220a、231a、233a‧‧‧輸入端 220a, 231a, 233a‧‧‧ inputs

220b、231b、233b、O‧‧‧輸出端 220b, 231b, 233b, O‧‧‧ output

231‧‧‧第一資料暫存器 231‧‧‧First data register

233‧‧‧第二資料暫存器 233‧‧‧Second data register

313‧‧‧時脈產生電路 313‧‧‧ Clock generation circuit

315‧‧‧相位調整單元 315‧‧‧ phase adjustment unit

317‧‧‧時脈開關單元 317‧‧‧clock switch unit

A‧‧‧第一輸入端 A‧‧‧ first input

AVC‧‧‧影音控制信號 AVC‧‧‧Video Control Signal

AVD‧‧‧影音資料信號 AVD‧‧‧ audio and video data signal

B‧‧‧第二輸入端 B‧‧‧second input

CLK1‧‧‧第一時脈信號 CLK1‧‧‧ first clock signal

CLK2‧‧‧第二時脈信號 CLK2‧‧‧ second clock signal

CMD1‧‧‧進入指令 CMD1‧‧‧Entering instructions

CMD2‧‧‧畫面更新指令 CMD2‧‧‧ screen update instruction

CMD3‧‧‧跳出指令 CMD3‧‧‧ jumping out command

DD‧‧‧輸出顯示資料 DD‧‧‧ Output display data

FD10~FD13、FD20~FD27、FD31~FD33、FD41~FD44‧‧‧顯示畫面 FD10~FD13, FD20~FD27, FD31~FD33, FD41~FD44‧‧‧ display screen

SPS‧‧‧相位設定信號 SPS‧‧‧ phase setting signal

ST‧‧‧狀態信號 ST‧‧‧ status signal

VDDA‧‧‧系統電壓 VDDA‧‧‧ system voltage

S510、S520、S530、S610、S620、S630‧‧‧步驟 S510, S520, S530, S610, S620, S630‧‧ steps

圖1A為依據本發明一實施例的顯示裝置的系統示意圖。 FIG. 1A is a schematic diagram of a system of a display device according to an embodiment of the invention.

圖1B為依據本發明一實施例的影音資料信號與顯示資料的時序示意圖。 FIG. 1B is a timing diagram of video and audio data signals and display materials according to an embodiment of the invention.

圖1C為依據本發明一實施例的顯示裝置的操作模式的狀態示意圖。 FIG. 1C is a schematic diagram showing a state of an operation mode of a display device according to an embodiment of the invention.

圖2為依據本發明另一實施例的顯示裝置的系統示意圖。 2 is a schematic diagram of a system of a display device in accordance with another embodiment of the present invention.

圖3為依據本發明再一實施例的顯示裝置的系統示意圖。 FIG. 3 is a schematic diagram of a system of a display device according to still another embodiment of the present invention.

圖4為依據本發明另一實施例的影音資料信號與顯示資料的時序示意圖。 4 is a timing diagram of video and audio data signals and display materials according to another embodiment of the present invention.

圖5為依據本發明一實施例的顯示裝置的時序控制器的運作方法的流程圖。 FIG. 5 is a flow chart showing a method of operating a timing controller of a display device according to an embodiment of the invention.

圖6為依據本發明另一實施例的顯示裝置的時序控制器的運作方法的流程圖。 6 is a flow chart showing a method of operating a timing controller of a display device in accordance with another embodiment of the present invention.

圖1A為依據本發明一實施例的顯示裝置的系統示意圖。請參照圖1A,在本實施例中,顯示裝置100包括時序控制器110、畫面緩衝器120、驅動電路130、顯示面板140及電源供應單元150。時序控制器110耦接影音來源10及畫面緩衝器120,以接收來自影像來源10的影音控制信號AVC及影音資料信號AVD,且輸出顯示資料DD,其中影音來源110可以是影音播放器或電腦。 FIG. 1A is a schematic diagram of a system of a display device according to an embodiment of the invention. Referring to FIG. 1A , in the embodiment, the display device 100 includes a timing controller 110 , a screen buffer 120 , a driving circuit 130 , a display panel 140 , and a power supply unit 150 . The timing controller 110 is coupled to the video source 10 and the picture buffer 120 to receive the video control signal AVC and the video data signal AVD from the image source 10, and outputs the display data DD, wherein the video source 110 can be a video player or a computer.

驅動電路130耦接時序控制器110及顯示面板140,以依據顯示資料DD驅動顯示面板127。電源供應單元150耦接時序控制器110及畫面緩衝器120,用以提供系統電壓VDDA至時序控 制器110及畫面緩衝器120。其中,電源供應單元150可受控於時序控制器110而提供系統電壓VDDA。 The driving circuit 130 is coupled to the timing controller 110 and the display panel 140 to drive the display panel 127 according to the display data DD. The power supply unit 150 is coupled to the timing controller 110 and the picture buffer 120 for providing system voltage VDDA to timing control. Controller 110 and picture buffer 120. Wherein, the power supply unit 150 can be controlled by the timing controller 110 to provide the system voltage VDDA.

在本實施例中,時序控制器110會依據影音控制信號AVC決定顯示裝置100的操作模式,例如標準模式、快取模式、自我更新模式、畫面更新模式、重新同步模式。並且,在不同的操作模式下,時序控制器110產生顯示資料DD的方式可能會不同,並且時序控制器110與畫面緩衝器120的傳輸模式也可能會不同,亦即畫面緩衝器120的使用程度會不同。當畫面緩衝器120的使用程度較低時,時序控制器110可降低存取畫面緩衝器120的工作頻率(即存取頻率)而不影響資料的傳送,並且可降低時序控制器110整體的電力消耗。換言之,時序控制器110會依據操作模式輸出對應影音資料信號AVD的顯示資料DD或對應儲存於畫面緩衝器120的畫面的顯示資料DD,並且時序控制器110依據操作模式調整畫面緩衝器110的存取頻率。 In the present embodiment, the timing controller 110 determines an operation mode of the display device 100 according to the video control signal AVC, such as a standard mode, a cache mode, a self-updating mode, a picture update mode, and a resynchronization mode. Moreover, in different operation modes, the manner in which the timing controller 110 generates the display material DD may be different, and the transmission mode of the timing controller 110 and the picture buffer 120 may also be different, that is, the degree of use of the picture buffer 120. It will be different. When the degree of use of the picture buffer 120 is low, the timing controller 110 can reduce the operating frequency (ie, access frequency) of the access picture buffer 120 without affecting the transfer of data, and can reduce the power of the timing controller 110 as a whole. Consumption. In other words, the timing controller 110 outputs the display material DD corresponding to the video material data signal AVD or the display material DD corresponding to the picture stored in the picture buffer 120 according to the operation mode, and the timing controller 110 adjusts the memory of the picture buffer 110 according to the operation mode. Take the frequency.

此外,在某些操作模式中,畫面緩衝器120可能處於閒置的狀態,因此時序控制器110可控制電源供應單元150停止提供系統電壓VDDA至畫面緩衝器120及時序控制器110中存取畫面緩衝器120的部分電路,以進一步降低顯示裝置100整體的電力消耗。 In addition, in some modes of operation, the picture buffer 120 may be in an idle state, so the timing controller 110 may control the power supply unit 150 to stop providing the system voltage VDDA to the picture buffer 120 and access the picture buffer in the timing controller 110. Part of the circuit of the device 120 to further reduce the power consumption of the display device 100 as a whole.

圖1B為依據本發明一實施例的影音資料信號與顯示資料的時序示意圖。圖1C為依據本發明一實施例的顯示裝置的操作模式的狀態示意圖。請參照圖1A至圖1C,在影音控制信號AVC 傳送進入指令CMD1前,亦即時序控制器110接收到進入指令CMD1前,顯示裝置100的操作模式會設定為標準模式,並且影音來源10會透過影音資料信號AVD不斷傳送顯示畫面(如FD10)至時序控制器110。當顯示裝置100的操作模式為標準模式時,時序控制器110會輸出對應影音資料信號AVD的顯示資料DD,亦即顯示資料DD會對應影音資料信號AVD的顯示畫面(如FD10)而形成顯示畫面(如FD20)。由於時序控制器110利用對應影音資料信號AVD產生顯示資料DD,因此畫面緩衝器120並未被使用,此時時序控制器110可關閉畫面緩衝器120,亦即可設定畫面緩衝器120的存取頻率為零,甚至可控制電源供應單元120停止提供系統電壓VDDA至畫面緩衝器120及時序控制器110中存取畫面緩衝器120的部分電路。 FIG. 1B is a timing diagram of video and audio data signals and display materials according to an embodiment of the invention. FIG. 1C is a schematic diagram showing a state of an operation mode of a display device according to an embodiment of the invention. Please refer to FIG. 1A to FIG. 1C, in the video and audio control signal AVC Before the transmission enter command CMD1, that is, before the timing controller 110 receives the entry command CMD1, the operation mode of the display device 100 is set to the standard mode, and the video source 10 continuously transmits the display screen (such as FD10) through the video data signal AVD to Timing controller 110. When the operation mode of the display device 100 is the standard mode, the timing controller 110 outputs the display data DD corresponding to the audio-visual data signal AVD, that is, the display data DD forms a display screen corresponding to the display image of the audio-visual data signal AVD (such as FD10). (such as FD20). Since the timing controller 110 generates the display material DD by using the corresponding video material signal AVD, the picture buffer 120 is not used. At this time, the timing controller 110 can turn off the picture buffer 120, and can also set the access of the picture buffer 120. The frequency is zero, and even the control power supply unit 120 can stop supplying the system voltage VDDA to the picture buffer 120 and a part of the circuit of the timing controller 110 that accesses the picture buffer 120.

在影音控制信號AVC傳送進入指令CMD1時,亦即時序控制器110接收到進入指令CMD1,顯示裝置100的操作模式會先進入快取模式,並且影音來源10會透過影音資料信號AVD傳送一個顯示畫面(如FD11)至時序控制器110,其中快取模式大致維持一個畫面期間。當操作模式為快取模式時,時序控制器110仍會輸出對應影音資料信號AVD的顯示資料DD,亦即顯示資料DD會對應影音資料信號AVD的顯示畫面(如FD11)而形成顯示畫面(如FD21)。 When the video control signal AVC transmits the incoming command CMD1, that is, the timing controller 110 receives the incoming command CMD1, the operating mode of the display device 100 first enters the cache mode, and the video source 10 transmits a display through the video data signal AVD. (e.g., FD11) to the timing controller 110, wherein the cache mode is maintained for substantially one picture period. When the operation mode is the cache mode, the timing controller 110 still outputs the display data DD corresponding to the video data signal AVD, that is, the display data DD forms a display screen corresponding to the display screen of the video data signal AVD (such as FD11) (eg, FD21).

此時,時序控制器110會將影音資料信號AVD所傳送的顯示畫面(如FD11)儲存於畫面緩衝器120,亦即畫面緩衝器120 為處於寫入狀態,因此時序控制器110可設定畫面緩衝器120的存取頻率為對應影音資料信號AVD的頻率。換言之,假設影音資料信號AVD的頻率為150MHz,影音資料信號AVD的位元率為24BPS,而畫面緩衝器120的資料寬度為32bit,則畫面緩衝器120的存取頻率可設定為112.5MHz(即150M×24/32)。 At this time, the timing controller 110 stores the display screen (such as FD11) transmitted by the video material data signal AVD in the picture buffer 120, that is, the picture buffer 120. In the write state, the timing controller 110 can set the access frequency of the picture buffer 120 to the frequency of the corresponding video material signal AVD. In other words, assuming that the frequency of the video material signal AVD is 150 MHz, the bit rate of the video material signal AVD is 24 BPS, and the data width of the picture buffer 120 is 32 bits, the access frequency of the picture buffer 120 can be set to 112.5 MHz (ie, 150M×24/32).

在快取模式結束後,顯示裝置100的操作模式會進入自我更新模式。當操作模式為自我更新模式時,時序控制器110會輸出對應儲存於畫面緩衝器120的顯示畫面的顯示資料DD,亦即時序控制器110會存取儲存於畫面緩衝器120的顯示畫面而形成顯示畫面(如FD22、FD23)。 After the cache mode ends, the operation mode of the display device 100 enters the self-updating mode. When the operation mode is the self-updating mode, the timing controller 110 outputs the display data DD corresponding to the display screen stored in the screen buffer 120, that is, the timing controller 110 accesses the display screen stored in the screen buffer 120 to form a display screen. Display screen (such as FD22, FD23).

此時,畫面緩衝器120為處於讀取狀態,因此時序控制器110可設定畫面緩衝器120的存取頻率為對應顯示資料DD的頻率。換言之,假設影音資料信號AVD的頻率為150MHz,影音資料信號AVD的畫面更新率(Frame rate)為60Hz,顯示面板140的更新率(Refresh rate)為40Hz,則顯示資料DD可設定為100MHz(即150M×40/60)。並且,假設顯示資料DD的位元率為24BPS,而畫面緩衝器120的資料寬度為32bit,則畫面緩衝器120的存取頻率可設定為75MHz(即100M×24/32)。 At this time, since the picture buffer 120 is in the read state, the timing controller 110 can set the access frequency of the picture buffer 120 to be the frequency corresponding to the display material DD. In other words, assuming that the frequency of the video material signal AVD is 150 MHz, the frame rate of the video material signal AVD is 60 Hz, and the refresh rate of the display panel 140 is 40 Hz, the display data DD can be set to 100 MHz (ie, 150M×40/60). Further, assuming that the bit rate of the display material DD is 24 BPS and the data width of the picture buffer 120 is 32 bits, the access frequency of the picture buffer 120 can be set to 75 MHz (i.e., 100 M × 24/32).

在影音控制信號AVC傳送畫面更新指令CMD2時,亦即時序控制器110接收到畫面更新指令CMD2,顯示裝置100的操作模式會進入畫面更新模式,並且影音來源10會透過影音資料信號AVD傳送一個顯示畫面(如FD12)至時序控制器110,其中畫 面更新模式大致維持一個畫面期間,並且在畫面更新模式結束後會再回到自我更新模式。當操作模式為畫面更新模式時,時序控制器110同樣會輸出對應儲存於畫面緩衝器120的畫面的顯示資料DD,亦即時序控制器110同樣會存取儲存於畫面緩衝器120的顯示畫面而形成顯示畫面(如FD24~FD26),並且時序控制器110會將影音資料信號AVD所傳送的顯示畫面(如FD12)儲存於畫面緩衝器120。 When the video control signal AVC transmits the picture update command CMD2, that is, the timing controller 110 receives the picture update command CMD2, the operation mode of the display device 100 enters the picture update mode, and the video source 10 transmits a display through the video material signal AVD. a picture (such as FD12) to the timing controller 110, wherein the picture The face update mode generally maintains one screen period and returns to the self-updating mode after the screen update mode ends. When the operation mode is the screen update mode, the timing controller 110 also outputs the display data DD corresponding to the screen stored in the screen buffer 120, that is, the timing controller 110 also accesses the display screen stored in the screen buffer 120. A display screen (such as FD24~FD26) is formed, and the timing controller 110 stores the display screen (such as FD12) transmitted by the video material signal AVD in the picture buffer 120.

此時,畫面緩衝器120為處於讀寫狀態,因此時序控制器110可設定畫面緩衝器120的存取頻率為對應影音資料信號AVD的頻率及顯示資料DD的頻率的總和。換言之,假設影音資料信號AVD的頻率為150MHz,影音資料信號AVD的畫面更新率為60Hz,顯示面板140的更新率為40Hz,則顯示資料DD可設定為100MHz(即150M×40/60)。並且,假設影音資料信號AVD及顯示資料DD的位元率皆為24BPS,而畫面緩衝器120的資料寬度為32bit,則畫面緩衝器120的存取頻率可設定為187.5MHz(即150M×24/32+100M×24/32)。 At this time, since the picture buffer 120 is in the read/write state, the timing controller 110 can set the access frequency of the picture buffer 120 to be the sum of the frequency of the corresponding video material signal AVD and the frequency of the display material DD. In other words, assuming that the frequency of the video material signal AVD is 150 MHz, the picture update rate of the video material signal AVD is 60 Hz, and the update rate of the display panel 140 is 40 Hz, the display material DD can be set to 100 MHz (ie, 150 M×40/60). Moreover, assuming that the bit rate of the video material signal AVD and the display material DD are both 24 BPS, and the data width of the picture buffer 120 is 32 bits, the access frequency of the picture buffer 120 can be set to 187.5 MHz (ie, 150 M×24/ 32+100M×24/32).

在影音控制信號AVC傳送跳出指令CMD3時,亦即時序控制器110接收到跳出指令CMD3,顯示裝置100的操作模式會先進入重新同步模式,並且影音來源10會透過影音資料信號AVD不斷傳送顯示畫面(如FD13)至時序控制器110,在重新同步模式結束後會回到標準模式。當操作模式為重新同步模式時,時序控制器110會輸出對應儲存於畫面緩衝器120的顯示畫面的顯示 資料DD,亦即時序控制器110同樣會存取儲存於畫面緩衝器120的顯示畫面而形成顯示畫面(如FD27)。將影音資料信號所傳送的顯示畫面(如FD13)儲存於畫面緩衝器120中。此時,畫面緩衝器120為處於讀寫狀態,因此時序控制器110可設定畫面緩衝器120的存取頻率為對應影音資料信號AVD的頻率及顯示資料DD的頻率的總和。 When the video control signal AVC transmits the bounce command CMD3, that is, the timing controller 110 receives the bounce command CMD3, the operation mode of the display device 100 first enters the resynchronization mode, and the video source 10 continuously transmits the display screen through the video data signal AVD. (e.g., FD13) to the timing controller 110, returning to the standard mode after the resynchronization mode ends. When the operation mode is the resynchronization mode, the timing controller 110 outputs a display corresponding to the display screen stored in the screen buffer 120. The data DD, that is, the timing controller 110 also accesses the display screen stored in the picture buffer 120 to form a display screen (such as FD 27). The display screen (such as FD 13) transmitted by the video material signal is stored in the picture buffer 120. At this time, since the picture buffer 120 is in the read/write state, the timing controller 110 can set the access frequency of the picture buffer 120 to be the sum of the frequency of the corresponding video material signal AVD and the frequency of the display material DD.

圖2為依據本發明另一實施例的顯示裝置的系統示意圖。請參照圖1A及圖2,在本實施例中,顯示裝置200大致相同於顯示裝置100,其不同之處在於時序控制器210及畫面緩衝器220,其中相同或相似元件使用相同或相似標號。時序控制器210包括資料多工器211、畫面控制器213、畫面介面電路215、畫面時脈產生器217及狀態判斷單元219。電源供應單元150繪示為耦接畫面緩衝器220、畫面控制器213及畫面介面電路215,以提供系統電壓VDDA畫面緩衝器220、畫面控制器213及畫面介面電路215,但本發明其他實施例的電源供應單元150亦可提供系統電壓VDDA至其他電路(如資料多工器211、畫面時脈產生器217及狀態判斷單元219),本發明實施例不以此為限。 2 is a schematic diagram of a system of a display device in accordance with another embodiment of the present invention. Referring to FIG. 1A and FIG. 2, in the present embodiment, the display device 200 is substantially the same as the display device 100, except that the timing controller 210 and the picture buffer 220 are the same or similar elements. The timing controller 210 includes a data multiplexer 211, a picture controller 213, a picture interface circuit 215, a picture clock generator 217, and a state determination unit 219. The power supply unit 150 is shown as being coupled to the picture buffer 220, the picture controller 213, and the picture interface circuit 215 to provide the system voltage VDDA picture buffer 220, the picture controller 213, and the picture interface circuit 215, but other embodiments of the present invention The power supply unit 150 can also provide the system voltage VDDA to other circuits (such as the data multiplexer 211, the picture clock generator 217, and the state determining unit 219), which is not limited thereto.

資料多工器211具有第一輸入端A、第二輸入端B及輸出端O,資料多工器211的第一輸入端A耦接影音來源10以接收影音資料信號AVD,資料多工器211的第二輸入端B耦接畫面控制器213,資料多工器211的輸出端O輸出顯示資料DD。畫面控制器213具有第一資料暫存器231及第二資料暫存器233,其中第 一資料暫存器231及第二資料暫存器233可以分別為先進先出(FIFO)暫存器。第一資料暫存器231的輸入端231a耦接影音來源10以接收影音資料信號AVD,第一資料暫存器231的輸出端231b耦接畫面介面電路215。第二資料暫存器233的輸入端233a耦接畫面介面電路215,第二資料暫存器233的輸出端233b耦接資料多工器211的第二輸入端B。 The data multiplexer 211 has a first input terminal A, a second input terminal B, and an output terminal O. The first input terminal A of the data multiplexer 211 is coupled to the video source 10 to receive the video data signal AVD, and the data multiplexer 211. The second input terminal B is coupled to the picture controller 213, and the output terminal O of the data multiplexer 211 outputs the display data DD. The picture controller 213 has a first data register 231 and a second data register 233, wherein A data register 231 and a second data register 233 can be first in first out (FIFO) registers, respectively. The input end 231a of the first data register 231 is coupled to the video source 10 to receive the video data signal AVD, and the output end 231b of the first data register 231 is coupled to the picture interface circuit 215. The input end 233a of the second data register 233 is coupled to the picture interface circuit 215, and the output end 233b of the second data register 233 is coupled to the second input end B of the data multiplexer 211.

畫面介面電路215用以耦接畫面控制器213的第一資料暫存器231的輸出端231b與畫面緩衝器220的輸入端220a,且耦接畫面控制器213的第二資料暫存器233的輸入端233a與畫面緩衝器220的輸出端220b。畫面時脈產生器217耦接畫面控制器213及畫面介面電路215,以提供第一時脈信號CLK1至畫面控制器213及畫面介面電路215,並且耦接畫面緩衝器220以提供第二時脈信號CLK2至畫面緩衝器220。狀態判斷單元219耦接影音來源10以接收影音控制信號AVC,以依據影音控制信號AVC判斷顯示裝置200的操作模式。狀態判斷單元219耦接資料多工器211,以控制資料多工器211的輸出端O耦接第一輸入端A或第二輸入端B。狀態判斷單元219耦接畫面時脈產生器217以依據顯示裝置200的操作模式調整第一時脈信號CLK1的頻率。以及,狀態判斷單元219耦接畫面控制器213以透過狀態信號ST控制畫面控制器213的運作。 The interface interface circuit 215 is configured to be coupled to the output end 231b of the first data register 231 of the picture controller 213 and the input end 220a of the picture buffer 220, and coupled to the second data register 233 of the picture controller 213. The input terminal 233a and the output terminal 220b of the picture buffer 220. The picture clock generator 217 is coupled to the picture controller 213 and the picture interface circuit 215 to provide the first clock signal CLK1 to the picture controller 213 and the picture interface circuit 215, and is coupled to the picture buffer 220 to provide the second clock. Signal CLK2 to picture buffer 220. The state judging unit 219 is coupled to the video source 10 to receive the video and audio control signal AVC to determine the operation mode of the display device 200 according to the video control signal AVC. The state determining unit 219 is coupled to the data multiplexer 211 to control the output terminal O of the data multiplexer 211 to be coupled to the first input terminal A or the second input terminal B. The state determining unit 219 is coupled to the screen clock generator 217 to adjust the frequency of the first clock signal CLK1 according to the operation mode of the display device 200. And, the state determining unit 219 is coupled to the picture controller 213 to control the operation of the picture controller 213 through the status signal ST.

依據上述,畫面控制器213會依據狀態信號ST而運作,並且依據第一時脈信號CLK1傳送資料至畫面介面電路215或自 畫面介面電路215接收資料;畫面介面電路215依據第一時脈信號CLK1傳送來自畫面控制器213的資料至畫面緩衝器或將來自畫面緩衝器220的資料傳送至畫面控制器213;畫面緩衝器220會依據第二時脈信號CLK2接收來自畫面介面電路215的資料或傳送資料至畫面介面電路215。 According to the above, the picture controller 213 operates according to the status signal ST, and transmits data to the picture interface circuit 215 or from the first clock signal CLK1. The screen interface circuit 215 receives the data; the screen interface circuit 215 transmits the data from the picture controller 213 to the picture buffer according to the first clock signal CLK1 or transfers the data from the picture buffer 220 to the picture controller 213; the picture buffer 220 The data from the picture interface circuit 215 or the transmission data is received to the picture interface circuit 215 according to the second clock signal CLK2.

假設在第一時脈信號CLK1與第二時脈信號CLK2同步的情況下,畫面介面電路215可順利存取畫面緩衝器220的資料,因此畫面介面電路215可透過存取畫面緩衝器220的資料判斷第一時脈信號CLK1與第二時脈信號CLK2是否同步。並且,畫面介面電路215可透過畫面緩衝器220的資料時序與第一時脈信號CLK計算一時間差(或相位差),畫面介面電路215再依據所計算的時間差(或相位差)提供相位設定信號SPS至畫面時脈產生器217,以使畫面時脈產生器217依據相位設定信號SPS調整第一時脈信號CLK1及/或第二時脈信號CLK2而使第一時脈信號CLK1與第二時脈信號CLK2同步化。其中,畫面緩衝器220可配置一特定區域用以進行存取測試,以避免顯示畫面被更改,並且上述調整第一時脈信號CLK1及/或第二時脈信號CLK2的動作可持續執行或於第一時脈信號CLK1與第二時脈信號CLK2未同步的情況下執行。 Assuming that the first clock signal CLK1 is synchronized with the second clock signal CLK2, the picture interface circuit 215 can smoothly access the data of the picture buffer 220, so the picture interface circuit 215 can access the data of the picture buffer 220. It is determined whether the first clock signal CLK1 is synchronized with the second clock signal CLK2. Moreover, the screen interface circuit 215 can calculate a time difference (or phase difference) from the first clock signal CLK through the data timing of the picture buffer 220, and the picture interface circuit 215 provides a phase setting signal according to the calculated time difference (or phase difference). SPS to the picture clock generator 217, so that the picture clock generator 217 adjusts the first clock signal CLK1 and/or the second clock signal CLK2 according to the phase setting signal SPS to make the first clock signal CLK1 and the second time The pulse signal CLK2 is synchronized. The picture buffer 220 can be configured with a specific area for performing an access test to prevent the display picture from being changed, and the action of adjusting the first clock signal CLK1 and/or the second clock signal CLK2 can be performed continuously or The first clock signal CLK1 is executed without being synchronized with the second clock signal CLK2.

請參照圖1B及圖2,在影音控制信號AVC傳送進入指令CMD1前,顯示裝置200的操作模式會設定為標準模式。當顯示裝置200的操作模式為標準模式時,狀態判斷單元219控制資料 多工器211的輸出端O耦接第一輸入端A,亦即輸出影音資料信號AVD作為顯示資料DD,並且狀態判斷單元219控制畫面控制器213為停止狀態(亦即使畫面控制器213停止運作),同時狀態判斷單元219調整第一時脈信號CLK1及第二時脈信號CLK2的頻率為零。此外,狀態判斷單元219可控制電源供應單元120停止提供系統電壓VDDA至畫面控制器213、畫面介面電路215及畫面緩衝器220。 Referring to FIG. 1B and FIG. 2, before the video control signal AVC transmits the entry command CMD1, the operation mode of the display device 200 is set to the standard mode. When the operation mode of the display device 200 is the standard mode, the state determination unit 219 controls the data. The output end O of the multiplexer 211 is coupled to the first input terminal A, that is, the video data signal AVD is output as the display data DD, and the state determining unit 219 controls the picture controller 213 to be in a stopped state (even if the picture controller 213 stops operating). The simultaneous state determination unit 219 adjusts the frequency of the first clock signal CLK1 and the second clock signal CLK2 to be zero. Further, the state judging unit 219 can control the power supply unit 120 to stop supplying the system voltage VDDA to the picture controller 213, the picture interface circuit 215, and the picture buffer 220.

在影音控制信號AVC傳送進入指令CMD1時,顯示裝置200的操作模式會先進入快取模式。當操作模式為快取模式時,狀態判斷單元219仍會控制資料多工器211的輸出端O耦接第一輸入端A;狀態判斷單元219控制畫面控制器213為運作狀態,以使影音資料信號AVD的顯示畫面(如FD11)會透過畫面控制器213及畫面介面電路215傳送至畫面緩衝器220而儲存於畫面緩衝器220;以及,狀態判斷單元219可控制畫面時脈產生器217以調整第一時脈信號CLK1及第二時脈信號CLK2的頻率為對應影音資料信號AVD的頻率。 When the video control signal AVC transmits the incoming command CMD1, the operation mode of the display device 200 first enters the cache mode. When the operation mode is the cache mode, the state determining unit 219 still controls the output terminal O of the data multiplexer 211 to be coupled to the first input terminal A; the state determining unit 219 controls the screen controller 213 to be in an operational state, so that the video data is The display screen of the signal AVD (such as FD11) is transmitted to the picture buffer 220 through the picture controller 213 and the picture interface circuit 215 and stored in the picture buffer 220; and the state determining unit 219 can control the picture clock generator 217 to adjust The frequencies of the first clock signal CLK1 and the second clock signal CLK2 are frequencies corresponding to the video data signal AVD.

在快取模式結束後,顯示裝置200的操作模式會進入自我更新模式。當操作模式為自我更新模式時,狀態判斷單元219控制資料多工器211的輸出端O耦接第二輸入端B,並且狀態判斷單元219會控制畫面控制器213為運作狀態,以使畫面緩衝器220所儲存的顯示畫面可透過畫面控制器213及畫面介面電路215傳送至資料多工器211的第二輸入端B。此時,狀態判斷單元219 可控制畫面時脈產生器217以調整第一時脈信號CLK1及第二時脈信號CLK2的頻率為對應顯示資料DD的頻率。 After the cache mode ends, the operation mode of the display device 200 enters the self-updating mode. When the operation mode is the self-updating mode, the state determining unit 219 controls the output terminal O of the data multiplexer 211 to be coupled to the second input terminal B, and the state determining unit 219 controls the picture controller 213 to be in an operational state to enable picture buffering. The display screen stored in the device 220 can be transmitted to the second input terminal B of the data multiplexer 211 through the picture controller 213 and the screen interface circuit 215. At this time, the state judging unit 219 The controllable picture clock generator 217 adjusts the frequency of the first clock signal CLK1 and the second clock signal CLK2 to the frequency corresponding to the display data DD.

在影音控制信號AVC傳送畫面更新指令CMD2時,顯示裝置200的操作模式會進入畫面更新模式,並且在畫面更新模式結束後會再回到自我更新模式。當操作模式為畫面更新模式時,狀態判斷單元219仍控制資料多工器211的輸出端O耦接第二輸入端B,並且狀態判斷單元219會控制畫面控制器213為運作狀態。此時,狀態判斷單元219可控制畫面時脈產生器217以調整第一時脈信號CLK1及第二時脈信號CLK2的頻率為對應影音資料信號AVD的頻率及顯示資料DD的頻率的總和。 When the video control signal AVC transmits the picture update command CMD2, the operation mode of the display device 200 enters the picture update mode, and returns to the self-updating mode after the picture update mode ends. When the operation mode is the picture update mode, the state determination unit 219 still controls the output terminal O of the data multiplexer 211 to be coupled to the second input terminal B, and the state determination unit 219 controls the picture controller 213 to be in an operational state. At this time, the state determining unit 219 can control the picture clock generator 217 to adjust the frequency of the first clock signal CLK1 and the second clock signal CLK2 as the sum of the frequency of the corresponding video material signal AVD and the frequency of the display material DD.

在影音控制信號AVC傳送跳出指令CMD3時,顯示裝置200的操作模式會先進入重新同步模式,在重新同步模式結束後會回到標準模式。當操作模式為重新同步模式,狀態判斷單元219仍控制資料多工器211的輸出端O耦接第二輸入端B,並且狀態判斷單元219會控制畫面控制器213為運作狀態。此時,狀態判斷單元219可控制畫面時脈產生器217以調整第一時脈信號CLK1及第二時脈信號CLK2的頻率為對應影音資料信號AVD的頻率及顯示資料DD的頻率的總和。 When the video control signal AVC transmits the jump command CMD3, the operation mode of the display device 200 first enters the resynchronization mode, and returns to the standard mode after the resynchronization mode ends. When the operation mode is the resynchronization mode, the state determination unit 219 still controls the output terminal O of the data multiplexer 211 to be coupled to the second input terminal B, and the state determination unit 219 controls the picture controller 213 to be in an operational state. At this time, the state determining unit 219 can control the picture clock generator 217 to adjust the frequency of the first clock signal CLK1 and the second clock signal CLK2 as the sum of the frequency of the corresponding video material signal AVD and the frequency of the display material DD.

在本發明的一實施例中,當畫面時脈產生器217受控於狀態判斷單元219而調整第一時脈信號CLK1及第二時脈信號CLK2的頻率時,畫面時脈產生器214會停止提供第一時脈信號CLK1至畫面控制器213,以致於畫面控制器213的第一資料暫存 器231不會再傳送資料,並且畫面控制器213的第二資料暫存器233不會再接收資料。此時,畫面時脈產生器217受控於狀態判斷單元219調整第一時脈信號CLK1及第二時脈信號CLK2的頻率至目標頻率,其中目標頻率可參照上述實施例,在此則不再贅述。並且,畫面時脈產生器217再依據相位設定信號SPS同步化第一時脈信號CLK1及第二時脈信號CLK2。在第一時脈信號CLK1及第二時脈信號CLK2同步化後,則畫面時脈產生器217將同步化後的第一時脈信號CLK1提供至畫面控制器213。 In an embodiment of the invention, when the picture clock generator 217 is controlled by the state determining unit 219 to adjust the frequencies of the first clock signal CLK1 and the second clock signal CLK2, the picture clock generator 214 stops. Providing the first clock signal CLK1 to the picture controller 213, so that the first data of the picture controller 213 is temporarily stored The device 231 no longer transmits the data, and the second data register 233 of the picture controller 213 no longer receives the data. At this time, the picture clock generator 217 is controlled by the state determining unit 219 to adjust the frequency of the first clock signal CLK1 and the second clock signal CLK2 to the target frequency, wherein the target frequency can refer to the above embodiment, and no longer Narration. Moreover, the picture clock generator 217 synchronizes the first clock signal CLK1 and the second clock signal CLK2 according to the phase setting signal SPS. After the first clock signal CLK1 and the second clock signal CLK2 are synchronized, the picture clock generator 217 supplies the synchronized first clock signal CLK1 to the picture controller 213.

依據上述,在調整第一時脈信號CLK1及第二時脈信號CLK2的頻率時,畫面控制器213的第二資料暫存器233不會再接收資料,但驅動電路130仍會從第二資料暫存器233擷取資料,亦即顯示資料DD仍為持續傳送。因此,第二資料暫存器233的容量可設計為大於等於畫面時脈產生器217調整第一時脈信號CLK1及第二時脈信號CLK2的頻率且同步化第一時脈信號CLK1及第二時脈信號CLK2所需時間所對應的容量。其中,畫面時脈產生器217可於第一時脈信號CLK1為一接地電壓時傳送或停止傳送第一時脈信號CLK1至畫面控制器213,以避免畫面控制器213產生誤動作。 According to the above, when the frequencies of the first clock signal CLK1 and the second clock signal CLK2 are adjusted, the second data register 233 of the picture controller 213 no longer receives the data, but the driving circuit 130 still receives the second data. The scratchpad 233 retrieves the data, that is, the display data DD is still continuously transmitted. Therefore, the capacity of the second data register 233 can be designed to be greater than or equal to the frequency of the first clock signal CLK1 and the second clock signal CLK2, and the first clock signal CLK1 and the second signal are synchronized. The capacity corresponding to the time required for the clock signal CLK2. The picture clock generator 217 can transmit or stop transmitting the first clock signal CLK1 to the picture controller 213 when the first clock signal CLK1 is a ground voltage, to prevent the picture controller 213 from malfunctioning.

圖3為依據本發明再一實施例的顯示裝置的系統示意圖。請參照圖2及圖3,在本實施例中,顯示裝置300大致相同於顯示裝置200,其不同之處在於時序控制器310的畫面時脈產生器311,並且狀態判斷單元219更耦接畫面介面電路215,其中相同 或相似元件使用相同或相似標號。畫面時脈產生器311包括時脈產生電路313、相位調整單元315及時脈開關單元317,其中相位調整單元315可利用相鎖定迴路(Phase Locked Loop,PLL)或延遲鎖定迴路(Delay Lock Loop,DLL)來實現,但本發明實施例不以此為限。 FIG. 3 is a schematic diagram of a system of a display device according to still another embodiment of the present invention. Referring to FIG. 2 and FIG. 3, in the embodiment, the display device 300 is substantially the same as the display device 200, and is different in the screen clock generator 311 of the timing controller 310, and the state determining unit 219 is further coupled to the screen. Interface circuit 215, wherein the same Or similar elements use the same or similar reference numerals. The picture clock generator 311 includes a clock generation circuit 313, a phase adjustment unit 315, and a pulse switch unit 317, wherein the phase adjustment unit 315 can utilize a Phase Locked Loop (PLL) or a Delay Lock Loop (DLL). The implementation of the present invention is not limited thereto.

時脈產生電路313耦接狀態判斷單元219及畫面緩衝器220,以受控於狀態判斷單元219產生第二時脈信號CLK2。相位調整單元315耦接畫面介面電路215及時脈產生電路313,以依據相位設定信號SPS及第二時脈信號CLK2提供第一時脈信號CLK1。時脈開關單元317耦接狀態判斷單元219、畫面控制器213及相位調整單元315,以受控於狀態判斷單元219將相位調整單元315提供的第一時脈信號CLK1傳送至畫面控制器213。 The clock generation circuit 313 is coupled to the state determination unit 219 and the picture buffer 220 to control the state determination unit 219 to generate the second clock signal CLK2. The phase adjustment unit 315 is coupled to the picture interface circuit 215 and the pulse generation circuit 313 to provide the first clock signal CLK1 according to the phase setting signal SPS and the second clock signal CLK2. The clock switch unit 317 is coupled to the state determining unit 219, the picture controller 213, and the phase adjusting unit 315 to control the state determining unit 219 to transmit the first clock signal CLK1 provided by the phase adjusting unit 315 to the picture controller 213.

進一步來說,當畫面時脈產生器311受控於狀態判斷單元219而調整第一時脈信號CLK1及第二時脈信號CLK2的頻率時,時脈開關單元317會受控於狀態判斷單元219而停止提供第一時脈信號CLK1至畫面控制器213,並且時脈產生電路313受控於狀態判斷單元219調整第二時脈信號CLK2的頻率至目標頻率,其中目標頻率可參照上述實施例,在此則不再贅述。此時,畫面介面電路215會受控於狀態判斷單元219提供相位設定信號SPS,以使畫面時脈產生器217依據相位設定信號SPS及第二時脈信號CLK2提供同步化的第一時脈信號CLK1,其中第一時脈信號CLK1會同步於第二時脈信號CLK2。在第一時脈信號CLK1及第 二時脈信號CLK2同步化後,則時脈開關單元317會受控於狀態判斷單元219將同步化後的第一時脈信號CLK1提供至畫面控制器213。 Further, when the picture clock generator 311 is controlled by the state determining unit 219 to adjust the frequencies of the first clock signal CLK1 and the second clock signal CLK2, the clock switch unit 317 is controlled by the state determining unit 219. The first clock signal CLK1 is stopped from being supplied to the picture controller 213, and the clock generation circuit 313 is controlled by the state determining unit 219 to adjust the frequency of the second clock signal CLK2 to the target frequency, wherein the target frequency can be referred to the above embodiment. I will not repeat them here. At this time, the screen interface circuit 215 is controlled by the state determining unit 219 to provide the phase setting signal SPS, so that the picture clock generator 217 provides the synchronized first clock signal according to the phase setting signal SPS and the second clock signal CLK2. CLK1, wherein the first clock signal CLK1 is synchronized with the second clock signal CLK2. At the first clock signal CLK1 and After the second clock signal CLK2 is synchronized, the clock switching unit 317 is controlled by the state determining unit 219 to supply the synchronized first clock signal CLK1 to the picture controller 213.

在本發明的一實施例中,時脈開關單元317於第一時脈信號CLK1為接地電壓時傳送或停止傳送第一時脈信號CLK1至畫面控制器213,以避免畫面控制器213產生誤動作。 In an embodiment of the invention, the clock switch unit 317 transmits or stops transmitting the first clock signal CLK1 to the picture controller 213 when the first clock signal CLK1 is the ground voltage to prevent the picture controller 213 from malfunctioning.

圖4為依據本發明另一實施例的影音資料信號與顯示資料的時序示意圖。請參照圖4,在本實施例中,假設顯示裝置(如100、200、300)處於重新同步模式的時間對應多個畫面期間,亦即影音資料信號AVD會傳送多個顯示畫面FD31~FD33,顯示資料DD會傳送多個顯示畫面FD41~FD44。並且,本實施例中,影音資料信號AVD所傳送的顯示畫面FD31~FD33不會全部寫入至畫面緩衝器(如120、220),並且在不對畫面緩衝器(如120、220)進行寫入時,畫面緩衝器(如120、220)處於讀取狀態,此時可調整畫面緩衝器(如120、220)的存取頻率為對應顯示資料DD的頻率。 4 is a timing diagram of video and audio data signals and display materials according to another embodiment of the present invention. Referring to FIG. 4, in the embodiment, it is assumed that the time when the display device (eg, 100, 200, 300) is in the resynchronization mode corresponds to a plurality of screen periods, that is, the video material data signal AVD transmits a plurality of display screens FD31 to FD33. The display data DD transmits a plurality of display screens FD41 to FD44. Moreover, in this embodiment, the display screens FD31 FD FD33 transmitted by the video material data signal AVD are not all written to the picture buffer (eg, 120, 220), and the picture buffers (eg, 120, 220) are not written. When the picture buffer (such as 120, 220) is in the read state, the access frequency of the picture buffer (such as 120, 220) can be adjusted to the frequency corresponding to the display data DD.

舉例來說,當顯示裝置(如100、200、300)處於重新同步模式時,影音資料信號AVD所傳送的顯示畫面FD31~FD33中可以寫入第一個顯示畫面(如FD31)至畫面緩衝器(如120、220),寫入奇數個顯示畫面(如FD31、FD33)至畫面緩衝器(如120、220),寫入偶數個顯示畫面(如FD32)至畫面緩衝器(如120、220),或者每n個顯示畫面中寫入一個顯示畫面至畫面緩衝器(如 120、220)。其中,上述顯示畫面的計數可透過計數器來完成,並且上述計數功能可整合於時序控制器(如110、210、310)中。 For example, when the display device (eg, 100, 200, 300) is in the resynchronization mode, the first display screen (such as FD31) can be written to the picture buffer in the display screens FD31~FD33 transmitted by the video material data signal AVD. (such as 120, 220), write an odd number of display screens (such as FD31, FD33) to the picture buffer (such as 120, 220), write an even number of display pictures (such as FD32) to the picture buffer (such as 120, 220) , or write a display screen to the picture buffer every n display screens (eg 120, 220). The counting of the display screen can be completed by using a counter, and the counting function can be integrated into the timing controller (such as 110, 210, 310).

參照圖1A及圖4,當顯示裝置100的操作模式為重新同步模式且影音資料信號AVD傳送的顯示畫面為寫入至畫面緩衝器120(對應第一顯示畫面)時,時序控制器110會將影音資料信號AVD傳送的顯示畫面傳送至畫面緩衝器120。當顯示裝置100的操作模式為重新同步模式且影音資料信號AVD傳送的顯示畫面為不寫入至畫面緩衝器120(對應第二顯示畫面)時,時序控制器110不會將影音資料信號AVD傳送的顯示畫面傳送至畫面緩衝器120。 Referring to FIGS. 1A and 4, when the operation mode of the display device 100 is the resynchronization mode and the display picture transmitted by the video material signal AVD is written to the picture buffer 120 (corresponding to the first display picture), the timing controller 110 will The display screen of the AV material signal AVD transmission is transmitted to the screen buffer 120. When the operation mode of the display device 100 is the resynchronization mode and the display picture transmitted by the video material signal AVD is not written to the picture buffer 120 (corresponding to the second display picture), the timing controller 110 does not transmit the video material signal AVD. The display screen is transferred to the screen buffer 120.

參照圖2、圖3及圖4,當顯示裝置200的操作模式為重新同步模式且影音資料信號AVD傳送的顯示畫面為寫入至畫面緩衝器220(對應第一顯示畫面)時,第一資料暫存器231受控於狀態判斷單元219接收影音資料信號AVD傳送的顯示畫面且提供所接收的顯示畫面。當顯示裝置200的操作模式為重新同步模式且影音資料信號AVD傳送的顯示畫面為不寫入至畫面緩衝器220(對應第二顯示畫面)時,第一資料暫存器231受控於狀態判斷單元219停止接收影音資料信號AVD傳送的顯示畫面且停止提供顯示畫面。 Referring to FIG. 2, FIG. 3 and FIG. 4, when the operation mode of the display device 200 is the resynchronization mode and the display picture transmitted by the video material data signal AVD is written to the picture buffer 220 (corresponding to the first display picture), the first data is used. The register 231 is controlled by the state judging unit 219 to receive the display screen transmitted by the video material signal AVD and to provide the received display screen. When the operation mode of the display device 200 is the resynchronization mode and the display picture transmitted by the video material data signal AVD is not written to the picture buffer 220 (corresponding to the second display picture), the first data register 231 is controlled by the state determination. The unit 219 stops receiving the display screen of the video material signal AVD transmission and stops providing the display screen.

在本發明的一實施例中,當顯示裝置200的操作模式為重新同步模式且影音資料信號AVD傳送的顯示畫面為不寫入至畫面緩衝器220(對應第二顯示畫面)時,畫面時脈產生器(如217、 311)受控於狀態判斷單元219停止提供第一時脈信號CLK1至第一資料暫存器231。 In an embodiment of the present invention, when the operation mode of the display device 200 is the resynchronization mode and the display picture transmitted by the video material data signal AVD is not written to the picture buffer 220 (corresponding to the second display picture), the picture clock is Generator (such as 217, 311) The controlled state determination unit 219 stops providing the first clock signal CLK1 to the first data register 231.

圖5為依據本發明一實施例的顯示裝置的時序控制器的運作方法的流程圖。請參照圖5,在本實施例中,時序控制器的運作方法包括下列步驟。時序控制器依據影音來源提供的影音控制信號決定操作模式(步驟S510)。時序控制器依據操作模式輸出對應影音資料信號的顯示資料或對應儲存於畫面緩衝器的畫面的顯示資料(步驟S520)。時序控制器依據操作模式調整顯示裝置的畫面緩衝器的存取頻率(步驟S530)。 FIG. 5 is a flow chart showing a method of operating a timing controller of a display device according to an embodiment of the invention. Referring to FIG. 5, in the embodiment, the operation method of the timing controller includes the following steps. The timing controller determines an operation mode according to the video control signal provided by the video source (step S510). The timing controller outputs display data corresponding to the audio/visual material signal or display data corresponding to the screen stored in the picture buffer according to the operation mode (step S520). The timing controller adjusts the access frequency of the picture buffer of the display device in accordance with the operation mode (step S530).

圖6為依據本發明另一實施例的顯示裝置的時序控制器的運作方法的流程圖。請參照圖5及6,在本實施例中,時序控制器的運作方法更包括步驟S610、S620及S630。在步驟S610中,時序控制器判斷操作模式是否為重新同步模式。當操作模式為重新同步模式且影音資料信號傳送第一顯示畫面(亦即要寫入畫面緩衝器的顯示畫面)時,時序控制器將所接收的第一顯示畫面傳送至畫面緩衝器(步驟S620)。當操作模式為重新同步模式且影音資料信號傳送第二顯示畫面(亦即不寫入畫面緩衝器的顯示畫面)時,時序控制器停止接收第二顯示畫面且停止提供所接收顯示畫面至畫面緩衝器(步驟S630)。其中,步驟S610、S620及S630於操作模式為重新同步模式時可持續執行,但本發明實施例不以此為限。並且,上述步驟S510、S520、S530、S610、S620及S630的順序為用以說明,本發明實施例不以為限。以及,上述步驟 S510、S520、S530、S610、S620及S630的細節可參照圖1A至圖1C、圖2、圖3及圖4的實施例,在此則不再贅述。 6 is a flow chart showing a method of operating a timing controller of a display device in accordance with another embodiment of the present invention. Referring to FIG. 5 and FIG. 6 , in the embodiment, the operation method of the timing controller further includes steps S610, S620, and S630. In step S610, the timing controller determines whether the operation mode is the resynchronization mode. When the operation mode is the resynchronization mode and the video data signal transmits the first display picture (that is, the display picture to be written to the picture buffer), the timing controller transmits the received first display picture to the picture buffer (step S620). ). When the operation mode is the resynchronization mode and the video data signal transmits the second display picture (that is, the display picture not written to the picture buffer), the timing controller stops receiving the second display picture and stops providing the received display picture to the picture buffer. (step S630). The steps S610, S620, and S630 are continuously performed when the operation mode is the resynchronization mode, but the embodiment of the present invention is not limited thereto. The order of the above steps S510, S520, S530, S610, S620, and S630 is for illustrative purposes, and the embodiments of the present invention are not limited thereto. And the above steps For details of S510, S520, S530, S610, S620, and S630, reference may be made to the embodiments of FIG. 1A to FIG. 1C, FIG. 2, FIG. 3, and FIG. 4, and details are not described herein again.

綜上所述,本發明實施例的顯示裝置及其時序控制器的其時序控制器的運作方法,其時序控制器可依據操作模式調整顯示裝置的畫面緩衝器的存取頻率,藉此可在部分操作模式中降低畫面緩衝器的存取頻率,以降低顯示裝置的電力消耗。 In summary, the display device of the embodiment of the present invention and the operation method of the timing controller of the timing controller thereof, the timing controller can adjust the access frequency of the picture buffer of the display device according to the operation mode, thereby The access frequency of the picture buffer is reduced in the partial operation mode to reduce the power consumption of the display device.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧影音來源 10‧‧‧Video source

100‧‧‧顯示裝置 100‧‧‧ display device

110‧‧‧時序控制器 110‧‧‧Sequence Controller

120‧‧‧畫面緩衝器 120‧‧‧ Picture buffer

130‧‧‧驅動電路 130‧‧‧Drive circuit

140‧‧‧顯示面板 140‧‧‧ display panel

150‧‧‧電源供應單元 150‧‧‧Power supply unit

AVC‧‧‧影音控制信號 AVC‧‧‧Video Control Signal

AVD‧‧‧影音資料信號 AVD‧‧‧ audio and video data signal

DD‧‧‧顯示資料 DD‧‧‧Display information

VDDA‧‧‧系統電壓 VDDA‧‧‧ system voltage

Claims (24)

一種顯示裝置,包括:一畫面緩衝器;一時序控制器,耦接一影音來源及該畫面緩衝器,以接收來自該影像來源的一影音控制信號及一影音資料信號,且輸出一顯示資料;一顯示面板;以及一驅動電路,耦接該時序控制器及該顯示面板,以依據該顯示資料驅動該顯示面板;其中,該時序控制器依據該影音控制信號決定一操作模式,該時序控制器依據該操作模式輸出對應該影音資料信號的該顯示資料或對應儲存於該畫面緩衝器的畫面的該顯示資料,並且該時序控制器依據該操作模式調整該畫面緩衝器的存取頻率;當該操作模式為一標準模式時,該時序控制器輸出對應該影音資料信號的該顯示資料,且設定該畫面緩衝器的存取頻率為零。 A display device includes: a picture buffer; a timing controller coupled to a video source and the picture buffer for receiving an audio and video control signal and a video data signal from the image source, and outputting a display data; a display panel, and a driving circuit coupled to the timing controller and the display panel to drive the display panel according to the display data; wherein the timing controller determines an operation mode according to the audio and video control signal, the timing controller And outputting the display data corresponding to the video data signal or the display data corresponding to the picture stored in the picture buffer according to the operation mode, and the timing controller adjusts the access frequency of the picture buffer according to the operation mode; When the operation mode is a standard mode, the timing controller outputs the display material corresponding to the video data signal, and sets the access frequency of the picture buffer to zero. 如申請專利範圍第1項所述的顯示裝置,更包括一電源供應單元,耦接該時序控制器及該畫面緩衝器,用以提供一系統電壓至該畫面緩衝器及該時序控制器中存取該畫面緩衝器的部分電路,當該操作模式為該標準模式時,該時序控制器控制該電源供應單元停止提供該系統電壓。 The display device of claim 1, further comprising a power supply unit coupled to the timing controller and the picture buffer for providing a system voltage to the picture buffer and the timing controller And taking part of the circuit of the picture buffer, when the operation mode is the standard mode, the timing controller controls the power supply unit to stop providing the system voltage. 如申請專利範圍第1項所述的顯示裝置,其中當該操作模式為一快取模式時,該時序控制器輸出對應該影音資料信號的該 顯示資料,將該影音資料信號所傳送的畫面儲存於該畫面緩衝器,並且設定該畫面緩衝器的存取頻率為對應該影音資料信號的頻率。 The display device of claim 1, wherein when the operation mode is a cache mode, the timing controller outputs the corresponding audio and video data signal. The data is displayed, and the picture transmitted by the video data signal is stored in the picture buffer, and the access frequency of the picture buffer is set to a frequency corresponding to the video data signal. 如申請專利範圍第1項所述的顯示裝置,其中當該操作模式為一自我更新模式時,該時序控制器輸出對應儲存於該畫面緩衝器的畫面的該顯示資料,且設定該畫面緩衝器的存取頻率為對應該顯示資料的頻率。 The display device of claim 1, wherein when the operation mode is a self-updating mode, the timing controller outputs the display material corresponding to the picture stored in the picture buffer, and sets the picture buffer. The access frequency is the frequency corresponding to the data displayed. 如申請專利範圍第1項所述的顯示裝置,其中當該操作模式為一畫面更新模式時,該時序控制器輸出對應儲存於該畫面緩衝器的畫面的該顯示資料,將該影音資料信號所傳送的畫面儲存於該畫面緩衝器,且設定該畫面緩衝器的存取頻率為對應該影音資料信號的頻率及該顯示資料的頻率的總和。 The display device of claim 1, wherein when the operation mode is a screen update mode, the timing controller outputs the display material corresponding to the screen stored in the screen buffer, and the video data signal is The transmitted picture is stored in the picture buffer, and the access frequency of the picture buffer is set to be the sum of the frequency corresponding to the video data signal and the frequency of the displayed data. 如申請專利範圍第1項所述的顯示裝置,其中當該操作模式為一重新同步模式時,該時序控制器輸出對應儲存於該畫面緩衝器的畫面的該顯示資料,將該影音資料信號所傳送的畫面儲存於該畫面緩衝器,且設定該畫面緩衝器的存取頻率為對應該影音資料信號的頻率及該顯示資料的頻率的總和。 The display device of claim 1, wherein when the operation mode is a resynchronization mode, the timing controller outputs the display material corresponding to the picture stored in the picture buffer, and the video data signal is The transmitted picture is stored in the picture buffer, and the access frequency of the picture buffer is set to be the sum of the frequency corresponding to the video data signal and the frequency of the displayed data. 如申請專利範圍第1項所述的顯示裝置,其中該時序控制器包括:一資料多工器,具有一第一輸入端、一第二輸入端及一輸出端,該第一輸入端耦接該影音來源以接收該影音資料信號,該輸出端輸出該顯示資料; 一畫面控制器,具有一第一資料暫存器及一第二資料暫存器,該第一資料暫存器的輸入端耦接該影音來源以接收該影音資料信號,該第二資料暫存器的輸出端耦接該資料多工器的第二輸入端;一畫面介面電路,用以耦接該畫面控制器的該第一資料暫存器的輸出端與該畫面緩衝器的輸入端,且耦接該畫面控制器的該第二資料暫存器的輸入端與該畫面緩衝器的輸出端;一畫面時脈產生器,耦接該畫面控制器及該畫面介面電路,以提供一第一時脈信號至該畫面控制器及該畫面介面電路,並且耦接該畫面緩衝器以提供一第二時脈信號至該畫面緩衝器;以及一狀態判斷單元,耦接該影音來源以接收該影音控制信號,以依據該影音控制信號判斷該操作模式,耦接該資料多工器以控制該資料多工器的該輸出端耦接該第一輸入端或該第二輸入端,耦接該畫面時脈產生器以依據該操作模式調整該第一時脈信號及該第二時脈信號的頻率,以及耦接該畫面控制器以控制該畫面控制器的運作。 The display device of claim 1, wherein the timing controller comprises: a data multiplexer having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled The audio and video source receives the video data signal, and the output end outputs the display data; a picture controller having a first data register and a second data register, wherein the input end of the first data register is coupled to the video source to receive the video data signal, and the second data is temporarily stored The output end of the device is coupled to the second input end of the data multiplexer; a picture interface circuit is configured to couple the output end of the first data register of the picture controller and the input end of the picture buffer, And an input end of the second data buffer coupled to the picture controller and an output end of the picture buffer; a picture clock generator coupled to the picture controller and the picture interface circuit to provide a first a clock signal to the picture controller and the picture interface circuit, and coupled to the picture buffer to provide a second clock signal to the picture buffer; and a state determining unit coupled to the video source to receive the The audio and video control signal is configured to determine the operation mode according to the audio and video control signal, and coupled to the data multiplexer to control the output end of the data multiplexer to be coupled to the first input end or the second input end, coupled to the Picture time production It is adjusted according to the operating mode of the first clock signal and the frequency of the second clock signal, and coupled to the controller to control the operation of the picture screen of the controller. 如申請專利範圍第7項所述的顯示裝置,其中該第一資料暫存器及該第二資料暫存器分別為一先進先出(FIFO)暫存器。 The display device of claim 7, wherein the first data register and the second data register are respectively a first in first out (FIFO) register. 如申請專利範圍第7項所述的顯示裝置,其中當該操作模式為一標準模式時,該狀態判斷單元控制該資料多工器的該輸出端耦接該第一輸入端,控制該畫面控制器為停止狀態,且調整該第一時脈信號及該第二時脈信號的頻率為零。 The display device of claim 7, wherein the state determining unit controls the output end of the data multiplexer to be coupled to the first input terminal to control the screen control when the operating mode is a standard mode. The device is in a stopped state, and the frequency of the first clock signal and the second clock signal is adjusted to be zero. 如申請專利範圍第9項所述的顯示裝置,更包括一電源供應單元,耦接該狀態判斷單元、該畫面控制器、該畫面介面電路及該畫面緩衝器,用以提供一系統電壓至該畫面控制器、該畫面介面電路及該畫面緩衝器,當該操作模式為該標準模式時,該狀態判斷單元控制該電源供應單元停止提供該系統電壓。 The display device of claim 9, further comprising a power supply unit coupled to the state determination unit, the picture controller, the picture interface circuit and the picture buffer for providing a system voltage to the The picture controller, the picture interface circuit and the picture buffer, when the operation mode is the standard mode, the state determining unit controls the power supply unit to stop providing the system voltage. 如申請專利範圍第7項所述的顯示裝置,其中當該操作模式為一快取模式時,該狀態判斷單元控制該資料多工器的該輸出端耦接該第一輸入端,控制該畫面控制器為運作狀態,且調整該第一時脈信號及該第二時脈信號的頻率為對應該影音資料信號的頻率。 The display device of claim 7, wherein the state determining unit controls the output end of the data multiplexer to be coupled to the first input terminal to control the screen when the operating mode is a cache mode. The controller is in an operational state, and the frequency of the first clock signal and the second clock signal is adjusted to be a frequency corresponding to the video data signal. 如申請專利範圍第7項所述的顯示裝置,其中當該操作模式為一自我更新模式時,該狀態判斷單元控制該資料多工器的該輸出端耦接該第二輸入端,控制該畫面控制器為運作狀態,且調整該第一時脈信號及該第二時脈信號的頻率為對應該顯示資料的頻率。 The display device of claim 7, wherein when the operation mode is a self-updating mode, the state determining unit controls the output end of the data multiplexer to be coupled to the second input terminal to control the screen. The controller is in an operational state, and the frequency of the first clock signal and the second clock signal is adjusted to be a frequency corresponding to the data to be displayed. 如申請專利範圍第7項所述的顯示裝置,其中當該操作模式為一畫面更新模式時,該狀態判斷單元控制該資料多工器的該輸出端耦接該第二輸入端,控制該畫面控制器為運作狀態,且調整該第一時脈信號及該第二時脈信號的頻率為對應該影音資料信號的頻率及該顯示資料的頻率的總和。 The display device of claim 7, wherein the state determining unit controls the output end of the data multiplexer to be coupled to the second input terminal to control the screen when the operation mode is a screen update mode. The controller is in an operational state, and the frequency of the first clock signal and the second clock signal is adjusted to be a sum of a frequency corresponding to the video data signal and a frequency of the display data. 如申請專利範圍第7項所述的顯示裝置,其中當該操作模式為一重新同步模式,該狀態判斷單元控制該資料多工器的該 輸出端耦接該第二輸入端,控制該畫面控制器為運作狀態,且調整該第一時脈信號及該第二時脈信號的頻率為對應該影音資料信號的頻率及該顯示資料的頻率的總和。 The display device of claim 7, wherein the state determining unit controls the data multiplexer when the operation mode is a resynchronization mode The output end is coupled to the second input end, and controls the picture controller to be in an operational state, and adjusts a frequency of the first clock signal and the second clock signal to a frequency corresponding to the video data signal and a frequency of the display data Sum. 如申請專利範圍第14項所述的顯示裝置,其中當該操作模式為該重新同步模式且該影音資料信號傳送一第一顯示畫面時,該第一資料暫存器受控於該狀態判斷單元接收該第一顯示畫面且提供所接收的第一顯示畫面,當該操作模式為該重新同步模式且該影音資料信號傳送一第二顯示畫面時,該第一資料暫存器受控於該狀態判斷單元停止接收該第二顯示畫面且停止提供顯示畫面。 The display device of claim 14, wherein the first data register is controlled by the state determining unit when the operating mode is the resynchronization mode and the video data signal transmits a first display picture. Receiving the first display screen and providing the received first display screen, when the operation mode is the resynchronization mode and the video data signal transmits a second display screen, the first data register is controlled by the state The determination unit stops receiving the second display screen and stops providing the display screen. 如申請專利範圍第15項所述的顯示裝置,其中當該操作模式為該重新同步模式且該影音資料信號傳送該第二顯示畫面時,該畫面時脈產生器受控於該狀態判斷單元停止提供該第一時脈信號至該第一資料暫存器。 The display device of claim 15, wherein when the operation mode is the resynchronization mode and the video data signal transmits the second display picture, the picture clock generator is controlled by the state determination unit to stop. Providing the first clock signal to the first data register. 如申請專利範圍第7項所述的顯示裝置,其中該畫面介面電路提供受控於該狀態判斷單元提供一相位設定信號,當該畫面時脈產生器受控於該狀態判斷單元調整該第一時脈信號及該第二時脈信號的頻率時,該畫面時脈產生器停止提供該第一時脈信號至該畫面控制器,調整該第一時脈信號及該第二時脈信號的頻率至一目標頻率,並且依據該相位設定信號同步化該第一時脈信號及該第二時脈信號,接著將同步化後的該第一時脈信號提供至該畫面控制器。 The display device of claim 7, wherein the picture interface circuit provides control by the state determining unit to provide a phase setting signal, and when the picture clock generator is controlled by the state determining unit, adjusting the first The clock signal generator stops providing the first clock signal to the picture controller to adjust the frequency of the first clock signal and the second clock signal when the frequency of the clock signal and the second clock signal is Up to a target frequency, and synchronizing the first clock signal and the second clock signal according to the phase setting signal, and then providing the synchronized first clock signal to the picture controller. 如申請專利範圍第17項所述的顯示裝置,其中該第二資料暫存器的容量大於等於該畫面時脈產生器調整該第一時脈信號及該第二時脈信號的頻率且同步化該第一時脈信號及該第二時脈信號所需時間所對應的容量。 The display device of claim 17, wherein the capacity of the second data register is greater than or equal to the frequency of the first clock signal and the second clock signal of the picture clock generator and is synchronized The capacity corresponding to the time required by the first clock signal and the second clock signal. 如申請專利範圍第17項所述的顯示裝置,其中該畫面時脈產生器包括:一時脈產生電路,耦接該狀態判斷單元及該畫面緩衝器,以受控於該狀態判斷單元產生該第二時脈信號;一相位調整單元,耦接該畫面介面電路及該時脈產生電路,以依據該相位設定信號及該第二時脈信號提供該第一時脈信號;以及一時脈開關單元,耦接該狀態判斷單元、該畫面控制器及該相位調整單元,以受控於該狀態判斷單元將該相位調整單元提供的該第一時脈信號傳送至該畫面控制器。 The display device of claim 17, wherein the picture clock generator comprises: a clock generation circuit coupled to the state determination unit and the picture buffer, to be controlled by the state determination unit to generate the a second clock signal; a phase adjustment unit coupled to the picture interface circuit and the clock generation circuit to provide the first clock signal according to the phase setting signal and the second clock signal; and a clock switch unit, The state determining unit, the picture controller and the phase adjusting unit are coupled to the state determining unit to transmit the first clock signal provided by the phase adjusting unit to the picture controller. 如申請專利範圍第19項所述的顯示裝置,其中該時脈開關單元於該第一時脈信號為一接地電壓時傳送或停止傳送該第一時脈信號至該畫面控制器。 The display device of claim 19, wherein the clock switch unit transmits or stops transmitting the first clock signal to the picture controller when the first clock signal is a ground voltage. 一種顯示裝置的時序控制器的運作方法,包括:該時序控制器依據一影音來源提供的一影音控制信號決定一操作模式;該時序控制器依據該操作模式輸出對應該影音資料信號的一顯示資料或對應儲存於該畫面緩衝器的畫面的該顯示資料;以及 該時序控制器依據該操作模式調整該顯示裝置的一畫面緩衝器的存取頻率。 A method for operating a timing controller of a display device includes: determining, by the timing controller, an operation mode according to an audio and video control signal provided by an audio and video source; and outputting, by the timing controller, a display data corresponding to the audio and video data signal according to the operation mode Or corresponding to the display material stored in the screen buffer; and The timing controller adjusts an access frequency of a picture buffer of the display device according to the operation mode. 如申請專利範圍第21項所述的顯示裝置的時序控制器的運作方法,其中該時序控制器依據該操作模式調整該顯示裝置的該畫面緩衝器的存取頻率的步驟包括:當該操作模式為一標準模式時,該時序控制器輸出對應該影音資料信號的該顯示資料,且設定該畫面緩衝器的存取頻率為零;當該操作模式為一快取模式時,該時序控制器輸出對應該影音資料信號的該顯示資料,將該影音資料信號所傳送的畫面儲存於該畫面緩衝器,並且設定該畫面緩衝器的存取頻率為對應該影音資料信號的頻率;當該操作模式為一自我更新模式時,該時序控制器輸出對應儲存於該畫面緩衝器的畫面的該顯示資料,且設定該畫面緩衝器的存取頻率為對應該顯示資料的頻率;當該操作模式為一畫面更新模式時,該時序控制器輸出對應儲存於該畫面緩衝器的畫面的該顯示資料,將該影音資料信號所傳送的畫面儲存於該畫面緩衝器,且設定該畫面緩衝器的存取頻率為對應該影音資料信號的頻率及該顯示資料的頻率的總和;以及當該操作模式為一重新同步模式時,該時序控制器輸出對應儲存於該畫面緩衝器的畫面的該顯示資料,將該影音資料信號所傳送的畫面儲存於該畫面緩衝器,且設定該畫面緩衝器的存取頻 率為對應該影音資料信號的頻率及該顯示資料的頻率的總和。 The method of operating a timing controller of a display device according to claim 21, wherein the step of adjusting the access frequency of the picture buffer of the display device according to the operation mode comprises: when the operation mode In a standard mode, the timing controller outputs the display data corresponding to the video data signal, and sets the access frequency of the picture buffer to zero; when the operation mode is a cache mode, the timing controller outputs And corresponding to the display data of the audio and video data signal, storing the picture transmitted by the video data signal in the picture buffer, and setting the access frequency of the picture buffer to correspond to the frequency of the video data signal; when the operation mode is In a self-updating mode, the timing controller outputs the display data corresponding to the picture stored in the picture buffer, and sets the access frequency of the picture buffer to the frequency corresponding to the data; when the operation mode is a picture In the update mode, the timing controller outputs the display material corresponding to the screen stored in the screen buffer, and the The picture transmitted by the audio data signal is stored in the picture buffer, and the access frequency of the picture buffer is set to be the sum of the frequency corresponding to the video data signal and the frequency of the display data; and when the operation mode is a resynchronization In the mode, the timing controller outputs the display data corresponding to the screen stored in the picture buffer, stores the picture transmitted by the video material signal in the picture buffer, and sets the access frequency of the picture buffer. The ratio is the sum of the frequency of the audiovisual data signal and the frequency of the displayed data. 如申請專利範圍第22項所述的顯示裝置的時序控制器的運作方法,更包括:當該操作模式為該標準模式時,該時序控制器控制一電源供應單元提供的一系統電壓停止提供至該畫面緩衝器及該時序控制器中存取該畫面緩衝器的部分電路。 The method for operating a timing controller of a display device according to claim 22, further comprising: when the operating mode is the standard mode, the timing controller controls a system voltage provided by a power supply unit to stop providing The picture buffer and a part of the circuit of the timing controller that access the picture buffer. 如申請專利範圍第22項所述的顯示裝置的時序控制器的運作方法,更包括:當該操作模式為該重新同步模式且該影音資料信號傳送一第一顯示畫面時,該時序控制器將所接收的該第一顯示畫面傳送至該畫面緩衝器;以及當該操作模式為該重新同步模式且該影音資料信號傳送一第二顯示畫面時,該時序控制器停止接收該第二顯示畫面且停止提供所接收顯示畫面至該畫面緩衝器。 The method for operating the timing controller of the display device of claim 22, further comprising: when the operating mode is the resynchronization mode and the video data signal transmits a first display screen, the timing controller The received first display screen is transmitted to the picture buffer; and when the operation mode is the resynchronization mode and the video material signal transmits a second display picture, the timing controller stops receiving the second display picture and The supply of the received display screen to the screen buffer is stopped.
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