TWI572506B - Apparatus with load dump protection - Google Patents

Description

Electronic device with load dump protection

The present invention relates to an electronic device having Load Dump Protection.

When an automotive electronic system encounters an abnormal condition (such as a load dump, a surge, or a transient voltage in a switching state), the voltage at the power supply terminal may sometimes be abnormally steep or steep in a short period of time. . For example, when a load dump occurs, a voltage of up to 100V is applied to the components of the automotive electronics system. To protect the components from permanent damage due to transient changes in the vehicle's power supply, it is necessary to provide a protection circuit.

According to an embodiment of the invention, an electronic device has load dump protection and is used to drive a load between a first output node and a second output node. The electronic device comprises a first half bridge output stage, a second half bridge output stage, a first voltage comparator, a second voltage comparator, a first clamping circuit and a second clamping circuit. The first half bridge output stage has a first transistor and a second transistor, wherein the first transistor and the second transistor are connected in series between a power voltage and a reference voltage, and the a first half bridge output stage having the first transistor and The first output node between the second transistors. The second half bridge output stage has a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are connected in series between the power voltage and the reference voltage, and the The second half bridge output stage has the second output node between the third transistor and the fourth transistor. The first voltage comparator is configured to compare the power voltage with a first set voltage, thereby generating a first comparison signal when the power voltage is greater than the first set voltage. The second voltage comparator is configured to compare the power voltage and a second set voltage, thereby generating a second comparison signal when the power voltage is greater than the second set voltage. The first clamping circuit is configured to perform a voltage dividing operation on the power supply voltage to generate a first divided voltage at the first output node according to the second comparison signal. The second clamping circuit is configured to perform a voltage dividing operation on the power supply voltage to generate a second divided voltage at the second output node according to the second comparison signal. The second set voltage is greater than the first set voltage. The first transistor, the second transistor, the third transistor, and the fourth transistor are not turned on according to the first comparison signal.

100,400‧‧‧Electronic devices

11,11'‧‧‧ drive circuit

12,12’‧‧‧load

14,14'‧‧‧Half-bridge output stage

15,15'‧‧‧Half-bridge output stage

16,16'‧‧‧Clamp circuit

18,18’‧‧‧Clamp circuit

20,20’‧‧‧Voltage comparator

22,22’‧‧‧Voltage comparator

42‧‧‧Boost circuit

C1~C4‧‧‧ capacitor

M1~M10‧‧‧O crystal

M1’~M4’‧‧•O crystal

R1~R4‧‧‧ resistor

The first figure shows a block diagram of an electronic device incorporating an embodiment of the present invention.

The second figure shows a circuit diagram of the clamp circuit incorporating an embodiment of the present invention.

The third figure shows a circuit diagram of the clamp circuit incorporating another embodiment of the present invention.

The fourth figure shows a block diagram of an electronic device incorporating another embodiment of the present invention.

Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" or "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

The first figure shows a block diagram of an electronic device 100 in accordance with an embodiment of the present invention. Referring to the first figure, the electronic device 100 includes a class D amplifier to drive a load 12. Class D amplifiers are often used as speaker drivers in consumer, automotive, and handheld applications. The Class D amplifier in the first figure has an H-bridge output stage. The H-bridge output stage consists of two half bridge output stages 14 and 15. The half bridge output stage 14 has an upper bridge transistor M1 and a lower bridge transistor M2, wherein the upper bridge transistor M1 and the lower bridge transistor M2 are connected in series to a power supply voltage VDD and a reference. Between voltage GND. The half bridge output stage 15 has an upper bridge transistor M3 and a lower bridge transistor M4, wherein the upper bridge transistor M3 and the lower bridge transistor M4 are connected in series to the power supply voltage VDD and the reference voltage GND between. The half bridge output stage 14 has a non-inverting output terminal OUTP, and the half bridge output stage 15 has an inverting output terminal OUTN.

The electronic device 100 further includes two clamp circuits 16 and 18, wherein the two clamp circuits 16 and 18 are connected in series between the power supply voltage VDD and the reference voltage GND. The clamping circuit 16 is configured to divide the power supply voltage VDD to generate a divided voltage at the non-inverting output terminal OUTP of the half-bridge output stage 14. The clamp circuit 18 is configured to divide the power supply voltage VDD to generate a divided voltage at the inverted output terminal OUTN of the half bridge output stage 15.

The electronic device 100 further includes two voltage comparators 20 and 22. The voltage comparator 20 is configured to compare the power supply voltage VDD and a set voltage VC1 to generate a comparison signal CP1. The voltage comparator 22 is configured to compare the power supply voltage VDD and a set voltage VC2 to generate a comparison signal CP2. The comparison signal CP1 determines whether the transistors M1, M2, M3, and M4 in the H-bridge output stage enter an off state, and the comparison signal CP2 determines whether the two clamp circuits 16 and 18 are enabled.

In normal operation, that is, when the power supply voltage VDD is lower than a first predetermined fixed voltage (for example, 22V), the transistor M1 in the half-bridge output stage 14 and the power of the half-bridge output stage 15 Crystal M4 is turned on and the half bridge output The transistor M2 of the stage 14 and the transistor M3 of the half bridge output stage 15 are turned off, at which time the load current flows from the left side of the load to the right side of the load; and when the transistor M2 of the half bridge output stage 14 and the half bridge type The transistor M3 of the output stage 15 is turned on and the transistor M1 of the half-bridge output stage 14 and the transistor M4 of the half-bridge output stage 15 are turned off, at which time the load current flows from the right side of the load to the left side of the load.

When a load dump occurs, the power supply voltage VDD first rises steeply above the first predetermined fixed voltage for a short period of time. The voltage comparator 20 generates the comparison signal CP1 when the power supply voltage VDD is higher than the first predetermined fixed voltage. The comparison signal CP1 is then passed to a drive circuit 11 to turn off the transistors M1, M2, M3 and M4 in the H-bridge output stage to protect the components. Thereafter, if the power supply voltage VDD continues to rise above a second predetermined fixed voltage, for example, when the power supply voltage VDD is higher than 28V, a protection mechanism is activated to protect the transistors M1, M2 in the off state. M3 and M4.

The voltage comparator 22 generates the comparison signal CP2 when the power supply voltage VDD is higher than the second predetermined fixed voltage. The comparison signal CP2 is then passed to the clamp circuit 16 to limit the voltage of the non-inverted output terminal OUTP of the half-bridge output stage 14 and to the clamp circuit 18 to limit the half-bridge output stage 15 The voltage at the inverting output terminal OUTN. The second figure shows a circuit diagram of the clamp circuit 16 and the clamp circuit 18 in conjunction with an embodiment of the present invention. Referring to the second figure, the clamp circuit 16 includes a plurality of resistors R1 and R2, wherein the resistors R1 and R2 are connected in series to the power supply voltage VDD through a transistor M5. The clamping circuit 18 includes a plurality of resistors R3 and R4, wherein the resistors R3 and R4 are connected in series to the supply voltage VDD through a transistor M6.

An operation of the clamp circuit 16 and the clamp circuit 18 will be described below with reference to the first and second figures. When the power supply voltage VDD rises above the second predetermined fixed voltage, the transistors M5 and M6 are turned on. Since the equivalent resistance when the transistor M5 is turned on is much smaller than the total resistance of the resistor R1 and the resistor R2, the clamp circuit 16 generates a divided voltage according to the resistance ratio of the resistors R1 and R2; since the transistor M6 is turned on The equivalent resistance is much smaller than the total resistance of the resistor R3 and the resistor R4, and the clamp circuit 18 generates a divided voltage according to the resistance ratio of the resistors R3 and R4.

The two-stage protection mode of the electronic device 100 when a load dump occurs is explained below with reference to the first and second figures. When the power supply voltage VDD rises above the first predetermined fixed voltage (eg, 22V), the transistors M1, M2, M3, and M4 in the H-bridge output stage are turned off. However, when the supply voltage VDD continues to rise, such a high supply voltage causes the drain-to-source extreme voltages of the transistors M1, M2, M3, and M4 to exceed the rated drain-to-source extinction voltage of the transistor (breakdown) Voltage, BVdss). Thus, the clamp circuit 16 and the clamp circuit 18 are activated to limit the drain-to-source extreme voltages of the transistors M1, M2, M3, and M4. Referring to the second figure, in an embodiment of the invention, the resistance ratios of the resistors R1 and R2 are set to 1:1, and the resistance ratios of the resistors R3 and R4 are set to 1:1. Therefore, the clamp circuit 16 divides the power supply voltage VDD by a voltage division operation of 2 to generate a divided voltage, thereby limiting the voltage of the non-inverted output terminal OUTP, and the clamp circuit 18 applies the voltage to the power supply voltage. VDD performs a divided operation of 2 to generate a divided voltage, thereby limiting the voltage of the inverted output terminal OUTN.

The clamp circuit 16 and the clamp circuit 18 illustrated in the second figure are in the form of a resistor divider, but the invention is not limited thereto. Referring to the third figure, the clamp circuit 16' and the clamp circuit 18' are in the form of a capacitive voltage divider. When the transistor M7, the transistor M8, the transistor M9, and the transistor M10 are turned on, the clamp circuit 16' is generated at the non-inverted output terminal OUTP of the half-bridge output stage 14 according to the capacitance ratio of the capacitors C1 and C2. A voltage is divided, and the clamp circuit 18' generates a divided voltage at the inverted output terminal OUTN of the half bridge output stage 15 according to the capacitance ratio of the capacitors C3 and C4. Therefore, the drain-to-source extreme voltages of the transistors M1, M2, M3, and M4 can be limited by the clamp circuit 16' and the clamp circuit 18'. In addition, the drain-to-source extreme voltages of the transistors M1 and M2 in the off state can be adjusted by the capacitance ratio of the capacitors C1 and C2, and the drains of the transistors M3 and M4 in the off state are The source extreme voltage can be adjusted by the ratio of the capacitance values of the capacitors C3 and C4.

Referring to the first figure, the transistors M1 and M3 in the H-bridge output stage are P-channel transistors, and the transistors M2 and M4 in the H-bridge output stage are N-channel transistors, but the present invention Not limited to this. Referring to the fourth figure, the transistors M1', M2', M3' and M4' in the H-bridge output stage are all N-channel transistors. In this embodiment, a bootstrap capacitor (not shown) is used to boost the gate voltage of the upper bridge transistor M1' in the half bridge output stage 14' and boost the half bridge output stage. Gate of the upper bridge transistor M3' in 15' Pressure. When the load dump occurs, if the power supply voltage VDD rises above the first predetermined fixed voltage (eg, 22V), the transistors M1', M2', M3', and M4 in the H-bridge output stage 'First will be closed. If the power supply voltage VDD continues to rise above the second predetermined fixed voltage (eg, 28V), the clamp circuit 16' and the clamp circuit 18' are activated to limit the transistors M1', M2', The drain-to-source extreme voltages of M3' and M4' protect these components from permanent damage.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is not to be construed as being limited by the scope of the invention, and

100‧‧‧Electronic devices

11‧‧‧Drive circuit

12‧‧‧ load

14‧‧‧Half-bridge output stage

15‧‧‧Half-bridge output stage

16‧‧‧Clamp circuit

18‧‧‧Clamp circuit

20‧‧‧Voltage comparator

22‧‧‧Voltage comparator

M1~M4‧‧‧O crystal

Claims (9)

An electronic device for driving a load between a first output node and a second output node, the electronic device comprising: a first half bridge output stage having a first transistor and a second transistor The first transistor and the second transistor are connected in series between a power supply voltage and a reference voltage, and the first half bridge output stage has the first transistor and the second transistor. The first output node; a second half bridge output stage having a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are connected to the power supply in series Between the voltage and the reference voltage, and the second half-bridge output stage has the second output node between the third transistor and the fourth transistor; a first voltage comparator for comparing the a power supply voltage and a first set voltage, wherein a first comparison signal is generated when the power supply voltage is greater than the first set voltage; and a second voltage comparator is configured to compare the power supply voltage with a second set voltage, thereby The power supply voltage Generating a second comparison signal at the second set voltage; a first clamping circuit is configured to perform a voltage dividing operation on the power supply voltage to generate a first divided voltage at the first output node according to the second comparison signal ;as well as a second clamping circuit is configured to perform a voltage dividing operation on the power supply voltage to generate a second divided voltage at the second output node according to the second comparison signal; wherein the second set voltage is greater than the first set voltage And wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are not turned on according to the first comparison signal. The electronic device of claim 1, wherein the first transistor is a P-channel transistor, the second transistor is an N-channel transistor, and the third transistor is a P-channel transistor, and the fourth device The crystal is an N-channel transistor. The electronic device of claim 1, wherein the first transistor is an N-channel transistor, the second transistor is an N-channel transistor, and the third transistor is an N-channel transistor, and the fourth device The crystal is an N-channel transistor. The electronic device of claim 1, wherein the first clamping circuit comprises a plurality of resistors connected in series to the power supply voltage via a fifth transistor, the fifth transistor being in accordance with the second Compare the signal and turn it on. The electronic device of claim 1, wherein the second clamping circuit comprises a plurality of resistors connected in series to the power supply voltage via a sixth transistor, the sixth transistor being in accordance with the second Compare the signal and turn it on. The electronic device of claim 1, wherein the first clamp circuit comprises a plurality of capacitors connected to each other via a seventh transistor Connected to the power supply voltage, the seventh transistor is turned on according to the second comparison signal. The electronic device of claim 1, wherein the second clamping circuit comprises a plurality of capacitors connected in series to the power supply voltage via an eighth transistor, the eighth transistor being in accordance with the second Compare the signal and turn it on. The electronic device according to claim 1, wherein the first clamp circuit divides the power supply voltage by a voltage dividing action of 2 to generate the first divided voltage. The electronic device of claim 1, wherein the second clamping circuit divides the power supply voltage by a voltage dividing action of two to generate the second divided voltage.