JP2012160928A - Load drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a load drive circuit that puts a current limitation suitable for a load characteristic by allowing a current limitation characteristic to follow a plurality of supply voltage conditions.SOLUTION: The load drive circuit shown in the figure includes an output MOS transistor connected to a power supply and a load, and a current limit value changeover circuit for limiting an output current flowing through the output MOS transistor to a plurality of levels of limit current in accordance with an output voltage of the output MOS transistor, and changing the output voltage at a limit current changeover in accordance with a change in a supply voltage. A resultant stepwise current limitation prevents an excessive current limitation to increase a load condition. The current limit value changeover further responds to the supply voltage, so that even if the supply voltage is different from an initial supply voltage condition, the current limitation characteristic can follow the supply voltage fluctuation to put a current limitation suitable for a load characteristic as a whole.

Description

  The present invention relates to a load driving circuit. In particular, the present invention relates to a load driving circuit having an overcurrent protection function for an output transistor that functions as a high-side switch.

  In a load driving circuit, a transistor is often used as a high-side switch. Here, Patent Document 1 discloses a drive circuit that prevents an overcurrent from flowing through an output transistor due to a short circuit of a load and a thermal breakdown of the output transistor by limiting the current flowing through the output transistor. ing.

  However, in the load driving circuit disclosed in Patent Document 1, since the current limit value is fixed to a single value, the current limit value is excessive in the low voltage region and cannot be applied to a wide load condition. Therefore, Patent Document 2 discloses a circuit that expands applicable load conditions by changing the current limit value according to the output voltage without fixing the current limit value to a single value.

JP-A-5-235365 JP 2004-80346 A

  The following analysis has been made from the viewpoint of the present invention.

  The power of the load driving circuit having the current limiting characteristic disclosed in Patent Document 2 in two stages will be examined. In a load drive circuit with two stages of current limit characteristics, if the maximum current limit value is changed by two equal parts at the voltage point that divides the power supply voltage into two equal parts, both the high and low voltage regions are almost equal. Maximum limit power can be obtained.

  FIG. 2 is a diagram showing current-voltage characteristics in a load driving circuit that performs two-stage current limiting. For example, as shown in FIG. 2, when the current of the load drive circuit is limited to ILimit1 (maximum current limit) and ILimit2, ILimit1 and ILimit2 are set to switch at Va, which is a voltage point ½ of the power supply voltage Vcc. To do. At the same time, the ratio of the currents ILimit1 and ILimit2 is set to 1: 1.

  The power is calculated by applying specific numbers to the above voltage and current. Here, Vcc = 12V, Va = 6V, ILimit1 = 2A, and ILimit2 = 1. The power in the region smaller than Va (the low voltage region in FIG. 2) can be calculated as 6V × 2A = 12 W, and the power in the region above Va and not higher than Vcc (the high voltage region in FIG. 2) can be calculated as 12 V × 1A = 12 W. .

  However, even if the maximum current limit value (ILimit1) and the switching voltage point (Va) are set in consideration of the balance of the maximum limit power as described above, the load driving circuit is used under a power supply voltage condition different from the original design. In this case, there is a problem that an appropriate relationship (a balanced state) between the load characteristic and the current limiting characteristic is lost (detailed description will be described later). That is, the load drive circuit disclosed in Patent Document 2 does not consider the followability of the current limiting characteristic with respect to a plurality of power supply voltage conditions.

  As described above, there are problems to be solved in the prior art.

  In one aspect of the present invention, a load driving circuit is desired in which a current limiting characteristic follows a plurality of power supply voltage conditions and performs a current limiting suitable for the load characteristic.

  According to the first aspect of the present invention, an output MOS transistor connected to a power source and a load, and an output current flowing through the output MOS transistor is limited to a plurality of stages of limited currents according to an output voltage of the output MOS transistor. In addition, a load drive circuit is provided that includes a current limit value switching circuit that switches an output voltage when the limit current is switched based on a change in power supply voltage.

  According to an aspect of the present invention, a load driving circuit is provided in which current limiting characteristics follow a plurality of power supply voltage conditions and current limiting suitable for load characteristics is performed.

It is a figure for demonstrating the outline | summary of this invention. It is a figure which shows an example of the current-voltage characteristic in the load drive circuit which performs an electric current limitation. It is a figure which shows the structure of the conventional load drive circuit. It is a figure which shows the relationship between the drain voltage of the output MOS transistor of FIG. 3, and output current. FIG. 5 is a diagram in which a current limit value is superimposed on FIG. 4. It is a figure which shows the structure of the conventional load drive circuit. FIG. 7 is a diagram in which the on / off states of the MOS transistors in FIG. 6 are shown in accordance with the output voltage range. FIG. 7 is a diagram in which the on / off states of the MOS transistors in FIG. 6 are shown in accordance with the output voltage range. FIG. 7 is a diagram in which the on / off states of the MOS transistors in FIG. 6 are shown in accordance with the output voltage range. 7 is a timing chart showing a relationship between an input voltage and an output voltage of the load driving circuit shown in FIG. 6. It is a figure which shows the relationship between the load characteristic and current limiting characteristic of the load drive circuit shown in FIG. It is a figure which shows the current-voltage characteristic at the time of dividing | segmenting the ratio of a power supply voltage and a maximum current limiting value equally. It is a figure which shows the current-voltage characteristic when the ratio of a power supply voltage and a maximum current limiting value is set to 1: 2. It is a figure which shows the current-voltage characteristic when the ratio of a power supply voltage and a maximum current limiting value is set to 2: 1. It is a figure which shows the current-voltage characteristic at the time of changing a power supply voltage in the load drive circuit which divided | segmented the ratio of a power supply voltage and the maximum current limiting value equally. It is a figure which shows an example of a structure of the load drive circuit of the 1st Embodiment of this invention. FIG. 17 is a diagram in which the on / off states of the MOS transistors in FIG. 16 are shown together according to the range of the output voltage. FIG. 17 is a diagram in which the on / off states of the MOS transistors in FIG. 16 are shown together according to the range of the output voltage. FIG. 17 is a diagram in which the on / off states of the MOS transistors in FIG. 16 are shown in accordance with the range of output voltages. It is a timing chart which shows the relationship between the input voltage and output voltage of the load drive circuit shown in FIG. FIG. 17 is a current-voltage characteristic diagram illustrating a relationship between load characteristics and current limiting characteristics of the load driving circuit illustrated in FIG. 16. FIG. 22 is a current-voltage characteristic diagram when the power supply voltage is changed from the driving conditions in FIG. 21.

  First, the outline of the embodiment will be described with reference to FIG. Note that the reference numerals of the drawings attached to this summary are attached to the respective elements for convenience as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

  As described above, even if the maximum current limit value and switching voltage point are set in consideration of the balance between the maximum limit power and the load drive circuit is used under a voltage condition different from the assumed power supply voltage, the load characteristics and current limit The proper relationship with the characteristics will be lost. Therefore, there is a need for a load driving circuit in which the current limiting characteristic follows a plurality of power supply voltage conditions and performs current limiting suitable for the load characteristic as a whole.

  Therefore, the load driving circuit shown in FIG. 1 is provided. The load driving circuit shown in FIG. 1 limits the output current flowing through the output MOS transistor to a plurality of stages of limiting currents according to the output MOS transistors connected to the power source and the load, and the output voltage of the output MOS transistors. A current limit value switching circuit that switches an output voltage when the current is switched based on a change in the power supply voltage.

  Since the load driving circuit shown in FIG. 1 performs current limitation step by step using a plurality of different current limit values, it is possible to prevent excessive current limitation and to expand load conditions. Furthermore, since the current limit value is switched according to the power supply voltage, even if it is used at a power supply voltage different from the original power supply voltage condition, the current limit characteristics follow the fluctuation of the power supply voltage and are suitable for the load characteristics. Current limiting can be performed.

  As a result, even if a load drive circuit designed based on a specific power supply voltage is used at a power supply voltage different from the original design, it is not necessary to design and evaluate the load drive circuit again. If it is not necessary to perform design and evaluation, the versatility of the load drive circuit is enhanced and the design cost of the load drive circuit can be reduced.

  Next, the load drive circuit disclosed in Patent Document 1 will be described with reference to FIG. The load driving circuit 10 shown in FIG. 3 includes a power supply terminal Pin, an input terminal In, and an output terminal Out, and is configured by MOS transistors M1 to M3 and resistors R1 and R2. Further, the charge pump circuit CP is connected to the input terminal In, the power supply terminal Pin is connected to the power supply, and the output terminal Out is connected to a grounded external load LD. In the following description, the MOS transistor represents an n-channel MOS transistor.

  The MOS transistor M1 is an output transistor, and the MOS transistor M2 is a current detection transistor. The output current is Id, and the current flowing through the current detection MOS transistor M2 is the sense current Is. The voltage Vd is the drain-source voltage of the output MOS transistor M1, Vs is the sense voltage (the voltage across the resistor R2), Vin is the input voltage, Vcc is the power supply voltage, and Vout is the output voltage.

  As shown in FIG. 3, the output MOS transistor M1 functions as a high-side switch for the load LD, the drain is connected to the power supply terminal Pin, and the source is connected to the load LD. The gate of the output MOS transistor M1 is connected to the charge pump circuit CP via the resistor R1.

  In the load drive circuit 10, an overcurrent protection circuit is configured by the current detection MOS transistor M2, the MOS transistor M3, and the resistor R2. The gate of the current detection MOS transistor M2 is connected to the gate of the output MOS transistor M1, and the drain of the current detection MOS transistor M2 is connected to the drain of the output MOS transistor M1. The source of the current detection MOS transistor M2 is commonly connected to the gate of the MOS transistor M3 and the resistor R2. The gate of the MOS transistor M3 is connected to the source of the current detection MOS transistor M2 and the resistor R2, the drain is commonly connected to the gates of the output MOS transistor M1 and the current detection MOS transistor M2, and the source is connected to the resistor R2. It is connected to the output terminal Out (load LD).

  The output current Id and the sense current Is have a current ratio corresponding to the cell size ratio of the output MOS transistor M1 and the current detection MOS transistor M2. By using the current detection MOS transistor M2, the output current Id can be detected with high accuracy. A resistor R2 connected between the source of the current detection MOS transistor M2 and the output terminal Out converts the sense current Is into a sense voltage Vs.

  When the sense voltage Vs becomes equal to or higher than the threshold voltage Vt3 of the MOS transistor M3, the MOS transistor M3 is turned on to lower the gate voltage of the output MOS transistor M1. In the following description, the threshold voltage of each transistor is expressed using a transistor code number. For example, the threshold voltage of the output MOS transistor M1 is expressed as Vt1.

  When the gate voltage of the output MOS transistor M1 decreases, the output current Id is limited. The operation at this time will be described with reference to FIG.

  FIG. 4 is a diagram showing the relationship between the drain voltage Vd (corresponding to Vcc−Vout) of the output MOS transistor M1 and the output current Id. In FIG. 4, the vertical axis represents the output current Id, and the horizontal axis represents the drain voltage Vd. In FIG. 4, k1 indicates a load characteristic.

  As can be seen from FIG. 4, the load characteristic k1 is a straight line having a negative gradient that intersects the horizontal axis and Vcc. The current-voltage characteristic of the output MOS transistor M1 corresponds to the basic transistor characteristic of the NMOS transistor, and the intersection point a between them is the operating point of the output MOS transistor M1. FIG. 5 is a diagram in which a current limit value (hereinafter referred to as Im) is superimposed on FIG. As shown in FIG. 5, in order to effectively use the current capability of the output MOS transistor M1, the current limit value Im is set so as not to cross the load characteristic k1.

  Here, if a short circuit of the load LD occurs, the sense current Is also increases in proportion to the increase in the output current Id. If the sense current Is increases, the sense voltage Vs also increases, and the sense voltage Vs eventually reaches the threshold voltage Vt3 of the MOS transistor M3. When the sense voltage Vs becomes equal to or higher than the threshold voltage Vt3 of the MOS transistor M3, the MOS transistor M3 is turned on, and the gate voltage of the output MOS transistor M1 decreases to a predetermined voltage (hereinafter referred to as Vgc). As a result, the output current Id is limited to the current limit value Im, and is protected from overcurrent.

  Next, the load drive circuit disclosed in Patent Document 2 will be described. FIG. 6 is a circuit diagram of the load driving circuit disclosed in FIG. The load drive circuit 20 includes a voltage detection circuit 21, a voltage clamp circuit 22, an output MOS transistor M4, and a resistor 12.

  The output MOS transistor M4 of the load driving circuit 20 operates as a low side switch, and the output terminal Out is connected to the load LD. Inputs to the load drive circuit 20 are received by input terminals InP and InN, and the load drive circuit 20 is grounded via a Gnd terminal.

  In the load drive circuit 20, the current limit value can be switched between two levels by changing the clamp voltage according to the level of the output voltage Vout. As a result, the load driving circuit 20 relaxes excessive restrictions due to current limitation, and can be applied to a wider range of load conditions.

  In the load drive circuit 20, the voltage detection circuit 21 and the voltage clamp circuit 22 constitute an overcurrent protection circuit. The voltage detection circuit 21 is connected between the output terminal Out and the ground terminal Gnd, and detects a voltage applied to the output MOS transistor M4. The voltage clamp circuit 22 is connected between the gate of the output MOS transistor M4 and the ground terminal Gnd, and generates two different clamp voltages. An output of the voltage clamp circuit 22 (a connection point between the gate of the output MOS transistor M4 and the resistor R3) is a node S1. Further, the voltage detection circuit 21 includes MOS transistors M5 to M9 and resistors R6 to R11, and the voltage clamp circuit 22 includes MOS transistor M10 and resistors R3 to R5. The resistance values of the resistors R3 to R12 are expressed as r3 to r12, respectively, and the following description will be given.

  Next, the operation of the load driving circuit 20 will be described. 7 to 9 are diagrams in which the on / off states of the MOS transistors of the load driving circuit 20 are shown in accordance with the range of the output voltage. FIG. 10 is a timing chart showing the relationship between the input voltage and the output voltage, and FIG. 11 is a current-voltage characteristic diagram showing the relationship between the load characteristic and the current limiting characteristic. The operation of the load driving circuit 20 will be described with reference to these drawings.

  As shown in FIG. 10, until time t1, the input voltage Vin is at the L level, and the output MOS transistor M4 is in the off state. Therefore, the output current Id does not flow, and the output voltage Vout becomes the power supply voltage Vcc.

式（１）で表せる電圧がＭＯＳトランジスタＭ５の閾値電圧Ｖｔ５以上になるとＭＯＳトランジスタＭ５はオン状態になる。このＭＯＳトランジスタＭ５がオン状態になる時の出力電圧ＶｏｕｔをＶＭ１とすると、ＶｏｕｔがＶＭ１以上の範囲（Ｖｏｕｔ≧ＶＭ１）では、ＭＯＳトランジスタＭ５はオン状態、ＭＯＳトランジスタＭ６はオフ状態、ＭＯＳトランジスタＭ７はオン状態となる。すると、ＭＯＳトランジスタＭ１０はオン状態となり、電圧クランプ回路２２が活性化する。 Next, when the input signal Vin transitions to the H level at time t1, the output MOS transistor M4 starts to conduct. At that time, the voltage of the formula (1) is applied to the gate of the MOS transistor M5.

When the voltage expressed by equation (1) becomes equal to or higher than the threshold voltage Vt5 of the MOS transistor M5, the MOS transistor M5 is turned on. Assuming that the output voltage Vout when the MOS transistor M5 is turned on is VM1, the MOS transistor M5 is turned on, the MOS transistor M6 is turned off, and the MOS transistor M7 is turned on in a range where Vout is equal to or higher than VM1 (Vout ≧ VM1). Turns on. Then, the MOS transistor M10 is turned on, and the voltage clamp circuit 22 is activated.

式（２）で表せる電圧がＭＯＳトランジスタＭ８の閾値電圧Ｖｔ８以上になるとＭＯＳトランジスタＭ８はオン状態になる。このＭＯＳトランジスタＭ８がオン状態になる時の出力電圧ＶｏｕｔをＶＭ２とすると、ＶｏｕｔがＶＭ２以上の範囲（Ｖｏｕｔ≧ＶＭ２）では、ＭＯＳトランジスタＭ８はオン状態になる（図７参照）。すると、ＭＯＳトランジスタＭ９はオフ状態になる。なお、図１０のｔ１≦ｔ≦ｔ２の範囲が図７の状態に相当する。 On the other hand, a voltage expressed by equation (2) is applied to the gate of the MOS transistor M8.

When the voltage expressed by equation (2) becomes equal to or higher than the threshold voltage Vt8 of the MOS transistor M8, the MOS transistor M8 is turned on. When the output voltage Vout when the MOS transistor M8 is turned on is VM2, the MOS transistor M8 is turned on in a range where Vout is equal to or higher than VM2 (Vout ≧ VM2) (see FIG. 7). Then, the MOS transistor M9 is turned off. Note that the range of t1 ≦ t ≦ t2 in FIG. 10 corresponds to the state of FIG.

従って、出力電流Ｉｄは出力ＭＯＳトランジスタＭ４のゲート電圧（ＶＧＳ１）により定まるので、電流ＩＬに制限されることになる。 Here, VM1 is smaller than VM2 (VM1 <VM2), and the threshold voltage Vt5 and the threshold voltage Vt8 are equal. At this time, VGS1 that is the output voltage of the voltage clamp circuit 22 output from the node S1 is a voltage that can be expressed by Expression (3).

Therefore, since the output current Id is determined by the gate voltage (VGS1) of the output MOS transistor M4, it is limited to the current IL.

従って、出力電流ＩｄはＶＧＳ２で決定される電流制限値ＩＨに制限される。その結果、電流制限特性は、図１１に示すように、出力電圧Ｖｏｕｔの大きさに応じて変化する２段階の電流制限値となる（ＩＬ＜ＩＨ）。なお、図１０のｔ２＜ｔ≦ｔ３の範囲が図８の状態に相当する。 Further, when the output current Id increases, the output voltage Vout decreases, and when the output voltage Vout falls within the range of VM1 ≦ Vout <VM2, as shown in FIG. 8, the MOS transistor M8 is turned off, and the MOS transistor M9 Is turned on, and the resistor R5 is avoided (shunted). At this time, the output voltage VGS2 of the voltage clamp circuit 22 is a voltage expressed by Expression (4). Note that VGS2> VGS1.

Therefore, the output current Id is limited to the current limit value IH determined by VGS2. As a result, as shown in FIG. 11, the current limiting characteristic becomes a two-stage current limiting value that varies depending on the magnitude of the output voltage Vout (IL <IH). Note that the range of t2 <t ≦ t3 in FIG. 10 corresponds to the state of FIG.

ここで、抵抗値ｒ３、ｒ４、ｒ１２は式（５）で表せる電圧値がほぼＶｉｎと等しくなるように設定される。すると、出力ＭＯＳトランジスタＭ４のゲートには、ほぼ入力電圧Ｖｉｎに等しい電圧が印加されるので、出力電圧Ｖｏｕｔは、負荷ＬＤの抵抗値ｒＬと出力ＭＯＳトランジスタＭ４の内部抵抗値ｒｍ４で決まる動作点Ｂ（Ｖｂ、Ｉｂ）に遷移する。なお、図１０のｔ３＜ｔ≦ｔ４の範囲が図９の状態に相当する。 Further, when the output current Id increases, the output voltage Vout decreases, and when the output voltage Vout becomes Vout <VM1, the MOS transistor M5 is turned off, the MOS transistor M6 is turned on, as shown in FIG. M7 is turned off. Accordingly, the MOS transistor M10 is turned off, and the voltage clamp circuit 22 is inactivated. When the voltage clamp circuit 22 becomes inactive, the voltage represented by the equation (5) is applied to the gate of the output MOS transistor M4.

Here, the resistance values r3, r4, r12 are set so that the voltage value expressed by the equation (5) is substantially equal to Vin. Then, since a voltage substantially equal to the input voltage Vin is applied to the gate of the output MOS transistor M4, the output voltage Vout is an operating point B determined by the resistance value rL of the load LD and the internal resistance value rm4 of the output MOS transistor M4. Transition to (Vb, Ib). Note that the range of t3 <t ≦ t4 in FIG. 10 corresponds to the state of FIG.

  Thereafter, when the load LD is short-circuited, the output voltage Vout becomes substantially equal to the power supply voltage Vcc. As a result, the voltage detection circuit 21 activates the current limit by turning on the MOS transistor M7, and turns off the MOS transistor M9 to bias the gate voltage of the output MOS transistor M4 to VGS1.

  As described above, when the load is short-circuited, the output current Id flowing through the output MOS transistor M4 is limited to the current limit value IL to protect the output MOS transistor M4 from thermal destruction. In the load driving circuit 20, in a region where Vout is greater than or equal to VM2 (Vout ≧ VM2; high voltage region), the current limit value IL is decreased to suppress power generated when the load is short-circuited, and a region where Vout is smaller than VM2 (Vout <VM2 In the low voltage region), the current limit value IH is relatively increased to relax the excessive current limit. In this way, the load condition is expanded.

  Note that k2 in FIG. 11 is a load characteristic in the load drive circuit 20, and applicable load conditions are expanded as compared with the load characteristic k3 in the case of a single current limit value IL. As described above, in the load driving circuit 20 disclosed in Patent Document 2, the current limit value is changed in two stages according to the output voltage Vout, so that the load condition can be expanded. As a result, in the load drive circuit 10 disclosed in Patent Document 1, since the current limit value Im is fixed to a single value, the current limit value becomes excessive (more than necessary) in the low voltage region, and cannot be applied to a wide load condition. Solve the problem.

  As disclosed in Patent Document 2, when the current limiting characteristic is set in two stages in order to widen the load characteristic, only the current value obtained by dividing the maximum current limiting value into two at the voltage point obtained by dividing the power supply voltage into two equal parts. If it is changed, it is possible to obtain a substantially uniform maximum limiting power in both the high and low voltage regions.

  FIG. 12 is a diagram showing current-voltage characteristics when the power supply voltage Vcc and the maximum current limit value IH are each equally divided into 1: 1. FIG. 13 is a diagram showing current-voltage characteristics when the power supply voltage Vcc division ratio is 1: 2 and the maximum current limit value IH is 2: 1. FIG. 14 is a diagram showing current-voltage characteristics when the power supply voltage Vcc division ratio is 2: 1 and the maximum current limit value IH division ratio is 1: 2. Since VM1 is an extremely small voltage, the following description will be given without considering the area below VM1.

  As shown in FIG. 12, Vcc = 12V, VM2 = 6V, IL = 1A, IH = 2A, and the maximum limit power (maximum voltage value × current limit value) in the high voltage region is 12 W (12V × 1A). Become. On the other hand, the maximum limit power in the low voltage region is 12 W (6 V × 2 A), and uniform maximum limit power can be obtained in both the high and low voltage regions.

  Next, in the division example shown in FIG. 13, VM2 = 4V, IL = 1.3A, IH = 2A, and the maximum limit power in the high voltage region is 15.6 W (12V × 1.3A), the low voltage region The maximum power limit is 8 W (4 V × 2 A), and the maximum power limit in both voltage regions is in an unbalanced state.

  Furthermore, in the division example shown in FIG. 14, VM2 = 8V, IL = 0.7A, IH = 2A, and the maximum limit power in the high voltage region is 8.4 W (12V × 0.7A), and in the low voltage region The maximum limit power is 16 W (= 8 V × 2 A), and the maximum limit power in both voltage regions is also in an unbalanced state.

  Thus, when switching the current limit value in two stages, if VM2 is set to a voltage point obtained by dividing the power supply voltage into two equal parts and IL is set to a current value obtained by dividing the maximum current limit value IH into two equal parts, the balance The maximum power limit can be obtained, and the current limit suitable for the load characteristics can be performed as the entire load driving circuit.

  However, as described above, even if the maximum current limit value IH and the switching voltage point (VM2) are set in consideration of the balance of the maximum limit power, the load drive circuit is used under a power supply voltage condition different from the original design. In this case, an appropriate relationship (a balanced state) between the load characteristic and the current limiting characteristic is lost.

  This will be described more specifically with reference to FIG. FIG. 15 is a diagram showing current-voltage characteristics when a load driving circuit designed with a division ratio of 1: 1 is changed from a power supply voltage assumed at the time of design. FIG. 15 shows an example in which a circuit designed with Vcc = 12V, IL = 1A, IH = 2A, VM2 = 6V (division ratio 1: 1) is used as a power supply with a power supply voltage Vcc = 10V.

  As shown in FIG. 15, when the power supply voltage Vcc changes, the load characteristics change accordingly (k2 → k4). As a result, the relative position of VM2 with respect to the power supply voltage Vcc changes (division ratio 1: 1 → 3: 2), and an appropriate relationship between the load characteristic and the current limiting characteristic is lost. Then, the maximum limit power in both the high and low voltage regions is in an unbalanced state, and the current limit suitable for the load characteristics as a whole cannot be performed. The load drive circuit 20 disclosed in Patent Document 2 means that no consideration is given to the followability of the current limiting characteristic with respect to a plurality of power supply voltage conditions. That is, in the load driving circuit 20 disclosed in Patent Document 2, it can be said that the load characteristic and the current limiting characteristic are independent of each other.

[First Embodiment]
Next, the first embodiment of the present invention will be described in more detail with reference to the drawings. FIG. 16 is an example showing the configuration of the load driving circuit 30 according to the first embodiment. In FIG. 16, the same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted.

  The difference between the load drive circuit 10 and the load drive circuit 30 shown in FIG. 3 is that the load drive circuit 30 includes a current limit value switching circuit 31. The current limit value switching circuit 31 includes MOS transistors M11 and M12 and resistors R13 and R14. The current limit value switching circuit 31 conducts between the output MOS transistor M1 and the output terminal Out, and has a role as a current path different from the path through which the output current Id flows. Further, it has a role of switching between two different current limit values according to the power supply voltage Vcc (the voltage between the power supply voltage Vcc and the ground). It is assumed that the threshold voltages of the MOS transistors M3 and M11 have the same voltage value, and the on-resistance and threshold voltage Vt12 of the MOS transistor M12 that functions as a switch can be ignored.

  The resistance value ratio of the resistors R13 and R14 is 1: 1, and the limiting current value is changed by 1/2 of the maximum current limiting value at a voltage point of 1/2 of the power supply voltage Vcc. The resistors R13 and R14 are connected in series between the power supply terminal Pin and the ground. The drain of the MOS transistor M11 is connected to the source of the MOS transistor M12, the source is connected to the output terminal Out, and the gate is connected to the gate of the MOS transistor M3. The drain of the MOS transistor M12 is connected to the gate of the output MOS transistor M1, the source is connected to the drain of the MOS transistor M11, and the gate is connected to the connection point of the resistors R13 and R14. A connection point between the gate of the output MOS transistor M1 and the drains of the MOS transistors M3 and M12 is defined as a node S2.

  Next, the operation of the load driving circuit 30 will be described. In the load driving circuit 30, the voltage across the resistor R2 increases as the sense current Is increases, and the MOS transistor M3 is turned on. As a result, a first current path is formed between the gate of the output MOS transistor M1 and the output terminal Out via the MOS transistor M3 in the on state. At that time, the MOS transistor M11 is also turned on.

  Further, when the MOS transistor M11 is in the ON state simultaneously with the MOS transistor M3, the MOS transistor M12 has a voltage difference between the divided voltage of the power supply voltage Vcc and the output voltage Vout equal to or higher than the threshold voltage Vt12 of the MOS transistor M12. The transistor M12 is turned on. As a result, a second current path is formed through the MOS transistors M11 and M12 in the on state in parallel with the first current path. In this way, two different current limit values can be generated.

  17 to 19 are diagrams in which the on / off states of the MOS transistors shown in FIG. 16 are shown in accordance with the output voltage range. FIG. 20 is a timing chart showing the relationship between the input voltage and the output voltage, and FIG. 21 is a current-voltage characteristic diagram showing the relationship between the load characteristic and the current limiting characteristic. Note that the on-resistance of each MOS transistor is expressed using the code number of the MOS transistor, and the following description will be given. For example, the on-resistance of the output MOS transistor M1 is expressed as rm1. The MOS transistor M12 operates as a switch, and the threshold voltage Vt12 and the on-resistance rm12 can be ignored.

  As shown in FIG. 20, when the input voltage is at the L level, the output MOS transistor M1 is in an off state and no current flows. Therefore, the output voltage Vout becomes the ground voltage (0 V), and Vcc−Vout = Vcc.

式（６）表せる電圧がＭＯＳトランジスタＭ３及びＭ１１の閾値電圧Ｖｔ３及びＶｔ１１以上となると、ＭＯＳトランジスタＭ３及びＭ１１は同時にオン状態となる。つまり、このときの式（６）が表す電圧（Ｖｃｃ−Ｖｏｕｔ）をＶＮ１とすると、Ｖｃｃ−Ｖｏｕｔ≧ＶＮ１の範囲内ではＭＯＳトランジスタＭ３及びＭ１１はオン状態である。 Next, when the input signal Vin transitions to H level at time t5, the output MOS transistor M1 starts to conduct. A voltage expressed by Expression (6) is applied to the gate of the MOS transistor M3.

When the voltage expressed by equation (6) becomes equal to or higher than the threshold voltages Vt3 and Vt11 of the MOS transistors M3 and M11, the MOS transistors M3 and M11 are simultaneously turned on. That is, assuming that the voltage (Vcc−Vout) represented by Equation (6) at this time is VN1, the MOS transistors M3 and M11 are in the on state within the range of Vcc−Vout ≧ VN1.

この式（７）で表せる電圧と出力電圧Ｖｏｕｔの電圧差がＭＯＳトランジスタＭ１２の閾値電圧Ｖｔ１２以上になるとＭＯＳトランジスタＭ１２はオン状態になる。このときの電圧（Ｖｃｃ−Ｖｏｕｔ）をＶＮ２とする。なお、負荷駆動回路３０は、ＶＮ１＜ＶＮ２となるように設計する。図１７（図２０のｔ５≦ｔ≦ｔ６の範囲時に相当）に示すように、（Ｖｃｃ−Ｖｏｕｔ）≧ＶＮ２の範囲内では、ＭＯＳトランジスタＭ３、Ｍ１１及びＭ１２は全てオン状態になる。 On the other hand, a voltage expressed by Expression (7) is applied to the gate of the MOS transistor M12.

When the voltage difference between the voltage expressed by the equation (7) and the output voltage Vout becomes equal to or higher than the threshold voltage Vt12 of the MOS transistor M12, the MOS transistor M12 is turned on. The voltage (Vcc−Vout) at this time is VN2. The load driving circuit 30 is designed so that VN1 <VN2. As shown in FIG. 17 (corresponding to the range of t5 ≦ t ≦ t6 in FIG. 20), within the range of (Vcc−Vout) ≧ VN2, the MOS transistors M3, M11, and M12 are all turned on.

  Therefore, between the gate of the output MOS transistor M1 and the output terminal Out, a first current path passing through the on-state MOS transistor M3 and a second current path passing through the on-state MOS transistors M11 and M12 are parallel. The gate voltage of the MOS transistor M1 (the voltage at the node S2) is determined. The voltage at this time is Vg2. As a result, the output current Id is limited to a current value I2 determined by the voltage Vg2.

なお、ｒｍｔ＝ｒｍ３×ｒｍ１１／（ｒｍ３＋ｒｍ１１）である。 Here, if the ratio of the resistance values of the resistors R13 and R14 is 1: 1, and the threshold voltage Vt12 of the MOS transistor M12 is an extremely small value and can be ignored, VN2 has a voltage value of approximately 1/2 of Vcc. . Further, the gate voltage Vg2 is a voltage that can be expressed by Expression (8).

Note that rmt = rm3 × rm11 / (rm3 + rm11).

  Further, the output current Id increases and the voltage (Vcc−Vout) decreases, and in the range of VN1 ≦ (Vcc−Vout) <VN2, it is shown in FIG. 18 (corresponding to the range of t6 <t ≦ t7 in FIG. 20). Thus, the MOS transistors M3 and M11 are turned on, and the MOS transistor M12 is turned off.

式（８）及び（９）から、Ｖｇ２＜Ｖｇ１であることが分かり、電流Ｉ２＜Ｉ１となる。 As a result, the second current path is cut off between the gate of the output MOS transistor M1 and the output terminal Out, and only the first current path passing through the on-state MOS transistor M3 is conducted, and the gate of the output MOS transistor M1 The voltage is determined. The voltage at this time is Vg1. As a result, the output current Id is limited to the current value I1 determined by the gate voltage Vg1. The gate voltage Vg1 is a voltage that can be expressed by the equation (9).

From equations (8) and (9), it can be seen that Vg2 <Vg1, and the current I2 <I1.

  Further, as the output current Id increases, the voltage (Vcc−Vout) decreases. As shown in FIG. 19 (corresponding to the range of t7 <t ≦ t8 in FIG. 20) within the range of (Vcc−Vout) <VN1. Thus, the MOS transistors M3, M11, and M12 are all turned off. Then, the input voltage Vin is applied to the gate of the output MOS transistor M1, and a transition is made to an operating point B (Vb, Ib) determined by the resistance value rL of the load LD and the internal resistance value rm1 of the output MOS transistor M1.

  Thereafter, when the load LD is short-circuited, the voltage (Vcc−Vout) becomes substantially equal to the power supply voltage Vcc, and the MOS transistors M3, M11, and M12 are all turned on, so that the gate voltage of the output MOS transistor M1 is set to Vg2. Bias. In this way, when the load is short-circuited, the output current Id flowing through the output MOS transistor M1 is limited to the current limit value I2 to protect the output MOS transistor M1 from thermal destruction.

  An example of the current-voltage characteristic of the load drive circuit 30 is shown in FIGS. FIG. 21 shows the current when I1 = 2A, I2 = 1A (division ratio of maximum current limit value 1: 1), VN2 = 6V (division ratio of power supply voltage 1: 1) and the power supply voltage is used at 12V. -It is a voltage characteristic figure. FIG. 22 is a current-voltage characteristic diagram when the power supply voltage is changed to 10 V from the condition of FIG.

  As shown in FIG. 21, when used with a 12V power supply, the output current Id is limited to the limiting current I2 (1A) in the high voltage region of (Vcc−Vout) ≧ VN2 (6V). On the other hand, in the low voltage region where (Vcc−Vout) <VN2, the output current Id is limited to the limiting current I1 (2A). Therefore, the maximum limit power in the high voltage region is 12 W (12 V × 1 A). On the other hand, the maximum limit power in the low voltage region is 12 W (6 V × 2 A), and uniform maximum limit power is obtained in both the high and low voltage regions.

  Next, when the load driving circuit 30 is used at a power supply voltage of 10 V, the load characteristic changes from k2 to k5. In such a case, in the load driving circuit 20, the proper relationship between the load characteristic and the current limiting characteristic is lost, the division ratio of Vcc by VM2 changes, and the maximum limiting power in both the high and low voltage regions is unbalanced. It becomes. However, in the load drive circuit 30, as shown in FIG. 22, VN2 changes following the change of Vcc while keeping the division ratio of Vcc by VN2 constant. For example, in the example of FIG. 22, the voltage of VN2 changes from 6V to 5V.

  For this reason, the maximum power limit in the high voltage region is 10 W (= 10 V × 1 A), and the maximum power limit in the low voltage region is 10 W (= 5 V × 2 A). Electric power can be obtained.

  In the description of the present embodiment, the case where the resistance value ratio of the resistors R13 and R14 is set to 1: 1 and the current limit value is changed at a voltage point of 1/2 of Vcc has been described. By setting the ratio appropriately, the current limit value can be switched at an arbitrary voltage point. Furthermore, in the description of the present embodiment, the circuit configuration has been described in which the current limit value is variable in two stages. However, a voltage dividing circuit that generates two or more divided voltages and a switch MOS transistor are further provided to increase the switching circuit. By doing so, it is possible to limit the current in a plurality of stages in which a plurality of switching voltage points vary according to the power supply voltage.

  As described above, in the load driving circuit 30, two different current limit values are switched to enable stepwise current limit. Therefore, excessive current limitation is not achieved in the low voltage region, and the range of load conditions is expanded. At the same time, the switching voltage point of the current limit value changes according to the power supply voltage while maintaining the power supply voltage division ratio, so that the current limit characteristics change following the use of different power supply voltage conditions. As a result, current limitation suitable for the load characteristics can be performed. In addition, when the current limit is performed in two stages, if the limit current value is changed by a half of the maximum current limit value at a voltage point that is 1/2 of the power supply voltage, it is even in both the high and low voltage regions. Maximum limit power can be obtained. Moreover, the switching voltage point of the current limit value can be set to an arbitrary voltage by changing the resistance value ratio of the voltage dividing resistor.

  It should be noted that the disclosures of the above patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea. For example, in the description of the embodiment, an n-channel MOS transistor is used on the assumption that a positive power supply is used. However, when a negative power supply is used, a p-channel MOS transistor can be used.

10, 20, 30 Load drive circuit 21 Voltage detection circuit 22 Voltage clamp circuit 31 Current limit value switching circuit LD Load M1 to M12 MOS transistors R1 to R14 Resistance CP Charge pump circuit

Claims (6)

An output MOS transistor connected to a power source and a load;
Current limiting that limits the output current flowing through the output MOS transistor to a plurality of stages of limiting current according to the output voltage of the output MOS transistor and that switches the output voltage when the limiting current is switched based on a change in power supply voltage A value switching circuit;
A load driving circuit comprising:   2. The load driving circuit according to claim 1, wherein a drain of the output MOS transistor is connected to a power source, a source is connected to a load, and the output MOS transistor is operated as a high side switch. Furthermore, a current detection MOS transistor for measuring an output current flowing through the output MOS transistor;
A first MOS transistor that varies a gate voltage of the output MOS transistor based on a current flowing through the current detection MOS transistor;
A load driving circuit according to claim 1 or 2. The current limit value switching circuit is:
A first resistor and a second resistor for generating a divided voltage from the power supply voltage;
A second MOS transistor that varies a gate voltage of the output MOS transistor based on a voltage difference between the divided voltage and the output voltage;
With
4. The load driving circuit according to claim 3, wherein the first MOS transistor conducts in correspondence with the second MOS transistor.   The current limit value switching circuit limits the output current to a first limit current and a second limit current that is larger than the first limit current, and the first limit current and the second limit current are 5. The load according to claim 1, wherein the voltage at the time of switching is approximately one half of the power supply voltage, and the second limited current value is approximately twice the first limited current value. 6. Driving circuit.   The load drive circuit according to claim 5, wherein resistance values of the first resistor and the second resistor are substantially equal.

Images