TWI571972B - Electrode improving method and structure of random access memories - Google Patents

Description

Memory electrode improvement method and its structure

The present invention relates to a method for improving the electrode of a memory and a structure thereof; and more particularly to a method for eliminating the surface effect of a resistive memory (resistive RAM) and a structure thereof.

In general, conventional resistive memory is disclosed in many domestic and foreign patent materials, such as: RESISTIVE MEMORY STRUCTURE WITH BUFFER LAYER, which has a buffer layer, and a patent for invention. It is disclosed that a memory device includes a first electrode, a second electrode, a buffer layer and a memory element. The memory element and the buffer layer are interposed between the first electrode and the second electrode, and the memory element and the buffer layer are electrically coupled to the first electrode and the second electrode. The memory element comprises more than one metal oxygen compound. The buffer layer contains at least an oxide or a nitride.

The memory device of another embodiment of the above-mentioned No. I402980 includes a first electrode, a second electrode, a buffer layer and a memory element. The memory element and the buffer layer are interposed between the first electrode and the second electrode, and the memory element and the buffer layer are electrically coupled to the first electrode and the second electrode. The buffer layer has a thickness of less than 50 angstroms. However, the memory device only enhances the performance of the resistive memory device by providing the buffer layer.

Another conventional resistive memory, such as the Republic of China patent The invention discloses a non-volatile resistive memory (NONVOLATILE RESISTANCE MEMORY DEVICE), which discloses a non-volatile resistive memory comprising: a first electrode, a second electrode and an oxide layer. The second electrode is formed on the first electrode, and the oxide layer is sandwiched between the first electrode and the second electrode. The oxide layer has an electric field varistor characteristic and exhibits a columnar grain structure along a direction substantially perpendicular to its layer. The columnar grains are arranged in a particular preferred direction. The grain boundaries of the adjacent columnar grains can serve as a fast moving path for the oxygen vacancies in the oxide layer, thereby forming a conductive filament which is stable and can drive resistance conversion at a low voltage.

The resistive memory of the above-mentioned No. I425623 improves the characteristics of the resistive memory by using a resistor layer having a better quality. The resistive memory adopts a resistive layer having a columnar grain structure and a specific preferred crystallinity. By using a straight grain boundary between columnar grains, a path for driving the ions to move is provided, thereby forming a conductive wire path in which the directional tendency is uniform. However, since the resistive memory adopts a columnar grain structure and a resistive layer having a particularly preferable crystallinity, the resistive memory body has a disadvantage that the process difficulty is greatly improved.

Another conventional resistive memory is, for example, the Resistive memory device and method of fabricating the same, which discloses a resistive memory and a method of manufacturing the same. The resistive memory manufacturing method mainly uses an annealing process technology to improve the reliability of the resistive memory and shorten the processing time.

In short, the resistive memory of the aforementioned No. 8278138 is subjected to thermal annealing treatment to improve the reliability of the resistive memory. However, since the annealing process of the resistive memory causes a large heat accumulation, it necessarily has the disadvantage of consuming a large amount of energy cost and increasing the difficulty of process integration.

Another conventional resistive memory, for example, the structure and manufacturing method of the non-volatile memory and its charge storage layer of the Republic of China Patent Publication No. I268579 [STRUCTURE AND FABRICATING METHOD OF NON-VOLATILE MEMORY AND CHARGE STORAGE LAYER THEREOF] The invention patent also discloses a method for improving the stability of the resistive memory, which mainly utilizes a high-temperature thermal oxidation annealing process to precipitate a metal nano-point (for example, a nano-dots) to enhance the resistance layer. The electric field makes the conduction path in the resistance layer fixed, improving the problem of unstable switching of the resistive memory.

Similarly, the resistive memory of the aforementioned No. I268579 is subjected to thermal annealing treatment to improve the stability of the resistive memory. However, since the annealing process of the resistive memory causes a large heat accumulation, it also has the disadvantage of consuming a large amount of energy costs and increasing the difficulty of process integration. Further, in the resistive memory of the above-mentioned No. 1268579, the nano-dots are precipitated and the ruthenium-nitrogen compound layer is a ruthenium oxynitride layer. Therefore, it is inevitably disadvantageous in that the degree of difficulty in the process is increased.

Obviously, conventional resistive memories necessarily have the need to further provide other operational stability improvements (e.g., improved electrodes). The above-mentioned patents of the Republic of China Patent Publication No. I402980, No. I425623, No. I268579, and U.S. Patent No. 8278138 are only for reference to the technical background of the present invention, and are not intended to limit the scope of the present invention.

In view of the above, the present invention provides an electrode improvement method for a memory and a configuration thereof, which are surface-treated to cause a physical or chemical reaction of the conductive layer to eliminate surface effects thereof, and The surface defects of the conductive layer are reduced or the interface layer of the conductive layer is reduced to improve the technical disadvantage of the electrode characteristics of the conventional memory.

The main object of the preferred embodiment of the present invention is to provide a record An electrode improvement method and structure thereof, wherein a conductive layer is surface-treated to physically or chemically react the conductive layer to eliminate surface effects thereof, and reduce surface defects of the conductive layer or reduce interface of the conductive layer Layer to achieve the purpose of improving the operational stability of the resistive memory.

In order to achieve the above object, a method for improving an electrode of a memory according to a preferred embodiment of the present invention includes: providing a substrate, wherein the substrate comprises a lower conductive layer, and the lower conductive layer is formed on the substrate; and the lower conductive layer is surfaced Processing to form a surface-treated underlying conductive layer; forming a resistive layer on the lower conductive layer; and forming an upper conductive layer on the resistive layer; wherein the surface-treated underlying conductive layer eliminates surface effects and reduces The surface of the lower conductive layer is defective or the interface layer of the lower conductive layer is reduced.

In order to achieve the above object, another preferred embodiment of the present invention The method for improving the electrode of the memory comprises: providing a substrate, wherein the substrate comprises a lower conductive layer, a resistive layer and an upper conductive layer, wherein the lower conductive layer is formed on the substrate, and the resistive layer is formed on the lower conductive layer The upper conductive layer is formed on the resistive layer; and the upper conductive layer is surface-treated to form a surface-treated upper conductive layer; wherein the surface-treated upper conductive layer eliminates surface effects thereof and reduces the upper conductive layer Surface defects of the layer or reduction of the interface layer of the upper conductive layer.

The surface treatment of the preferred embodiment of the invention is a plasma surface treatment.

In the preferred embodiment of the present invention, the surface treatment of the plasma uses a reactive gas, and the reaction gas is selected from the group consisting of Ar, O ₂ , N ₂ , NH ₃ , CF ₄ , N ₂ O, H ₂ O, H ₂ , Cl _{2 .} Or any mixture of gases.

In the preferred embodiment of the present invention, the lower conductive layer or the upper conductive layer has a specific crystal arrangement direction, and the crystal arrangement direction includes (100), (200) or (110).

In a preferred embodiment of the present invention, after the lower conductive layer is formed on the substrate, the lower conductive layer is subjected to surface treatment.

In order to achieve the above object, a memory structure of a preferred embodiment of the present invention includes: a substrate; an insulating layer disposed on the substrate; a lower conductive layer disposed on the insulating layer; and a resistive layer disposed on the substrate On the lower conductive layer; and an upper conductive layer disposed on the resistive layer; wherein the lower conductive layer or the upper conductive layer is surface-treated to physically or chemically react the lower conductive layer or the upper conductive layer so that The surface effect is eliminated and the surface defects of the lower conductive layer or the upper conductive layer are reduced or the interface layer of the lower conductive layer or the upper conductive layer is reduced.

The surface treatment of the preferred embodiment of the invention is a plasma surface treatment.

In the preferred embodiment of the present invention, the surface treatment of the plasma uses a reactive gas, and the reaction gas is selected from the group consisting of Ar, O ₂ , N ₂ , NH ₃ , CF ₄ , N ₂ O, H ₂ O, H ₂ , Cl _{2 .} Or any mixture of gases.

In the preferred embodiment of the present invention, the lower conductive layer or the upper conductive layer has a specific crystal arrangement direction, and the crystal arrangement direction includes (100), (200) or (110).

110‧‧‧Resistive memory components

112‧‧‧Substrate

114‧‧‧Insulation

116‧‧‧lower conductive layer

118‧‧‧resistance layer

120‧‧‧Upper conductive layer

212‧‧‧Initial action

214‧‧‧Erasing action

216‧‧‧Write action

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412‧‧‧Write voltage of resistive memory without plasma surface treatment

414‧‧‧Waste voltage of resistive memory without plasma surface treatment

416‧‧‧Write voltage of resistive memory after plasma surface treatment

418‧‧‧Waste voltage of resistive memory after plasma surface treatment

512‧‧‧Resistive state of resistive memory without plasma surface treatment

514‧‧‧High resistance state of resistive memory without plasma surface treatment

516‧‧‧ Low resistance state of resistive memory after plasma surface treatment

518‧‧‧High resistance state of resistive memory after plasma surface treatment

Figure 1 is a cross-sectional view showing a memory structure of a preferred embodiment of the present invention Figure.

Fig. 2 is a view showing the relationship between voltage and current of the resistance switching characteristic of the memory of the preferred embodiment of the present invention.

Fig. 3 is a flow chart showing a method for improving the electrode of a memory according to a preferred embodiment of the present invention.

Fig. 4 is a view showing the operating voltage of the memory of the preferred embodiment of the present invention.

Fig. 5 is a view showing the state of resistance of the memory of the preferred embodiment of the present invention.

In order to fully understand the present invention, the preferred embodiments of the present invention are described in detail below, and are not intended to limit the invention.

In general, memory components can be generally divided into two categories, namely, volatile memory and non-volatile memory. At present, among various non-volatile memories, flash memory which can be quickly written and erased is particularly valued. However, as components continue to shrink, flash memory is also facing the dilemma of excessive write voltage, excessive write time, and too thin gates resulting in reduced memory time. Therefore, the newly developed non-volatile memory gradually replaces the flash memory, wherein the resistive memory element has short write erasing time, low operating voltage and current, long memory time, multi-state memory, simple structure, and simplified The advantages of writing and reading methods and small required area.

In view of the above, the method for improving the electrode of the memory of the preferred embodiment of the present invention and the structure thereof do not require a complicated process, and the electrode layer or the conductive layer in the resistive memory is surface-treated by various plasma treatment methods. The conductive layer is physically or chemically reacted to eliminate the surface effect, and the surface defect of the conductive layer is reduced or the interface layer of the conductive layer is reduced to achieve stable operation of the improved resistive memory. The purpose of sex.

In general, filament theory is one of the theories of the resistance switching mechanism of resistive memory. The filament theoretical mechanism mainly uses the writing and erasing actions to repeatedly form and break the current conductive path or the conductive path inside the resistive layer, thereby forming the resistive memory element into a low resistance state. LRS] and high resistance state (HRS) are used as the discrimination between 〝0〞 and 〝1〞 signals in the digital signal.

1 is a cross-sectional view of a memory structure in accordance with a preferred embodiment of the present invention, the construction of which includes five structural layers, but is not intended to limit the scope of the present invention. Referring to FIG. 1 , for example, the memory structure of the preferred embodiment of the present invention is suitable for forming a resistive memory element 110 or for other general memory elements, the resistive memory. The component 110 includes a substrate 112, an isolating layer 114, a lower electrode layer 116, a resist layer 118, and an upper electrode layer 120. The insulating layer 114, the lower conductive layer 116, the resistive layer 118, and the upper conductive layer 120 are sequentially disposed on the substrate 112 from bottom to top.

For example, in another preferred embodiment of the present invention, the lower conductive layer 116 has a thickness of 10 to 1000 nm. In another preferred embodiment of the present invention, the lower conductive layer 116 has a specific crystal alignment direction, and the crystal alignment direction includes (100), (200) or (110). In another preferred embodiment of the present invention, the resistive layer 118 has a thickness of 20 to 500 nm.

Fig. 2 is a view showing the relationship between voltage and current of the switching characteristics of the memory of the preferred embodiment of the present invention, wherein the horizontal axis is voltage and the vertical axis is current. Referring to FIGS. 1 and 2, the switching characteristics of the resistive memory device 110 sequentially include an initializing operation 212, a erase operation 214, and a write operation SET 216. It is not intended to limit the scope of the invention.

For example, the method for improving the switching characteristics of the memory according to the preferred embodiment of the present invention includes: after preparing the resistive memory device 110, generating a partial electric field in the resistive memory device 110. For example, the local electric field is generated by the voltage bias treatment on the upper conductive layer 120, and the local electric field is formed on the resistance layer 118 to improve the switching characteristics (not shown). The initialization operation 212 is then performed on the resistive memory device 110.

The method for improving the switching characteristics of the memory of the preferred embodiment of the present invention is a method for improving the characteristics of the prior to the switching of the memory, and the preferred embodiment of the present invention uses the technique of local electric field 〞. The noun can be defined as a tiny electric field formed in the resistive memory element 110, as will be described herein.

Referring to FIGS. 1 and 2 again, since the initial resistance state (IRS) of the resistive memory device 110 is too high, the initialization operation 212 needs to be provided, so that the resistive memory can be provided. Body element 110 begins to perform a memory function.

After the resistive memory device 110 is completed, the initialization operation 212 is performed on the resistive memory device 110. For example, the bias voltage of the initialization action 212 increases from 0V to the positive direction. As the bias voltage increases to V1, the current rises sharply, the resistance decreases instantaneously, and a conductance is formed inside the resistive memory element 110. The path, and the resistance of the resistive memory element 110 transitions to a low resistance state, ie, the initialization action 212 is completed to subsequently perform the erase action 214.

Then, the erasing action 214 is performed on the resistive memory device 110, and an erase voltage is appropriately applied. The bias voltage of the erase voltage is increased in a negative direction from 0 V, and the current is gradually increased as the negative bias voltage is increased. When the negative voltage increases to V2, the current drops sharply, the resistance increases instantaneously, and the conductance path inside the resistive memory element 110 is broken. The rupture, and the resistance of the resistive memory element 110 transitions to a high resistance state, that is, the erase action 214 is completed to subsequently perform the write action 216.

Then, the write operation 216 is performed on the resistive memory device 110, and a write voltage is appropriately applied. The bias voltage of the write voltage is positively increased from 0 V, and the current is increased as the bias voltage is increased to V3. The conduction path is re-established, and the conductance path is again formed inside the resistive memory element 110, and the resistance of the resistive memory element 110 is again converted to a low resistance state, that is, the write operation 216 is completed. As such, the resistive memory component 110 has completed the operational mechanism of the resistive memory, that is, the memory function has been completed. The erasing operation 214 and the writing operation 216 are continuously performed in sequence, and the resistive memory element 110 can be operated.

A method for improving switching characteristics of a memory according to a preferred embodiment of the present invention includes forming a plurality of current conduction paths in the resistive memory device 110. For example, in order to prevent the resistive memory element 110 from continuously flowing up through the resistive memory element 110 after forming the current conducting path, the resistive memory element 110 may be permanently damaged. . In order to prevent the current flowing through the resistive memory device 110 from rising continuously, when the initializing operation 212 and the writing operation 216 are applied to the resistive memory device 110, the limiting currents I1 and I3 are appropriately set, as in the second The figure is shown to protect the resistive memory element 110. In addition, in the erase operation 214, the current conduction path is broken as the reverse bias voltage increases, so there is no need to set the limit current, as shown in FIG. 2, wherein the erase current is I2.

In the present invention, when the initializing action 212 and the writing operation 216 are applied to a specific value by applying a bias voltage, the current conducting path is formed in the resistive layer 118, so that the resistance value of the resistive memory device 110 is greatly reduced and enters. a low resistance state, and when the resistive memory element 110 performs the erase operation 214 in a low resistance state, the current conduction path in the resistance layer 118 forms a fracture, and thus the resistive memory element 110 The resistance value rises again and enters a high resistance state. The resistive memory device 110 is distinguished by the above-described low resistance state and high resistance state as 〝0〞 and 〝1〞 of the digital signal.

FIG. 3 is a flow chart showing a method for improving the electrode of the memory according to the preferred embodiment of the present invention, which comprises five step blocks. Referring to FIGS. 1, 2 and 3, the substrate 112 containing the lower conductive layer 116 is prepared in step 312, and the resistive layer 118 and the upper conductive layer 120 are deposited in step 314. The current conducting path is formed inside the resistive layer 118, and a memory function is performed in step 318. In addition, step 322 is performed prior to step 314, in which the conductive layer 116 under the resistive memory device 110 is plasma surface treated.

The present invention utilizes the surface treatment of the lower conductive layer 116 to physically or chemically react the surface of the lower conductive layer 116 to eliminate surface effects thereof and reduce surface defects of the lower conductive layer 116 or reduce the lower conductive layer 116. The interface layer is used to achieve improved operational stability of the resistive memory device 110.

Referring to FIGS. 1 and 3 , for example, the preferred embodiment of the present invention uses the resistive memory device 110 as follows: the substrate 112 is a P-type wafer, and the substrate 112 is first RCA. Cleaning and removing the native oxide layer, particles and organic matter on the wafer, and then using a horizontal furnace tube to grow 200 nm or other suitable thickness of cerium oxide [SiO2] to form the insulating layer 114 to prevent leakage of the substrate 112 and reduce Parasitic effects.

Next, 20 nm or other suitable thickness of titanium nitride [TiN] is deposited by a multi-layer metal sputtering system or other suitable technique as an adhesive layer to adhere the insulating layer 114 and the lower conductive layer. Layer 116.

Next, using a chemical vapor deposition (CVD) system or other suitable When the technical means deposits 150 nm or other suitable thickness of tungsten as the lower conductive layer 116 (ie, the lower conductive electrode), the substrate 112 including the lower conductive layer 116 is completed, as in step 312 of FIG. Shown.

Next, in a preferred embodiment of the present invention, the substrate 112 including the lower conductive layer 116 is surface-treated by appropriate technical means before depositing the resistive layer 118. For example, the surface treatment is a plasma surface treatment, and carbon tetrafluoride [CF ₄ ] or other suitable gas is selected as the gas source for the plasma surface treatment, as shown in step 322 of FIG. The plasma surface treatment uses a reactive gas selected from the group consisting of Ar, O ₂ , N ₂ , NH ₃ , N ₂ O, H ₂ O, H ₂ , Cl ₂ or any mixed gas thereof.

Next, 20 nm or other suitable thickness of cerium oxide is sputtered by a RF magnetron sputtering machine (RF-Magnetron Sputter) or other techniques as the resistance layer 118.

Next, 200 nm or other suitable thickness of copper [Cu] is deposited by a thermal evaporation machine or other technical means as the upper conductive layer 120 (ie, the lower conductive electrode), and the metal mask is used for the purpose. The area of the upper conductive layer 120 is as shown in step 314 of FIG.

In addition, another preferred embodiment of the present invention selects the surface treatment of the lower conductive layer 116 and the upper conductive layer 120 by appropriate technical means, or selects only the upper conductive layer 120 to be surface-treated by appropriate technical means. For example, the surface treatment is a plasma surface treatment, and carbon tetrafluoride [CF ₄ ] or other suitable gas is selected as the gas source for the plasma surface treatment. The plasma surface treatment uses a reactive gas selected from the group consisting of Ar, O ₂ , N ₂ , NH ₃ , N ₂ O, H ₂ O, H ₂ , Cl ₂ or any mixed gas thereof.

The electrical measurement of the present invention is tested by the HP 4155B semiconductor parameter analyzer, and various electrical analysis is performed by using the automated measurement program developed by the LabVIEW program editing software. The upper conductive layer 120 is connected. The power output is connected to the ground layer.

Figure 4 is a diagram showing the operating voltage of the memory of the preferred embodiment of the present invention. Please refer to Figure 4, which shows the operating voltage of the resistive memory device. 412 is the write voltage of the resistive memory without the surface treatment of the plasma; 414 is the erase voltage of the resistive memory without the surface treatment of the plasma; 416 is the resistive memory after the surface treatment by the plasma The write voltage, 418 is the erase voltage of the resistive memory after the plasma surface treatment.

Referring to FIGS. 1 and 4 again, the display voltage 416 of the resistive memory after the surface treatment of the plasma and the erase voltage 418 of the resistive memory after the plasma surface treatment are compared with respect to the The write voltage 412 of the resistive memory that is not subjected to the plasma surface treatment and the erase voltage 414 of the resistive memory that has not been subjected to the plasma surface treatment tend to decrease. It is known from the foregoing that the surface treatment of the lower conductive layer 116 has been eliminated by the plasma surface treatment of the present invention, the operating voltage of the resistive memory element 110 is significantly reduced, and the operational stability of the resistive memory element 110 is improved. .

Fig. 5 is a view showing the state of resistance of the memory of the preferred embodiment of the present invention. Referring to Figure 5, it shows the resistance state of the resistive memory device. 512 is the low resistance state of the resistive memory without surface plasma treatment; 514 is the high resistance state of the resistive memory without surface plasma treatment; 516 is the resistive memory after the surface plasma treatment In the low resistance state, 518 is a high resistance state of the resistive memory after surface plasma treatment.

Referring again to FIGS. 1 and 5, the low resistance state 516 of the resistive memory after the surface plasma treatment and the high resistance state 518 of the resistive memory after the surface plasma treatment are compared with respect to the The low resistance state 512 of the resistive memory without surface plasma treatment and the high resistance state of the resistive memory without surface plasma treatment become 514 More stable. It is known from the foregoing that the surface treatment of the lower conductive layer 116 is changed by the plasma surface treatment of the present invention, and the surface effect thereof is eliminated, and the surface defects of the lower conductive layer 116 are reduced, thereby improving the resistive memory element 110. Operational stability.

Referring to Figures 1, 4 and 5 again, the resistive memory device 110 of the present invention has the advantage of low process difficulty compared to the conventional resistive memory, and the component preparation can be completed at room temperature. There is no need to consider issues such as heat accumulation and process integration. In addition, the resistive memory device 110 of the present invention has the advantages of low manufacturing cost, easy execution, and high compatibility with general semiconductor processes, thereby achieving cost reduction while improving the operational stability of the resistive memory device 110.

The foregoing preferred embodiments are merely illustrative of the invention and the technical features thereof, and the techniques of the embodiments can be carried out with various substantial equivalent modifications and/or alternatives; therefore, the scope of the invention is subject to the appended claims. The scope defined by the scope shall prevail. The copyright limitation of this case is used for the purpose of patent application in the Republic of China.

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Claims (10)

A method for improving an electrode of a memory, comprising: providing a substrate, wherein the substrate comprises a lower conductive layer, and the lower conductive layer is formed on the substrate; and the lower conductive layer is surface-treated to form a surface treated a conductive layer; forming a resistive layer on the lower conductive layer; and forming an upper conductive layer on the resistive layer; wherein the surface treated lower conductive layer eliminates surface effects thereof and reduces surface defects or reduction of the lower conductive layer The interface layer of the lower conductive layer. A method for improving an electrode of a memory, comprising: providing a substrate, wherein the substrate comprises a lower conductive layer, a resistive layer and an upper conductive layer, and the lower conductive layer is formed on the substrate, the resistive layer is formed under the substrate On the conductive layer, the upper conductive layer is formed on the resistive layer; the upper conductive layer is surface-treated to form a surface-treated upper conductive layer; and the surface-treated upper conductive layer eliminates surface effects thereof and reduces The surface of the upper conductive layer is defective or the interface layer of the upper conductive layer is reduced. The method for improving the electrode of the memory according to claim 1 or 2, wherein the surface treatment is a plasma surface treatment. The method for improving the electrode according to the third aspect of the invention, wherein the plasma surface treatment uses a reactive gas, and the reaction gas is selected from the group consisting of Ar, O ₂ , N ₂ , NH ₃ , CF ₄ , N _{2 .} O, H ₂ O, H ₂ , Cl ₂ or any mixture thereof. The method for improving the electrode of the memory according to the first or second aspect of the invention, wherein the lower conductive layer or the upper conductive layer has a specific crystal arrangement direction, and the crystal arrangement direction comprises (100), (200) or (110). The method for improving the electrode of the memory according to the first aspect of the invention, wherein the lower conductive layer is surface-treated after the lower conductive layer is formed on the substrate. A memory structure comprising: a substrate; an insulating layer disposed on the substrate; a lower conductive layer disposed on the insulating layer; a resistive layer disposed on the lower conductive layer; and an upper layer a conductive layer disposed on the resistive layer; wherein the lower conductive layer or the upper conductive layer is surface-treated to physically or chemically react the lower conductive layer or the upper conductive layer to eliminate surface effects thereof and reduce the lower layer The surface of the conductive layer or the upper conductive layer is defective or the interface layer of the lower conductive layer or the upper conductive layer is reduced. The memory structure of claim 7, wherein the surface treatment is a plasma surface treatment. The memory structure according to claim 8, wherein the plasma surface treatment uses a reactive gas, and the reaction gas is selected from the group consisting of Ar, O ₂ , N ₂ , NH ₃ , CF ₄ , N ₂ O, H. ₂ O, H ₂ , Cl ₂ or any mixture thereof. The memory structure according to claim 7, wherein the lower conductive layer or the upper conductive layer has a specific crystal arrangement direction, and the crystal arrangement direction includes (100), (200) or (110).