CN105185903B - A kind of preparation method of resistor-type memory cell - Google Patents

A kind of preparation method of resistor-type memory cell Download PDF

Info

Publication number
CN105185903B
CN105185903B CN201510503866.9A CN201510503866A CN105185903B CN 105185903 B CN105185903 B CN 105185903B CN 201510503866 A CN201510503866 A CN 201510503866A CN 105185903 B CN105185903 B CN 105185903B
Authority
CN
China
Prior art keywords
layer
memory cell
resistor
type memory
electrode layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201510503866.9A
Other languages
Chinese (zh)
Other versions
CN105185903A (en
Inventor
刘汇慧
李同伟
崔红玲
毛爱霞
王会娴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Henan University of Science and Technology
Original Assignee
Henan University of Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Henan University of Science and Technology filed Critical Henan University of Science and Technology
Priority to CN201510503866.9A priority Critical patent/CN105185903B/en
Publication of CN105185903A publication Critical patent/CN105185903A/en
Application granted granted Critical
Publication of CN105185903B publication Critical patent/CN105185903B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Semiconductor Memories (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

A kind of preparation method of resistor-type memory cell, it is related to nonvolatile semiconductor memory member technical field, first, with conductive material formation lower electrode layer on substrate, deposition or one layer of insulating medium layer of spin coating on lower electrode layer, groove is formed on insulating medium layer by photoetching process, the bottom land of groove passes to lower electrode layer;Then, the functional layer of resistor-type memory cell is formed in groove, the functional layer is upper and lower two layers of laminated construction, and it is by amorphous SnOxLayer and nitrogen oxides MnOxNyLayer laminate is constituted, amorphous SnOxMiddle x span is 0<x<2, nitrogen oxides MnOxNyIn x and y span be respectively 1<x<2,0.001<y<2;Finally, the flush of upper electrode layer and insulating medium layer is made using flatening process with conductive material formation upper electrode layer on a functional, you can.Resistor-type memory cell prepared by the present invention can stably realize multilevel storage, it is possible to increase the storage density and stability of memory cell.

Description

A kind of preparation method of resistor-type memory cell
Technical field
The present invention relates to nonvolatile semiconductor memory member technical field, and in particular to a kind of resistive formula of high density thin membrane structure The preparation method of memory cell.
Background technology
Developed rapidly recently as computer technology, Internet technology, nonvolatile semiconductor memory member is in semiconductor row Play the part of more and more important role in industry.In nonvolatile semiconductor memory member, though when power supply be cut off, the elementary cell of device Still keep the data stored in elementary cell.Resistive random access memory (RRAM)(Resistive Random Access Memory, RRAM)It is a kind of new nonvolatile memory, the mechanism of its work is to trigger reversible resistance transition effect in external electric field, that is, is existed In the presence of applied voltage, the resistance of device is in low resistance state(“0”)And high-impedance state(“1”)Between reversible transition, it is and resulting Resistance external electric field removal after can remain behind.Resistor-type memory due to high read or write speed, high integration and The features such as multilevel storage ability, and as the focus studied at this stage.
Resistive memory is usually metal-oxide-metal sandwich structure, can pass through conventional filming technology Such as sputter, prepared by the technique that is vapor-deposited;Meanwhile, be present multilevel electric resistance changing phenomenon in resistive memory, do not changing The storage of more information can be realized under conditions of unit volume, and it is good with semiconductor technology compatibility, it is possible to use it is existing Some semiconductor process technique production, can reduce development cost significantly.
On the premise of performance is ensured, the focus that storage density is existing research how is improved, storage density ability is improved Reduce cost and improve the market competitiveness.In general, the storage density for improving memory mainly has following two modes:The first It is, come the size of reduction unit area, typically to use cross array structure with realization theory by technique or device architecture Minimum unit area;Second is to use multilevel memory cell, can improve storage face in the case where not increasing storage area Product, lowers the cost of position/area, and multilevel storage refers to binary number of the record more than a bit on a node of memory According to, so that increase the storage density of memory, raising memory capacity.
At present, researcher obtains multilevel storage and mainly obtained by improving individual layer change resistance layer, such as applies different Reset voltages obtain the resistance of different high-impedance states, or pass through and apply different programmings electricity to one-off programming memory The program current of pressure or different current strength, makes one-time programming memory program different low resistance states from high-impedance state, to realize Multilevel storage.But be due to individual layer change resistance layer structures shape during reset, not no stable intermediate state, just Cause the uniformity of the multilevel storage of individual layer resistive Rotating fields it is difficult to ensure that.
The content of the invention
It is an object of the invention to provide a kind of resistor-type memory cell for the membrane structure that change resistance performance is good, stability is good and Its preparation method.
To achieve the above object, the technical scheme is that:A kind of resistor-type memory cell, its functional layer becomes for resistance Change type accumulation layer, the functional layer is upper and lower two layers of laminated construction, and it is by amorphous SnOxLayer and nitrogen oxides MnOxNyLayer Lamination is constituted, wherein, amorphous SnOxMiddle x span is 0<x<2, nitrogen oxides MnOxNyIn x and y value model Enclose respectively 1<x<2,0.001<y<2.
The resistor-type memory cell includes substrate, lower electrode layer, functional layer, upper electrode layer and insulating medium layer, lower electricity Pole layer is covered on substrate, and insulating medium layer is covered on lower electrode layer, and insulating medium layer passes to lower electrode layer provided with bottom land Groove, upper electrode layer and functional layer are sequentially provided with from top to bottom in groove, functional layer is directly contacted with lower electrode layer, Top electrode Layer is set with insulating medium layer flush.
The lower electrode layer and upper electrode layer are conducting metal, conductive metal alloy or conductive metallic compound, wherein Conducting metal be Cu, Ag, Ti, Pt or Ni, conductive metal alloy be Pt/Ti, Cu/Ti or Cu/Au, conductive metallic compound For TiN, TaN or ITO.
The material of the insulating medium layer is SiO2Or SiN.
The thickness of the lower electrode layer and upper electrode layer is amorphous SnO in 80-150nm, functional layerxThe thickness of layer For 20-45nm, nitrogen oxides MnOxNyThe thickness of layer is 50-80nm, and the thickness of insulating medium layer is 300nm ~ 5000nm.
The substrate is the substrate of glass substrate, semiconductor substrate or other suitable materials.
The preparation method of the resistor-type memory cell of the present invention, comprises the following steps:
(1), on substrate with conductive material formation lower electrode layer;
(2), on lower electrode layer deposition or one layer of insulating medium layer of spin coating, then by photoetching process in insulating medium layer Upper formation groove, the bottom land of groove passes to lower electrode layer;
(3), using the method for magnetron sputtering or ald the resistor-type memory cell is formed in groove Functional layer, the functional layer is upper and lower two layers of laminated construction, and it is by amorphous SnOxLayer and nitrogen oxides MnOxNyLayer laminate Constitute, wherein, amorphous SnOxMiddle x span is 0<x<2, nitrogen oxides MnOxNyIn x and y span point Wei 1<x<2,0.001<y<2;
(4), on a functional with conductive material formation upper electrode layer, using flatening process make upper electrode layer with insulation be situated between The flush of matter layer, you can.
Above-mentioned steps(3)In, the formation of double-decker functional layer includes amorphous SnOxFilm forming step and nitrogen oxygen Compound MnOxNyFilm forming step, can first form amorphous SnO in groovexFilm layer, then in amorphous SnOxIt is thin Nitrogen oxides MnO is formed in film layerxNyFilm layer, can also first form nitrogen oxides MnO in groovexNyFilm layer, then in nitrogen Oxide M nOxNyAmorphous SnO is formed in film layerxFilm layer.
Amorphous SnOxFilm forming method:Using metallic tin as target, the reaction of magnetic-controlled sputtering coating equipment is controlled Chamber indoor temperature is 180 DEG C ~ 200 DEG C, and O is passed through into reaction chamber2With Ar gases, metallic tin target is sent out under Ar Ions Bombardments Raw sputtering, and with the O in reaction chamber2Collide and react, so as to form amorphous SnOxFilm.
Nitrogen oxides MnOxNyThe forming method of film layer:First, two-step method:First, using metal Mn as target, control is anti- It is 100 ~ 400 DEG C to answer chamber indoor temperature, and O is passed through into reaction chamber2With Ar gases, metal Mn targets are sent out under Ar Ions Bombardments Raw sputtering, and with the O in reaction chamber2Collide and react, so as to be initially formed one layer of MnOxFilm layer;Then, to MnOxLayer N~+ implantation is carried out with by MnOxLayer is changed into nitrogen oxides MnOxNyLayer.2nd, one-step method:Using metal Mn as target, control Reaction chamber indoor temperature is 100 ~ 400 DEG C, and O is passed through into reaction chamber2With Ar gases, while into reaction chamber inject nitrogen from Component, metal Mn targets are sputtered under Ar Ions Bombardments, with the O in reaction chamber2Collide and the generation MnO that reactsx, MnOxCombined with the Nitrogen ion of injection, so as to form one layer of nitrogen oxides MnOxNyFilm layer.In two methods, by controlling oxygen X and y value are controlled with the intake of Nitrogen ion, finally makes the nitrogen oxides MnO to be formedxNyX and y span point Wei 1<x<2,0.001<y<2.
In the preparation process in accordance with the present invention, even if amorphous Sn OxA surface part for layer is being passed through O2During absorb Oxygen formation SnO2, the storage characteristics of this layer is not interfered with yet, because the main component or the SnO of amorphous of this layerx, 0<x<2.
Beneficial effect:
1st, the store function layer of resistor-type memory cell prepared by the present invention is by amorphous SnOxLayer and nitrogen oxides MnOxNyThe double-decker of layer laminate formation, the store function layer of this double-decker, in the presence of current impulse, can stablize Realize multilevel storage in ground.
2nd, resistor-type memory cell prepared by the present invention has low resistance state, stable intermediate state and high-impedance state, realizes many The stability and uniformity of resistance state, it is possible to increase the storage density and stability of memory cell.
3rd, wherein, amorphous SnOx, can under low current operation with a very brief current impulse in stable state To realize reset processes, current power dissipation can be reduced in storing process.Nitrogen oxides MnOxNyIn N+Movement can be real The formation and fracture of existing room conductive channel, can also reduce the resistive voltage in storing process, reduce electric current work(during storage Consumption.
Brief description of the drawings
The structural representation for the resistor-type memory cell that accompanying drawing 1 is prepared for the present invention;
The test chart of the I-E characteristic for the resistor-type memory cell that accompanying drawing 2 is prepared for the present invention;
The test chart of the resistance state retentivity for the resistor-type memory cell that accompanying drawing 3 is prepared for the present invention.
The drawing reference numeral of accompanying drawing 1:1st, substrate, 2, lower electrode layer, 3, insulating medium layer, 4 and 5 represent the non-of functional layer respectively Crystalline state SnOxLayer and nitrogen oxides MnOxNyLayer, or nitrogen oxides MnO is represented respectivelyxNyLayer and amorphous Sn OxLayer, 6, upper electricity Pole layer.
Embodiment
As shown in figure 1, resistor-type memory cell prepared by the present invention includes substrate 1, lower electrode layer 2, functional layer, Top electrode Layer 6 and insulating medium layer 3, lower electrode layer 2 are covered on substrate 1, and insulating medium layer 3 is covered on lower electrode layer 2, dielectric Layer 3 passes in the groove of lower electrode layer 2, groove provided with bottom land and is sequentially provided with upper electrode layer 6 and functional layer, function from top to bottom Layer is directly contacted with lower electrode layer 2, and upper electrode layer 6 is set with the flush of insulating medium layer 3.Functional layer therein becomes for resistance Change type accumulation layer, the functional layer is upper and lower two layers of laminated construction, and it is by amorphous SnOxLayer and nitrogen oxides MnOxNyLayer Lamination is constituted, wherein, amorphous SnOxMiddle x span is 0<x<2, nitrogen oxides MnOxNyIn x and y value model Enclose respectively 1<x<2,0.001<y<2.Functional layer can be that upper strata is amorphous SnOxLayer, lower floor is nitrogen oxides MnOxNy Layer or upper strata are nitrogen oxides MnOxNyLayer, lower floor is amorphous SnOxLayer.
Using analyzing parameters of semiconductor tester test prepared by the present invention based on double-decker resistance-change memory functional layer The I-E characteristic of resistor-type memory cell(Namely I-V characteristic), resistor-type is tested under the continuous scan pattern of voltage The I-E characteristic of memory cell, current-voltage test result are as shown in fig. 2, it can be seen that in certain voltage and electricity Flow down, resistor-type memory cell of the invention can stably realize the circulation of erasing and write-in, can realize the characteristic of storage.
The resistance state for the resistor-type memory cell based on double-decker resistance-change memory functional layer that accompanying drawing 3 is prepared for the present invention is protected The test chart of holding property, as can be seen from the figure:Resistor-type memory cell prepared by the present invention has stable low resistance state, intermediate state And high-impedance state, resistance state has good retention performance.
Two embodiments are set forth below to illustrate the preparation method of resistor-type memory cell of the present invention, can be according to the present invention's The difference of each tunic material in resistor-type memory cell, the appropriate section in two embodiment preparation methods is changed or Replacement can just prepare the different resistor-type memory cell in the scope of the present invention.
Embodiment 1
A kind of preparation method of resistor-type memory cell, its step is as follows:
(1), lower electrode layer formed on substrate using magnetron sputtering coating method:Using Ni metal target, using Ar gas as Working gas, on the glass substrate sputtering forms Cu films, wherein operating pressure during sputtering is 5 × 10-1Pa~10×10- 1Pa, sputtering time is 20 ~ 25min, and sputtering voltage is 300 ~ 380V, and sputtering current is 120 ~ 180mA, finally in glass substrate It is upper to form the Cu lower electrode layers that thickness is about 80-150nm;
(2), on Cu lower electrode layers formed one layer of insulating medium layer:The mode for forming insulating medium layer can be atomic layer Deposition process or the mode of spin coating, the thickness for forming insulating medium layer is 300nm ~ 5000nm, and the material of insulating medium layer can be with For SiO2Or SiN, after insulating medium layer is formed, groove is formed on insulating medium layer using traditional photoetching process, For forming other follow-up Rotating fields;
(3), amorphous SnO is formed in the groove of formationxFilm:Using metallic tin target, in reaction chamber internal control Temperature processed is 180 DEG C ~ 200 DEG C, and O is passed through into reaction chamber2With Ar gases, O is controlled2The partial pressure of gas is 5 × 10-2Pa~1× 10-1Pa, operating pressure is 5 × 10-1Pa~10×10-1Pa, metallic tin target is sputtered under Ar Ions Bombardments, and with reaction O in chamber2Collide and react, so as to form amorphous SnOxFilm, wherein, the reaction time(That is sputtering time)For 40 ~ 100 minutes, 50 ~ 200mA of sputtering current, sputtering voltage was 300 ~ 380V, the amorphous Sn O of formationxThe thickness of film is 20 ~45nm;
(4), nitrogen oxides MnOxNyThe preparation of film:Nitrogen oxides MnOxNyFilm is prepared in two steps, first, using Mn Target, the temperature for keeping substrate is 100 ~ 400 DEG C, and O is passed through into reaction chamber2With Ar gases, O is controlled2The partial pressure of gas is 5 ×10-2Pa~1×10-1Pa, metal Mn targets are sputtered under Ar Ions Bombardments, and with the O in reaction chamber2Collide and send out Raw reaction, so as to be initially formed one layer of MnOxLayer, wherein, the reaction time(That is sputtering time)For 20 ~ 150 minutes, sputtering current 30 ~ 400mA, sputtering voltage is 200 ~ 380V;Then, to MnOxLayer carries out N~+ implantation, and the ion implanting time is 10 ~ 80 minutes, So as to by MnOxLayer is changed into nitrogen oxides MnOxNyLayer.Wherein, control x's and y by controlling the intake of oxygen and Nitrogen ion Value, finally makes the nitrogen oxides MnO to be formedxNyX and y span be respectively 1<x<2,0.001<y<2, the thickness of formation Spend for 50-80nm;
(5), in nitrogen oxides MnOxNyPass through the method formation Ag metal levels of magnetron sputtering or ald on film As upper electrode layer, the Ag metal levels and dielectric as upper electrode layer are made by flatening process after formation Ag metal levels Layer surface is flushed, that is, the functional layer and upper electrode layer of the double-decker ultimately formed are located in the groove of insulating medium layer.
Embodiment 2
A kind of preparation method of resistor-type memory cell, its step is as follows:
(1), using Pt metal target, using Ar gas as working gas, on a semiconductor substrate sputtering form Pt films, wherein Semiconductor substrate can be Si substrates, operating pressure during sputtering is 5 × 10-1Pa~10×10-1Pa, sputtering time be 20 ~ 45min, sputtering voltage is 300 ~ 380V, and sputtering current is 120 ~ 180mA, forms the Pt bottom electrodes that thickness is about 80-150nm Layer;
(2), on Pt lower electrode layers formed one layer of insulating medium layer, is formed insulating medium layer mode can for deposit or The mode of spin coating, the thickness for forming insulating medium layer is 300nm ~ 5000nm, and the material of insulating medium layer can be SiO2Or SiN materials, after insulating medium layer is formed, groove is formed for shape using traditional photoetching process on insulating medium layer Into other follow-up Rotating fields;
(3), nitrogen oxides MnO is formed in the groove of formationxNyFilm:Forming nitrogen oxides MnOxNyAdopted during film Formed with a step, using Mn targets, the temperature for keeping substrate is 100 ~ 400 DEG C, and O is passed through into reaction chamber2With Ar gases, together When Nitrogen ion source is injected into reaction chamber, control O2The partial pressure of gas is 5 × 10-2Pa~1×10-1Pa, sputtering current 30 ~ 400mA, sputtering voltage is 200 ~ 380V, and the reaction time is 50 ~ 180 minutes, and metal Mn targets splash under Ar Ions Bombardments Penetrate, with the O in reaction chamber2Collide and the generation MnO that reactsx, MnOxCombined with the Nitrogen ion of injection, so as to form one layer Nitrogen oxides MnOxNyFilm layer;Wherein, x and y value are controlled by controlling the intake of oxygen and Nitrogen ion, finally makes shape Into nitrogen oxides MnOxNyX and y span be respectively 1<x<2,0.001<y<2, the thickness of formation is about 50-80nm;
(4), in nitrogen oxides MnOxNyAmorphous SnO is formed on filmxFilm:Using metallic tin target, in reaction chamber It is indoor to control temperature to be 180 DEG C ~ 200 DEG C, O is passed through into reaction chamber2With Ar gases, O is controlled2The partial pressure of gas is 5 × 10- 2Pa~1×10-1Pa, operating pressure is 5 × 10-1Pa~10×10-1Pa, forms amorphous SnOxFilm;Wherein, the reaction time For 40 ~ 100 minutes, 50 ~ 200mA of sputtering current, sputtering voltage was 300 ~ 380V, the amorphous Sn O of formationxThe thickness of film is 20~45nm;
(5), in amorphous Sn OxUpper electricity is used as by magnetron sputtering or ald formation Ti metal levels on film Made after pole layer, formation Ti metal levels by flatening process neat as the Ti metal levels and dielectric layer surface of upper electrode layer Flat, the double-deck resistive functional layer and upper electrode layer ultimately formed is located in the groove of insulating medium layer.

Claims (6)

1. a kind of preparation method of resistor-type memory cell, it is characterised in that:Comprise the following steps:
(1), on substrate with conductive material formation lower electrode layer;
(2), on lower electrode layer deposition or one layer of insulating medium layer of spin coating, then by photoetching process on insulating medium layer shape Into groove, the bottom land of groove passes to lower electrode layer;
(3), the function of the resistor-type memory cell is formed using the method for magnetron sputtering or ald in groove Layer, the functional layer is upper and lower two layers of laminated construction, and it is by amorphous SnOxLayer and nitrogen oxides MnOxNyLayer laminate is constituted, Wherein, amorphous SnOxMiddle x span is 0<x<2, nitrogen oxides MnOxNyIn x and y span be respectively 1< x<2,0.001<y<2;
(4), on a functional with conductive material formation upper electrode layer, make upper electrode layer and insulating medium layer using flatening process Flush, you can.
2. a kind of preparation method of resistor-type memory cell as claimed in claim 1, it is characterised in that:Step(3)In, utilize The method that magnetic-controlled sputtering coating equipment forms the functional layer is:First, using metallic tin as target, magnetron sputtering plating is controlled The reaction chamber indoor temperature of equipment is 180 DEG C ~ 200 DEG C, and O is passed through into reaction chamber2With Ar gases, the gold under Ar Ions Bombardments Category tin target sputter, and with the O in reaction chamber2Collide and react, so as to form amorphous SnOxFilm;So Afterwards, using metal Mn as target, it is 100 ~ 400 DEG C to control reaction chamber indoor temperature, and O is passed through into reaction chamber2With Ar gases, Metal Mn targets are sputtered under Ar Ions Bombardments, and with the O in reaction chamber2Collide and react, so that in amorphous The SnO of statexMnO is formed on filmxLayer, to MnOxLayer carries out N~+ implantation with by MnOxLayer is changed into nitrogen oxides MnOxNy Layer.
3. a kind of preparation method of resistor-type memory cell as claimed in claim 1, it is characterised in that:Step(1)And step (4)Described in conductive material be conducting metal, conductive metal alloy or conductive metallic compound, conducting metal therein is Cu, Ag, Ti, Pt or Ni, conductive metal alloy be Pt/Ti, Cu/Ti or Cu/Au, conductive metallic compound be TiN, TaN or ITO。
4. a kind of preparation method of resistor-type memory cell as claimed in claim 1, it is characterised in that:The insulating medium layer Material be SiO2Or SiN.
5. a kind of preparation method of resistor-type memory cell as claimed in claim 1, it is characterised in that:The lower electrode layer and The thickness of upper electrode layer is amorphous SnO in 80-150nm, functional layerxThe thickness of layer is 20-45nm, nitrogen oxides MnOxNyThe thickness of layer is 50-80nm, and the thickness of insulating medium layer is 300nm ~ 5000nm.
6. a kind of preparation method of resistor-type memory cell as claimed in claim 1, it is characterised in that:Step(1)Described in Substrate be glass substrate or semiconductor substrate.
CN201510503866.9A 2015-08-17 2015-08-17 A kind of preparation method of resistor-type memory cell Expired - Fee Related CN105185903B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510503866.9A CN105185903B (en) 2015-08-17 2015-08-17 A kind of preparation method of resistor-type memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510503866.9A CN105185903B (en) 2015-08-17 2015-08-17 A kind of preparation method of resistor-type memory cell

Publications (2)

Publication Number Publication Date
CN105185903A CN105185903A (en) 2015-12-23
CN105185903B true CN105185903B (en) 2017-09-26

Family

ID=54907868

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510503866.9A Expired - Fee Related CN105185903B (en) 2015-08-17 2015-08-17 A kind of preparation method of resistor-type memory cell

Country Status (1)

Country Link
CN (1) CN105185903B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106328593B (en) * 2015-06-24 2019-05-31 旺宏电子股份有限公司 Using metal oxide as the memory component of substrate and its manufacturing method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8168468B2 (en) * 2008-02-29 2012-05-01 Freescale Semiconductor, Inc. Method of making a semiconductor device including a bridgeable material
US8274065B2 (en) * 2009-10-19 2012-09-25 Macronix International Co., Ltd. Memory and method of fabricating the same
CN102867911A (en) * 2011-07-07 2013-01-09 复旦大学 Resistance memory and preparation method thereof
JP2013157469A (en) * 2012-01-30 2013-08-15 Sharp Corp Variable resistive element, and nonvolatile semiconductor storage device
US9040951B2 (en) * 2013-08-30 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Resistance variable memory structure and method of forming the same
CN104617218B (en) * 2013-11-04 2018-12-11 华邦电子股份有限公司 Resistive memory device and preparation method thereof

Also Published As

Publication number Publication date
CN105185903A (en) 2015-12-23

Similar Documents

Publication Publication Date Title
US7777215B2 (en) Resistive memory structure with buffer layer
KR101796790B1 (en) Memory component and memory device
CN103367635B (en) Memory element and storage device
CN101556986B (en) Multi-state resistive switching material, thin film prepared therewith, multi-sate resistive switching memory element and application of memory element in memory device
KR101913860B1 (en) Memory element and memory device
JP2011124511A (en) Storage element and storage device
JP2013016530A (en) Memory element, method for manufacturing the same, and memory device
CN103311435B (en) Based on the resistance-variable storing device and preparation method thereof of vanadium oxide/aluminium oxide laminated construction
CN102270739A (en) Resistive random access memory unit having snap switch device and making method of resistive random access memory unit
CN103151459B (en) Hafnium-oxynitride-based low-power consumption resistive random access memory and preparation method for same
Wu et al. Analyzing electric field effect by applying an ultra-short time pulse condition in hafnium oxide-based RRAM
CN105185904B (en) A kind of more resistance state double-layer film structure resistive holders and preparation method thereof
CN105185903B (en) A kind of preparation method of resistor-type memory cell
CN101174673A (en) Double-layer compound film non-volatile memory device and method for producing the same
CN102214674B (en) RRAM (resistive random access memory) with self-rectifying effect based on SOI (silicon on insulator) materials
CN105185902B (en) A kind of resistor-type memory cell
CN111785830A (en) Resistive random access memory based on gallium oxide film and preparation method thereof
CN105514267A (en) Low-power-consumption memristor based on amorphous SiC thin-film and preparation method thereof
CN108258113A (en) The resistance-variable storing device that a kind of performance is controllable and stability is high
CN207993903U (en) The resistance-variable storing device that a kind of performance is controllable and stability is high
Liu et al. Resistive switching characteristics of HfO x/Al 2 O 3 nano-multilayers structure memristor fabricated by atomic layer deposition
CN101599531B (en) Memory cell of resistive random access memory (RRAM) and preparation method thereof
CN101894911A (en) Preparation method of resistance type memory with high data retention ability
CN109273597B (en) Resistive random access memory based on SrO and preparation method thereof
CN103514948A (en) Storage device and storage unit

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20170926

Termination date: 20180817