TWI611404B - Resistive random access memory without having an active electrode and manufacturing method thereof - Google Patents

Resistive random access memory without having an active electrode and manufacturing method thereof Download PDF

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Publication number
TWI611404B
TWI611404B TW104139724A TW104139724A TWI611404B TW I611404 B TWI611404 B TW I611404B TW 104139724 A TW104139724 A TW 104139724A TW 104139724 A TW104139724 A TW 104139724A TW I611404 B TWI611404 B TW I611404B
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layer
metal oxide
resistive
resistive memory
conductive layer
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TW104139724A
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Chinese (zh)
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TW201719654A (en
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劉志益
江崑祺
林盟崇
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國立高雄應用科技大學
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Abstract

A resistive memory comprises a substrate, an insulating layer, a lower conductive layer, a resistive layer, a metal oxide layer and an upper conductive layer. The resistive memory manufacturing method includes: providing the substrate; forming the insulating layer on the substrate; forming the lower conductive layer on the insulating layer; forming the resistive layer on the lower conductive layer; forming the metal oxide layer on Forming the upper conductive layer on the metal oxide layer to form a memory device, and the metal oxide layer is formed between the resistance layer and the upper conductive layer. Since the metal oxide layer provides metal ions to the resistive layer to form a plurality of filamentary paths, an electrochemical transition of the memory element is formed.

Description

Resistive memory without active electrode and manufacturing method thereof

The present invention relates to a resistive memory (resistive RAM) and a method for fabricating the same, and a method of fabricating the same, and more particularly to a resistive memory that does not employ or reduce an active electrode and Manufacturing method construction and manufacturing method thereof.

In general, the conventional resistive memory is disclosed in many domestic and foreign patent materials, for example, the manufacturing method and the invention patent of the resistive memory of the Republic of China Patent Publication No. I473209, which discloses the manufacture of a resistive memory. method. The method includes first placing a substrate in a sputtering chamber and forming a lower electrode on the substrate. A copper target and a cerium oxide target are provided in the sputtering chamber, or a composite target is provided, which is formed by mixing copper with cerium oxide. Then, using the copper target and the cerium oxide target to perform a common sputtering process, or using the composite target to perform a sputtering process to deposit a copper-doped cerium oxide mixed film layer on the surface of the lower electrode And the copper-doped ceria mixed film layer can be used as a variable resistance film layer. The Cu/(Cu+Si) molar percentage of the copper-doped ceria mixed film layer is from 1% to 15%. Further, an upper electrode is formed on the variable resistance film layer to form a resistive memory.

In fact, the variable resistive film layer of the above No. I473209 is doped with a reactive metal copper on the ceria resistive switching layer by a sputtering process, and the copper metal is sputtered to form the upper electrode by a sputtering process, but copper metal The complicated manufacturing process is required in the semiconductor manufacturing process, which makes the process difficulty increase. In addition, copper metal is also prone to diffusion in the semiconductor process, which further reduces the reliability of the memory device.

Another conventional resistive memory, such as the resistive memory structure of the Republic of China Patent Publication No. I489461, its operation method and manufacturing method, and the invention patent, discloses a resistive memory structure, an operation method thereof and a manufacturing method thereof. The resistive memory structure includes a first electrode layer, a resistance switching layer, a diffusion metal layer and a second electrode layer. The resistance switching layer is coated on the first electrode layer, and the diffusion metal layer is coated on the resistance switching layer, and the second electrode layer is coated on the diffusion metal layer. Further, at least one electrode extension portion is provided in the resistance switching layer.

In fact, the diffusion metal layer of the above-mentioned No. I489461 is used as a source of filamentary path growth, so that the memory element grows its filamentary path by the diffusion metal of the diffusion metal layer during the writing process, so as to be a memory state of the memory element. However, the interaction mechanism between the diffusion metal and the active metal is the same, so the memory element still needs to be transformed by the active metal.

In short, the method of manufacturing the resistive memory of the above-mentioned No. I489461 utilizes forming a metal layer on the diffusion metal layer to utilize the metal layer as an upper electrode [second electrode layer]. In operation, a voltage is applied to the metal layer, and the diffusion metal is introduced into the resistance switching layer by an electric field to grow a wire-like path to form an extension of the diffusion metal layer, thereby forming a memory. The memory state of the component. However, this method still needs to pass through the active metal as the core of the filamentary path growth, and the memory process of the memory component will be different due to different operating environments.

Obviously, the conventional resistive memory necessarily has the further requirement of how to avoid the use of active metal and reduce the influence of operating environment factors on the memory state of the memory element, thereby enabling the memory element to provide a stable memory state in different operating environments. The aforementioned Republic of China Patent Notice The patents of I473209 and I489461 are only for reference to the technical background of the present invention and the state of the art is not intended to limit the scope of the present invention.

In view of the above, the present invention provides a resistive memory structure using an active electrode and a method of fabricating the same, which comprises forming at least one metal oxide layer on a resistive layer, and A conductive layer is formed on the metal oxide layer, such that the metal oxide layer is formed between the resistive layer and the upper conductive layer, and the metal oxide layer provides metal ions to electrochemically shift the memory element for different operations. The same switching operation characteristics are generated in the environment to improve the technical disadvantages that the switching operation characteristics of the conventional memory components cannot be stably operated in different operating environments [an airless environment or a dry environment].

The main object of the preferred embodiment of the present invention is to provide a resistive memory structure using no active electrode or a method for fabricating the same, which comprises forming at least one metal oxide layer on a resistive layer and an upper conductive layer. Formed on the metal oxide layer, such that the metal oxide layer is formed between the resistive layer and the upper conductive layer, and the metal oxide layer provides metal ions to electrochemically transfer the memory element for different operating environments [ The same switching operation characteristics are produced in an anhydrous gas environment or a dry environment to achieve the purpose of improving the operational stability of the resistive memory.

In order to achieve the above object, a resistive memory structure according to a preferred embodiment of the present invention comprises: a substrate; an insulating layer disposed on the substrate; a lower conductive layer disposed on the insulating layer; and a resistive layer Provided on the lower conductive layer; at least one metal oxide layer disposed on the resistance layer; and an upper conductive layer disposed on the metal oxide layer to form Forming a memory element, and the metal oxide layer is formed between the resistance layer and the upper conductive layer; wherein the metal oxide layer provides metal ions to the resistance layer to form a plurality of filamentous paths, thereby forming an electrification of the memory element Learn to change.

In order to achieve the above object, a resistive memory structure according to another preferred embodiment of the present invention includes: a substrate; an insulating layer disposed on the substrate; a lower conductive layer disposed on the insulating layer; and a resistive layer Provided on the lower conductive layer; a plurality of metal oxide layers disposed on the resistive layer; and an upper conductive layer disposed on the plurality of metal oxide layers to form a memory device, and The metal oxide layer is formed between the resistive layer and the upper conductive layer; wherein the plurality of metal oxide layers provide metal ions to the resistive layer to form a plurality of filamentary paths, thereby forming an electrochemical transition state of the memory device .

In the preferred embodiment of the invention, the metal oxide layer is a film of a mixture of an active metal oxide film or an active metal oxide.

The metal oxide layer of the preferred embodiment of the invention comprises copper, silver or other active metal.

In the preferred embodiment of the invention, the metal oxide layer comprises a sulfide film, a nitride film or a mixture film thereof.

In order to achieve the above object, a resistive memory manufacturing method according to a preferred embodiment of the present invention includes: providing a substrate; forming an insulating layer on the substrate; forming a conductive layer on the insulating layer; Forming a resistive layer on the lower conductive layer; forming a metal oxide layer on the resistive layer; and forming an upper conductive layer on the metal oxide layer to form a memory device, and the metal oxide layer is formed thereon Between the resistive layer and the upper conductive layer; wherein the metal oxide layer provides metal ions to the resistive layer to form a plurality of filamentary paths, thereby forming an electrochemical transition of the memory element.

In the preferred embodiment of the invention, the metal oxide layer is a film of a mixture of an active metal oxide film or an active metal oxide.

The metal oxide layer of the preferred embodiment of the invention comprises copper, silver or other active metal.

In the preferred embodiment of the invention, the metal oxide layer comprises a sulfide film, a nitride film or a mixture film thereof.

In the preferred embodiment of the invention, the metal oxide layer has a thickness of between 1 and 100 nm.

In a preferred embodiment of the invention, the thickness of the lower conductive layer is between 10 and 1000 nanometers, and the thickness of the resistive layer is between 20 and 500 nanometers.

The metal oxide layer of the preferred embodiment of the present invention is formed by a thermal evaporation method, a sputtering method, a co-sputtering method, an electron beam evaporation method, a plasma oxidation method, or other forming methods.

110‧‧‧Resistive memory components

112‧‧‧Substrate

114‧‧‧Insulation

116‧‧‧lower conductive layer

118‧‧‧resistance layer

120‧‧‧Upper conductive layer

A‧‧‧metal oxide layer

212‧‧‧Initial action

214‧‧‧Erasing action

216‧‧‧Write action

312‧‧ steps

314‧‧‧Steps

316‧‧‧Steps

318‧‧‧Steps

320‧‧‧Steps

324‧‧‧Steps

412‧‧‧Initial action

414‧‧‧Erasing action

416‧‧‧Write action

512‧‧‧Initial action

514‧‧‧Erasing action

516‧‧‧Write action

612‧‧‧Write voltage

614‧‧‧Erase voltage

616‧‧‧Write voltage

618‧‧‧ erase voltage

712‧‧‧High resistance state

714‧‧‧Low resistance state

Fig. 1 is a cross-sectional view showing the structure of a resistive memory according to a preferred embodiment of the present invention.

Fig. 2 is a view showing the relationship between voltage and current of the resistance switching characteristic of the resistive memory according to the preferred embodiment of the present invention.

Figure 3 is a diagram showing a method of manufacturing a resistive memory according to a preferred embodiment of the present invention Schematic diagram of the process.

Figure 4: Schematic diagram of the relationship between voltage and current of a conventional resistive memory device in a gas-free or dry environment.

Fig. 5 is a view showing the relationship between voltage and current of a resistive memory in a gas-free or dry environment in a preferred embodiment of the present invention.

Figure 6 is a schematic view showing the operating voltage of the resistive memory in the atmosphere of the preferred embodiment of the present invention.

Figure 7 is a schematic diagram showing the switching operation between high and low resistance and the number of stable switching times of the resistive memory in the preferred embodiment of the present invention in an anhydrous gas or dry environment.

In order to fully understand the present invention, the preferred embodiments of the present invention are described in detail below, and are not intended to limit the invention.

In general, memory components can be generally divided into two categories, namely, volatile memory and non-volatile memory. The non-volatile memory can still store its memory state in the component without being continuously supplied through the power supply. At present, among various non-volatile memories, flash memory which can be quickly written and erased is particularly valued. However, as components continue to shrink, flash memory is gradually facing the problem of excessive write voltage, excessive write time, physical miniaturization limit and too thin gate, resulting in shortened memory time. Therefore, the newly developed non-volatile memory gradually replaces the flash memory, wherein the resistive memory device has a short write erase time, low operating voltage and current (low power consumption), long memory time, multi-state memory, The structure is simple, the writing and reading modes are simplified, and the required area is small.

In addition to the above advantages, the resistive memory and the complementary metal-oxide semiconductor (CMOS, Complementary Metal-Oxide Semiconductor) have easy and unrestricted process integration. point. Therefore, the current mainstream of research on non-volatile memory is the use of resistive memory as the most forward-looking memory component.

In view of the above, the resistive memory structure using the active electrode and the manufacturing method thereof are not used or improved in the preferred embodiment of the present invention, and are mainly used to improve the electrochemical transition state of the conventional resistive memory device with the pressure of the ambient water and gas. The technical problem of significant switching characteristics (operating characteristics) changes is changed, and the advantages of not requiring complicated processing processes and cost reduction are achieved, and the operational stability of the resistive memory is achieved.

In general, filament theory is one of the theories of the resistance switching mechanism of resistive memory. The filament theoretical mechanism mainly uses the writing and erasing actions to repeatedly form and break the current conductive path or the conductive path inside the resistive layer, thereby forming the resistive memory element into a low resistance state. LRS] and high resistance state (HRS) are used as the discrimination between 〝0〞 and 〝1〞 signals in the digital signal.

According to the above, the switching characteristic of the resistive memory adopts the formation and fracture of the filament-shaped conduction path (current conduction path), thereby switching the element between the low resistance state and the high resistance state. When the filamentary conduction path is formed, the component is in a low resistance state, that is, 〝1〞 in the digital signal. Conversely, when the filamentary conduction path breaks, the component transitions to a high resistance state, which is 〝0〞 in the digital signal.

1 is a cross-sectional view of a resistive memory structure in accordance with a preferred embodiment of the present invention, the construction of which includes six structural layers, but is not intended to limit the scope of the invention. Referring to FIG. 1 , for example, the memory structure of the preferred embodiment of the present invention is suitable for forming a resistive memory element 110 or for other general memory elements, the resistive memory. The component 110 includes a substrate 112, an isolating layer 114, a lower electrode layer 116, a resistive layer 118, and at least One or more metal oxide layers a and an upper electrode layer 120. The insulating layer 114, the lower conductive layer 116, the resistive layer 118, the metal oxide layer a, and the upper conductive layer 120 are sequentially disposed on the substrate 112 from bottom to top.

For example, in another preferred embodiment of the present invention, the lower conductive layer 116 has a thickness of 10 to 1000 nm. In another preferred embodiment of the present invention, the lower conductive layer 116 has a specific crystal alignment direction, and the crystal alignment direction includes (100), (200) or (110). In another preferred embodiment of the present invention, the resistive layer 118 has a thickness of 20 to 500 nm. In another preferred embodiment of the present invention, the metal oxide layer a has a thickness of from 1 to 100 nm.

Fig. 2 is a view showing the relationship between voltage and current of the switching characteristics of the resistive memory according to the preferred embodiment of the present invention, wherein the horizontal axis is voltage and the vertical axis is current. Referring to FIGS. 1 and 2, the switching characteristics of the resistive memory device 110 sequentially include an initializing operation 212, a erase operation 214, and a write operation SET 216. It is not intended to limit the scope of the invention.

Referring to FIGS. 1 and 2 again, after the component is manufactured, since the initial resistance state (IRS) of the resistive memory device 110 is an initial resistance value is too high, the approximate insulation state is Therefore, the initialization action 212 needs to be provided, so that the resistive memory element 110 can start performing the resistance switching function, that is, performing the memory function.

Referring to FIGS. 1 and 2 again, after the preparation of the resistive memory device 110 is completed, the initializing operation 212 is performed on the resistive memory device 110. For example, the bias voltage of the initialization action 212 increases from 0V to the positive direction. As the bias voltage increases to V1, the current rises sharply, the resistance value decreases or decreases instantaneously, and is inside the resistive memory element 110. Forming a filament-like conduction path, and the resistance of the resistive memory element 110 transitions to a low resistance state, that is, completing the initialization action 212 to The erase action 214 is subsequently performed.

Then, the erasing action 214 is performed on the resistive memory device 110, and an erase voltage is appropriately applied. The bias voltage of the erase voltage is negatively increased from 0 V to apply a negative bias. As the negative bias voltage increases, the current also gradually increases, and its voltage is proportional to the current. When the negative voltage is increased to V2, the current is rapidly decreased, the resistance is instantaneously increased, and the filament-like conduction path inside the resistive memory element 110 is broken, and the resistance of the resistive memory element 110 is changed to high. The resist state, i.e., the erase action 214 is completed, to subsequently perform the write action 216.

Next, the write operation 216 is performed on the resistive memory device 110, and a write voltage is applied as appropriate, and the bias voltage of the write voltage is positively increased from 0 V to apply a positive bias. As the bias voltage is increased to V3, the resistance value is instantaneously decreased or decreased, the current is rapidly increased, and the filament-shaped conduction path is again formed inside the resistive memory element 110, and the resistance of the resistive memory element 110 is again The write to action 216 is accomplished by transitioning to a low resistance state. As such, the resistive memory component 110 has completed the operational mechanism of the resistive memory, that is, the memory function has been completed. The erasing operation 214 and the writing operation 216 are continuously performed in sequence, and the resistive memory element 110 can be operated.

Referring to FIGS. 1 and 2 again, in order to prevent the resistive memory device 110 from forming a wire-shaped conduction path, the current flowing through the resistive memory device 110 continues to rise, even at a high current state. This resistive memory element 110 can be permanently destroyed. In order to prevent the current flowing through the resistive memory device 110 from rising continuously, when the initializing operation 212 and the writing operation 216 are applied to the resistive memory device 110, a limiting current I1 and I3 are appropriately set, as described in 2 is shown to protect the resistive memory element 110. In addition, in the erasing action 214, the filament-like conduction path is broken as the reverse bias voltage increases, so that it is not necessary to set the limiting current, as shown in FIG. 2, wherein the erasing current is I2.

FIG. 3 is a flow chart showing a method of manufacturing a resistive memory according to a preferred embodiment of the present invention, which comprises six step blocks. Referring to FIGS. 1, 2 and 3, in step 312, a substrate 112 having the insulating layer 114 and the lower conductive layer 116 is prepared, and the resistive layer 118 is deposited in step 314, and the metal is deposited in step 324. The oxide layer a (for example, depositing a nano-scale copper oxide film by thermal evaporation), depositing the upper conductive layer 120 in step 316, and forming the filament-like conduction path inside the resistance layer 118 in step 318, The memory function is performed in step 320.

Referring to FIG. 1 again, the metal oxide layer a is formed between the resistance layer 118 and the upper conductive layer 120. The metal oxide layer a is formed by a thermal evaporation method, a co-sputtering method, an electron beam evaporation method, a plasma oxidation method, or other molding methods. Since the metal oxide layer a is easily dissociated from metal ions (for example, copper ions, silver ions or other active metal ions) in an anhydrous gas atmosphere or a dry environment, the operational characteristics of the resistive memory device 110 are in an anhydrous gas atmosphere or dried. Stabilization is formed in the environment to achieve improved operational stability of the resistive memory element 110.

Referring to FIG. 1 again, the copper oxide film of the metal oxide layer a replaces the active metal copper layer of the conventional resistive memory device, that is, the conventional resistive memory does not need to use the active metal as the electrode, so as to achieve the reduction. Manufacturing costs and streamlined process operations. Further, the metal oxide layer a is a film of a mixture of an active metal oxide film or an active metal oxide. For example, the metal oxide layer comprises a film of a sulfide, a film of a nitride or a mixture thereof.

Referring again to FIG. 1, the metal oxide layer a is a single metal oxide layer or a composite metal oxide layer. The metal oxide layer a is a metal oxide film (for example, a copper oxide film), a sulfide film or other metal oxide film. The metal oxide layer a comprises: copper oxide, silver oxide, nickel oxide or any mixture thereof; copper oxide, cuprous oxide, copper, copper sulfide or any mixture thereof; copper sulfide, silver sulfide, nickel sulfide or Any mixture thereof.

Referring to FIGS. 1 and 3 again, for example, the preferred embodiment of the present invention uses the resistive memory device 110 as follows:

The substrate 112 is a P-type wafer, and the substrate 112 is first cleaned by RCA to remove the native oxide layer, particles and organic matter on the wafer, and then the horizontal furnace tube is used with the wet oxidation method to grow 200 nm or other suitable thickness of cerium oxide. [SiO 2 ] to form the insulating layer 114 to prevent leakage of the substrate 112 and to reduce parasitic effects.

Next, after the wet oxidation process is completed, 20 nm or other suitable thickness of titanium [Ti] or titanium nitride is deposited by a multilayer metal sputtering system, an electron beam (E-beam) evaporation system, or other suitable techniques. [TiN] is used as an adhesive layer to adhere the insulating layer 114 and the lower conductive layer 116.

Next, 150 nm or other suitable thickness of tungsten is deposited by a suitable technical means (for example, a chemical vapor deposition system) as the lower conductive layer 116 (ie, the lower conductive electrode), that is, the lower conductive layer 116 is completed. The substrate 112 is shown as step 312 of FIG.

Next, a 20 nm or other suitable thickness of cerium oxide [SiO 2 ] is sputtered by a RF magnetron sputtering machine (RF-Magnetron Sputter) or other techniques as the resistance layer 118, as in step 314 of FIG. Shown.

Conventional resistive memory components are used to directly deposit a suitable thickness of copper [Cu] by a thermal vaporizer or other suitable technique when depositing a conductive layer, as an upper conductive layer, and defined by a metal mask. The area of the upper conductive layer, and it is not possible to perform an electrochemically-switched resistance switching operation in an anhydrous gas environment.

Next, before depositing the upper conductive layer 120, directly deposit a copper oxide [Cu x O] film of a suitable thickness by a thermal vapor deposition machine or other suitable technical means as the metal oxide layer a, as shown in FIG. Step 324 is shown.

Then, a low-active metal or an inert metal such as nickel [Ni] of 200 nm or other suitable thickness is vapor-deposited by a thermal evaporation machine or other technical means to serve as the upper conductive layer 120. And, the area of the upper conductive layer 120 is determined by a metal mask, as shown in step 316 of FIG.

The electrical measurement of the present invention is tested by the HP 4155B semiconductor parameter analyzer, and various electrical analysis is performed by using the automated measurement program developed by the LabVIEW program editing software. The upper conductive layer 120 is connected to the power output terminal, and the lower conductive layer 120 is connected to the power output terminal. The conductive layer 116 is connected to the ground.

Fig. 4 is a view showing the relationship between voltage and current of a conventional resistive memory device for performing a resistance switching operation in an anhydrous gas or a dry environment. Referring to FIG. 4, the conventional resistive memory device performs a resistance switching operation in an anhydrous gas or dry environment, and includes an initialization operation 412, an erasing action 414, and a writing operation 416. When the initialization action 412 is performed on a conventional resistive memory device, the component enters a hard collapse phenomenon. Once the component enters a hard collapse state, it does not operate the component regardless of whether the erase operation 414 or the write operation 416 is performed, that is, the electrochemical resistance memory cannot be transformed by the electrochemical effect in an anhydrous gas environment.

Fig. 5 is a view showing the relationship between the voltage and current of the resistance-switching operation of the resistive memory in the anhydrous gas or dry environment according to the preferred embodiment of the present invention. Referring to FIGS. 1 and 5, the resistive memory device 110 is shown in an anhydrous environment, and the initialization operation 512 is performed. After the initialization operation 512, the erase operation 514 is performed. The write operation 516 is continued to confirm that the resistive memory device 110 can still undergo a resistive transition in an anhydrous gas environment.

Figure 6 shows a resistive memory in accordance with a preferred embodiment of the present invention Schematic diagram of operating voltage in an atmospheric environment. Referring to Figures 1 and 6, it is shown that the resistive memory device 110 has a write voltage 612 and an erase voltage 614 in the atmosphere. In contrast, the resistive memory device 110 has a write voltage 616 and an erase voltage 618 in an anhydrous gas environment. The write voltage 612 and the erase voltage 614 in the atmosphere are not much different from the write voltage 616 and the erase voltage 618 in an anhydrous gas environment. In the preferred embodiment of the present invention, the resistive memory element 110 exhibits no difference in transition characteristics in different atmospheres.

Fig. 7 is a view showing the switching operation between the high and low resistance and the number of stable switching times of the resistive memory in the preferred embodiment of the present invention in an anhydrous gas or dry environment. Referring to Figures 1 and 7, it is shown that through the writing and erasing of the continuous cycle of the component, a high resistance state 712 and a low resistance state 714 are respectively taken out from the cyclic writing process, and the display component can be in the waterless state. The switching between the high resistance state 712 and the low resistance state 714 is stably performed several times in a gaseous environment.

Referring to Figures 1, 4 and 5 again, it is shown that the conventional resistive memory device will not be able to undergo a transition state in an anhydrous gas environment; otherwise, the resistive memory device 110 of the preferred embodiment of the present invention adopts no The active electrode can still be transformed in an anhydrous gas environment, that is, the filamentary path of the inactive electrode (relatively lower active metal electrode or inert metal electrode) of the upper conductive layer 120 can still be obtained from the metal in an anhydrous gas or in a dry state. The copper oxide film of the oxide layer a supplies copper ions. Therefore, the resistive memory device 110 of the preferred embodiment of the present invention is not affected by the ambient atmosphere, and the active metal electrode of the conventional resistive memory device can be replaced by the copper oxide film of the metal oxide layer a.

The above experimental data is preliminary experimental results obtained under specific conditions, which are only used to easily understand or refer to the technical content of the present invention, and other related experiments are still required. The experimental data and its results are not intended to limit the scope of the invention.

The foregoing preferred embodiments are merely illustrative of the invention and the technical features thereof, and the techniques of the embodiments can be carried out with various substantial equivalent modifications and/or alternatives; therefore, the scope of the invention is subject to the appended claims. The scope defined by the scope shall prevail. The copyright limitation of this case is used for the purpose of patent application in the Republic of China.

110‧‧‧Resistive memory components

112‧‧‧Substrate

114‧‧‧Insulation

116‧‧‧lower conductive layer

118‧‧‧resistance layer

120‧‧‧Upper conductive layer

A‧‧‧metal oxide layer

Claims (10)

  1. A resistive memory structure without an active electrode, comprising: a substrate; an insulating layer disposed on the substrate; a lower conductive layer disposed on the insulating layer; and a resistive layer disposed under the substrate On the conductive layer; at least one metal oxide layer disposed on the resistance layer, and the metal oxide layer is a mixture film of an active metal oxide film or an active metal oxide; and an upper conductive layer disposed on the conductive layer Forming a memory element on the metal oxide layer, and the metal oxide layer is formed between the resistance layer and the upper conductive layer; wherein the metal oxide layer provides metal ions to the resistance layer to form a plurality of filamentary paths, thereby forming a plurality of filamentary paths The electrochemical transition of the memory element is formed, and the resistance transition can be continued in the anhydrous gas environment, and the active electrode is not required to be disposed.
  2. A resistive memory structure without an active electrode, comprising: a substrate; an insulating layer disposed on the substrate; a lower conductive layer disposed on the insulating layer; and a resistive layer disposed under the substrate a plurality of metal oxide layers disposed on the resistive layer, wherein the plurality of metal oxide layers are a mixture of an active metal oxide film or an active metal oxide; and an upper conductive layer disposed Depositing a plurality of the metal oxide layers to form a memory device, and a plurality of the metal oxide layers are formed between the resistance layer and the upper conductive layer; wherein the plurality of metal oxide layers provide metal ions to the resistance layer A plurality of filamentary paths are formed, thereby forming an electrochemical transition of the memory element, while continuing the resistance transition in an anhydrous gas environment, and there is no need to provide an active electrode.
  3. According to the resistive memory structure described in claim 1 or 2, The metal oxide layer is formed by a thermal evaporation method, a co-sputtering method, an electron beam evaporation method, or a plasma oxidation method.
  4. The resistive memory structure of claim 1 or 2, wherein the metal oxide layer comprises copper, silver or a combination oxide thereof.
  5. The resistive memory structure of claim 1 or 2, wherein the metal oxide layer comprises a sulfide film or a nitride film.
  6. A method for manufacturing a resistive memory without using an active electrode, comprising: providing a substrate; forming an insulating layer on the substrate; forming a conductive layer on the insulating layer; forming a resistive layer on the lower conductive layer; Forming a metal oxide layer on the resistive layer, and the metal oxide layer is a film of a mixture of an active metal oxide film or an active metal oxide; and forming an upper conductive layer on the metal oxide layer to form a memory a body element, and the metal oxide layer is formed between the resistance layer and the upper conductive layer; wherein the metal oxide layer provides metal ions to the resistance layer to form a plurality of filamentous paths, thereby forming an electrochemical turn of the memory element State, while in the anhydrous gas environment can continue to resist the transition state, and does not need to set the active electrode.
  7. The method of manufacturing a resistive memory according to claim 6, wherein the metal oxide layer is formed by a thermal evaporation method, a co-sputtering method, an electron beam evaporation method, or a plasma oxidation method.
  8. The method of manufacturing a resistive memory according to claim 6, wherein the metal oxide layer comprises copper, silver or a combination oxide thereof.
  9. The method of manufacturing a resistive memory according to claim 6, wherein the metal oxide layer comprises a sulfide film or a nitride film.
  10. The method of manufacturing a resistive memory according to claim 6, wherein the metal oxide layer has a thickness of between 1 and 100 nm.
TW104139724A 2015-11-27 2015-11-27 Resistive random access memory without having an active electrode and manufacturing method thereof TWI611404B (en)

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