TWI570918B - Semiconductor device and method of manufacturing the same - Google Patents

Description

Semiconductor device and method of manufacturing same

The present disclosure relates to a semiconductor device and a method of fabricating the same, and in particular to a semiconductor device having a trench and a method of fabricating the same.

The semiconductor integrated circuit industry has experienced rapid growth over the past few decades. Advances in semiconductor materials and design techniques have made circuits smaller and more complex. Advances in the above materials and design have been achieved due to advances in related process technologies. In the course of semiconductor development, the number of components that can be interconnected per unit area is increasing due to the smaller and smaller size of the smallest components that can be reliably fabricated.

The semiconductor integrated circuit industry has made many developments in an effort to reduce the size of components. However, as the size of the smallest component shrinks, many challenges arise, such as the structural reliability of the device. However, current semiconductor integrated devices are not satisfactory in all respects.

Therefore, the industry still needs a semiconductor device with higher structural reliability.

The present disclosure provides a semiconductor device comprising: a substrate having a first conductivity type; an epitaxial layer disposed on the substrate and having a first conductivity type; a gate electrode disposed on the epitaxial layer; a source region and a drain region On the opposite side of the gate electrode In the epitaxial layer, wherein the source region has a first conductivity type, and the drain region has a second conductivity type, and the first conductivity type is different from the second conductivity type; the trench extends from the upper surface of the epitaxial layer Passing through the source region and extending into the epitaxial layer, wherein the trench has inclined sidewalls and a bottom surface; and the first conductive type connection region has a first conductivity type, wherein the first conductive type connection region surrounds the inclined sidewall of the trench and Contacting a bottom surface of the trench, wherein the first conductive type connection region is electrically connected to the source region and the substrate.

The present disclosure further provides a method for fabricating a semiconductor device, comprising: providing a substrate, the substrate having a first conductivity type; forming an epitaxial layer on the substrate, wherein the epitaxial layer has a first conductivity type; and forming a gate electrode on the epitaxial layer Forming a source region and a drain region in the epitaxial layer on the opposite side of the gate electrode, wherein the source region has a first conductivity type, and the drain region has a second conductivity type, and the first conductivity type and the second conductivity type The conductive type is different; forming a trench extending from the upper surface of the epitaxial layer through the source region and extending into the epitaxial layer, wherein the trench has inclined sidewalls and a bottom surface; and forming a first conductive type connection region, The first conductive type connection region has a first conductivity type, wherein the first conductive type connection region surrounds the inclined sidewall of the trench and contacts the bottom surface of the trench, wherein the first conductive type connection region is electrically connected to the source region and the substrate.

In order to make the features and advantages of the present disclosure more comprehensible, the preferred embodiments are described below, and are described in detail below with reference to the accompanying drawings.

100‧‧‧Base

102‧‧‧The first conductivity type epitaxial layer

102T‧‧‧ upper surface

104‧‧‧ gate dielectric layer

106‧‧‧gate electrode

108‧‧‧First telluride layer

110‧‧‧ source area

112‧‧‧Bungee Area

114‧‧‧ spacer layer

116‧‧‧First heavily doped area

118‧‧‧Second heavily doped area

120‧‧‧ trench

120’‧‧‧ trench

120S‧‧‧ sloping side wall

120’S‧‧‧Vertical sidewall

120B‧‧‧ bottom surface

120’B‧‧‧ bottom surface

120T‧‧‧ upper

122‧‧‧First Conductive Connection Area

122'‧‧‧First Conductive Connection Area

124‧‧‧Doping step

126‧‧‧Source contact

128‧‧‧汲pole contacts

130‧‧‧Second telluride layer

132‧‧‧ Third telluride layer

134‧‧‧ dielectric layer

200‧‧‧Semiconductor device

200'‧‧‧ semiconductor devices

Θ‧‧‧ acute angle

W1‧‧‧Width

W2‧‧‧Width

W3‧‧‧Width

W4‧‧‧Width

W5‧‧‧Width

W6‧‧‧Width

W7‧‧‧Width

D1‧‧ depth

D2‧‧ depth

D3‧‧ depth

D4‧‧ depth

D5‧‧ depth

D6‧‧ depth

Figures 1-4 and 6 are cross-sectional views of various stages of the semiconductor device of the present disclosure in its method of manufacture.

Figure 5 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

Hereinafter, the semiconductor device and the method of manufacturing the same will be described in detail. It will be appreciated that the following description provides many different embodiments or examples for implementing the various aspects of the disclosure. The specific elements and arrangements described below are merely illustrative of the disclosure. Of course, these are only used as examples and not as a limitation of the disclosure. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the disclosure, and are not intended to be a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is on or above a second material layer, the first material layer is in direct contact with the second material layer. Alternatively, it is also possible to have one or more layers of other materials interposed, in which case there may be no direct contact between the first layer of material and the second layer of material.

It must be understood that the elements or devices of the drawings may be in various forms well known to those skilled in the art. In addition, when a layer is "on" another layer or substrate, it may mean "directly" on another layer or substrate, or a layer on another layer or substrate, or between other layers or substrates. Other layers.

In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the drawing to another. It will be understood that if the device of the drawing is flipped upside down, the component described on the "lower" side will become the component on the "higher" side.

Here, the terms "about", "about" and "major" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, there is no specific description of "about", "about", In the case of "almost", the meanings of "about", "about" and "major" may still be implied.

It will be understood that the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or portions, such elements, components, and regions. The layers, and/or portions are not to be limited by the terms, and the terms are used to distinguish different elements, components, regions, layers, and/or parts. Therefore, a first element, component, region, layer, and/or portion discussed below may be referred to as a second element, component, region, layer, and/or without departing from the teachings of the disclosure. section.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning It will be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the context or context of the present disclosure, and should not be in an idealized or overly formal manner. Interpretation, unless specifically defined herein.

The embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the present disclosure are also considered as part of the disclosure. It should be understood that the drawings of the present disclosure are not shown in the form of actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings in order to clearly illustrate the features of the present disclosure. In addition, the structures and devices in the drawings are schematically illustrated in order to clearly illustrate the features of the disclosure.

In this disclosure, relative terms such as "lower", "upper", "horizontal", "vertical", "lower", "above", "top", "bottom", etc. shall be understood as The orientation shown in the paragraph and related schemas. This relative term is used for convenience of description only, and does not mean that the device described therein needs to be in a specific orientation. To manufacture or operate. Terms such as "joining" and "interconnecting", etc., unless otherwise defined, may mean that two structures are in direct contact, or that two structures are not in direct contact, and other structures are provided here. Between the two structures. The term "joining and joining" may also include the case where both structures are movable or both structures are fixed.

It should be noted that the term "substrate" may include the formed elements on the semiconductor wafer and the various film layers overlying the wafer, on which any desired semiconductor components may have been formed, but here Simplify the drawing and only represent it as a flat base. In addition, the "substrate surface" includes the uppermost and exposed film layer on the semiconductor wafer, such as a germanium surface, an insulating layer, and/or metal lines.

The "copper" mentioned in the present disclosure includes copper and its alloys.

The semiconductor device of the embodiment of the present disclosure uses a trench having a slanted side and a first conductive type connection region surrounding the trench to ensure an electrical connection between the source region and the substrate, thereby enhancing the semiconductor device. Structural reliability.

Figures 1-4 and 6 are cross-sectional views of various stages of the semiconductor device of the present disclosure in its method of manufacture. Referring to Figure 1, a substrate 100 is provided having a first conductivity type. The substrate 100 may include: a single crystal structure, a polycrystalline structure or an amorphous structure of germanium or germanium elemental semiconductor; gallium nitride (GaN), silicon carbide, gallium arsenic, gallium phosphide a compound semiconductor such as (gallium phosphide), indium phosphide, indium arsenide or indium antimonide; alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP or GaInAsP or Other suitable materials and/or combinations of the above.

In some embodiments, the first conductivity type is a P-type, and the substrate 100 can be a heavily doped P-type substrate. In the illustrated embodiment, "heavily doped" means a doping concentration in excess of about 10 ¹⁹ /cm ³ , such as a doping concentration of from about 10 ¹⁹ /cm ³ to about 10 ²¹ /cm ³ . However, it will be appreciated by those of ordinary skill in the art that the definition of "heavily doped" can also be determined by the particular device type, technical generation, minimum component size, and the like. Thus, the definition of "heavily doped" is re-evaluated based on technical content and is not limited by the embodiments presented herein.

Referring to FIG. 1, an epitaxial layer 102 is formed on the substrate 100. The epitaxial layer 102 also has a first conductivity type. The epitaxial layer 102 can comprise ruthenium, osmium, iridium and osmium, a III-V compound, or a combination thereof. The epitaxial layer 102 can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), metal organic chemical vapor deposition (MOVPE), plasma enhanced chemical vapor deposition. Plasma-enhanced CVD, remote controlled plasma chemical vapor deposition (RP-CVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE) Formed by chloride vapor phase epitaxy (Cl-VPE) or a similar method.

In some embodiments, when the first conductivity type is a P-type, the epitaxial layer 102 having the first conductivity type is a P-type epitaxial layer, which can be in the reaction gas when the epitaxial layer 102 is deposited. Adding borane (BH ₃ ) or boron tribromide (BBr ₃ ) for in-situ doping, or depositing undoped epitaxial layer 102 first, followed by boron ion or indium ion Perform ion implantation. The epitaxial layer 102 may have a doping concentration of from about 10 ¹⁶ /cm ³ to about 10 ¹⁸ /cm ³ .

Next, a gate dielectric layer 104 can be blanket deposited and placed thereon A layer of conductive material (to form a gate electrode 106, not shown) on the epitaxial layer 102. Next, the conductive material layer is patterned by a lithography and etching process to form a gate electrode 106 disposed on the gate dielectric layer 104 (or disposed on the epitaxial layer 102).

The material of the gate dielectric layer 104 may be tantalum oxide, tantalum nitride, hafnium oxynitride, a high-k dielectric material, or any other suitable dielectric material, or a combination thereof. The material of the high-k dielectric material may be a metal oxide, a metal nitride, a metal halide, a transition metal oxide, a transition metal nitride, a transition metal telluride, a metal oxynitride, Metal aluminate, zirconium silicate, zirconium aluminate. For example, the high-k dielectric material may be LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfO. ₂ , HfO ₃ , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr)TiO ₃ (BST), Al ₂ O ₃ , other high dielectric constants of other suitable materials Dielectric material, or a combination of the above. The gate dielectric layer 104 can be formed by chemical vapor deposition (CVD) or spin coating. The chemical vapor deposition method can be, for example, low pressure chemical vapor deposition (LPCVD). Low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD) Atomic layer deposition (ALD) or other commonly used methods of atomic layer chemical vapor deposition.

The material of the conductive material layer (that is, the material of the gate electrode 106) may be amorphous germanium, polycrystalline germanium, one or more metals, metal nitrides, conductive metals. Oxide, or a combination of the above. The above metals may include, but are not limited to, molybdenum, tungsten, titanium, tantalum, platinum or hafnium. The above metal nitrides may include, but are not limited to, molybdenum nitride, tungsten nitride, titanium nitride, and tantalum nitride. The above conductive metal oxide may include, but is not limited to, ruthenium oxide and indium tin oxide. The material of the conductive material layer can be formed by the aforementioned chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method, for example, in an implementation. For example, an amorphous germanium conductive material layer or a polycrystalline germanium conductive material layer may be deposited by low pressure chemical vapor deposition (LPCVD) at a temperature between 525 and 650 ° C, and may have a thickness ranging from about 1000 Å to about 10000 Å.

Next, a metal deuteration process can be selectively performed to form a first germanide layer 108 on the upper surface of the gate electrode 106. This first germanide layer 108 can further reduce the on-resistance of the device. The material of the first telluride layer 108 may include, but is not limited to, nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, tantalum silicide, platinum telluride. (platinum silicide), erbium silicide, or any other suitable metal halide.

Next, the source region 110 and the drain region 112 are formed in the epitaxial layer 102 on the opposite side of the gate electrode 106. The source region 110 has a first conductivity type, and the drain region 112 has a second conductivity type, and the first conductivity type is different from the second conductivity type.

In some embodiments, when the first conductivity type is a P type and the second conductivity type is an N type, the source region 110 may be a heavily doped P-type source region, and the heavily doped P-type source region The doping concentration may range from about 10 ¹⁷ /cm ³ to about 10 ¹⁹ /cm ³ . The drain region 112 may be a lightly doped N-type drain region, and the lightly doped N-type drain region may have a doping concentration of about 10 ¹⁵ /cm ³ to about 10 ¹⁸ /cm ³ . In addition, the ratio of the doping concentration of the epitaxial layer 102 to the doping concentration of the lightly doped N-type drain region may be greater than about 2 orders of magnitude (ie, greater than about 100 times).

The source region 110 and the drain region 112 can be formed by an ion implantation step. For example, in an embodiment, when the source region 110 is a P-type source region 110 and the drain region 112 is an N-type drain region 112, the P-type source region 110 may be predetermined to be formed in the epitaxial layer 102. The region is implanted with boron ions, indium ions or boron difluoride ions (BF ₂ ⁺ ) to form a P-type source region 110, and a region in which the N-type drain region 112 is predetermined to be formed in the epitaxial layer 102 is implanted. Phosphorus ions or arsenic ions form an N-type drain region 112.

In some embodiments, as shown in FIG. 1, the source region 110 and the drain region 112 extend only from a portion of the upper surface 102T of the epitaxial layer 102 into the epitaxial layer 102. The width W1 of the source region 110 is smaller than the width W3 of the epitaxial layer 102, and the width W2 of the drain region 112 is also smaller than the width W3 of the epitaxial layer 102. Moreover, in some embodiments, the source region 110 and the drain region 112 extend only a portion of the depth of the epitaxial layer 102. That is, the depth D1 of the source region 110 is smaller than the depth D3 of the epitaxial layer 102, and the depth D2 of the drain region 112 is also smaller than the depth D3 of the epitaxial layer 102. In addition, the source region 110 and the drain region 112 both extend slightly into the epitaxial layer 102 under the gate electrode 106.

Next, referring to FIG. 2, a first heavily doped region 116 is formed in the source region 110, and a second heavily doped region 118 is formed in the drain region 112. The first heavily doped region 116 and the second heavily doped region 118 have a second conductivity type. This first heavily doped region 116 and the second heavily doped region 118 can be formed by an ion implantation step. For example, in an embodiment, when the second conductivity type is N-type, phosphorus ions may be implanted in the region of the epitaxial layer 102 where the first heavily doped region 116 and the second heavily doped region 118 are to be formed. Arsenic ions form the first heavily doped region 116 and the second heavily doped region 118.

Moreover, the ratio of the doping concentration of the first heavily doped region 116 to the doping concentration of the source region 110 can be greater than about two orders of magnitude (ie, greater than about 100 times). The doping concentration of the second heavily doped region 118 is greater than the doping concentration of the drain region 112.

Next, referring to FIG. 2, a spacer layer 114 is formed on the gate electrode 106 and a portion of the source region 110 and the drain region 112 in compliance. The spacer layer 114 may be made of yttrium oxide/tantalum nitride/yttria (ONO), tantalum nitride/yttria (NO), tantalum oxide, tantalum nitride, or any other suitable material, or a combination thereof. . The spacer layer 114 can be formed by chemical vapor deposition (CVD). The chemical vapor deposition method can be, for example, low pressure chemical vapor deposition (LPCVD) or low temperature chemical vapor deposition ( Low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer chemical vapor deposition Atomic layer deposition (ALD) or other commonly used methods.

In some embodiments, as shown in FIG. 2, the first heavily doped region 116 extends only from a portion of the upper surface 102T of the source region 110 into the epitaxial layer 102. The width W4 of the first heavily doped region 116 is less than the width W1 of the source region 110. Moreover, in some embodiments, the first heavily doped region 116 extends only a portion of the depth of the source region 110. That is, the depth D4 of the first heavily doped region 116 is less than the depth of the source region 110. D1. Moreover, the first heavily doped region 116 extends slightly into the epitaxial layer 102 below the spacer layer 114.

Similarly, in some embodiments, as shown in FIG. 2, the second heavily doped region 118 extends only from a portion of the upper surface 102T of the drain region 112 into the epitaxial layer 102. The width W5 of the second heavily doped region 118 is less than the width W2 of the drain region 112. Moreover, in some embodiments, the second heavily doped region 118 extends only a portion of the depth into the drain region 112. That is, the depth D5 of the second heavily doped region 118 is less than the depth D2 of the drain region 112. Moreover, this second heavily doped region 118 extends slightly into the epitaxial layer 102 below the spacer layer 114.

In some embodiments, as shown in FIG. 2, the source region 110 completely surrounds the first heavily doped region 116 except for the side of the upper surface 102T. The drain region 112 completely surrounds the second heavily doped region 118 except for the side of the upper surface 102T.

Next, referring to FIG. 3, trenches 120 are formed in the epitaxial layer 102. This trench 120 extends from the upper surface 102T of the epitaxial layer 102 through the source region 110 and into the epitaxial layer 102. In detail, the trench 120 extends through the first heavily doped region 116 and the source region 110 and stops in the epitaxial layer 102. The trench 120 has a sloped sidewall 120S and a bottom surface 120B, and the sloped sidewall 120S of the trench 120 intersects the bottom surface 120B of the trench 120 and is at an acute angle θ as shown in FIG. In other words, the angle between the inclined side wall 120S and the bottom surface 120B is not 90 degrees.

In detail, the width W6 of the upper portion 120T of the trench 120 (or the width W6 of the trench 120 on the same horizontal line as the upper surface 102T of the epitaxial layer 102) is wider than the width W7 of the bottom surface 120B of the trench 120. In other words, the groove 120 is a tapered shape.

In some embodiments, as shown in Figure 3, a portion of the epitaxial layer 102 is removed to form trenches 120. The method of removing a portion of the epitaxial layer 102 includes forming a photoresist pattern layer (not shown) on the epitaxial layer 102 to expose a portion of the epitaxial layer 102 to be removed. The photoresist pattern layer can be formed by photolithography, immersion lithography, ion-beam writing, or other suitable technique. For example, optical lithography includes spin coating, soft baking, exposure, post exposure, development, cleaning, drying, and other suitable processes.

Next, the exposed portion of the epitaxial layer 102 can be removed by dry etching, wet etching, or a combination thereof to form the trench 120 having the sloped sidewalls 120S. This wet etch can include immersion etching, spray etching, combinations of the above, or other suitable dry etch. The dry etching step includes capacitively coupled plasma etching, inductively coupled plasma etching, spiral plasma etching, electron cyclotron resonance plasma etching, combinations of the foregoing, or other suitable dry etching. The dry etch step may stop etching after a period of time to leave a local epitaxial layer 102. Therefore, only a portion of the epitaxial layer 102 is removed to form the trenches 120. In addition, any of the photoresist pattern layers (not shown) may be removed by wet stripping, plasma ashing, or a combination thereof.

Moreover, in some embodiments, as shown in FIG. 3, the trenches 120 extend only from the first heavily doped region 116 into the epitaxial layer 102. The maximum width W6 of the trench 120 is less than the width W4 of the first heavily doped region 116. Moreover, in some embodiments, trenches 120 extend through source region 110 and only into portions of epitaxial layer 102. In other words, the depth D6 of the trench 120 is greater than the depth D1 of the source region 110, but less than the depth D3 of the epitaxial layer 102.

Next, referring to FIG. 4, forming a first guide having a first conductivity type The electrical connection region 122 is in the epitaxial layer 102 and the substrate 100. The first conductive type connection region 122 can be formed by the doping step 124. This doping step 124 is doped to the region of the epitaxial layer 102 corresponding to the trench 120. The doping concentration of the first conductive type connection region 122 is higher than the doping concentration of the source region 110 and the epitaxial layer 102. Since the trench 120 has the inclined sidewall 120S, the first conductive type connection region 122 can not only contact the bottom surface 120B of the trench 120, but also the inclined sidewall 120S of the trench 120, and can thereby electrically connect the substrate 100 and the adjacent The source region 110 of the sloped sidewall 120S of the trench 120.

Fig. 5 is a cross-sectional view showing a semiconductor device 200' according to another embodiment of the present invention. The embodiment shown in Fig. 5 differs from the embodiment of Fig. 4 in that the trench of the semiconductor device of Fig. 5 has vertical sidewalls instead of inclined sidewalls. In other words, the vertical sidewall 120'S of the trench 120' shown in Fig. 5 is perpendicular or orthogonal to the bottom surface 120'B. It should be noted that elements or layers that are the same or similar to those in the foregoing will be denoted by the same or similar reference numerals, and the materials, manufacturing methods and functions thereof are the same or similar to those described above, and therefore will not be described later. Narration.

As shown in Fig. 5, since the trench 120' has a vertical sidewall 120'S instead of a slanted sidewall, the first conductive type connection region 122' cannot surround the entire vertical sidewall 120'S, and thus cannot contact the source region 110. Therefore, in Fig. 5, the source region 110 cannot be electrically connected to the substrate 100 by the first conductive type connection region 122', and thus causes a problem of device reliability. The above reliability problem is also referred to as an unclamped inductive switching issue.

Compared to FIG. 5, since the trench 120 in FIG. 4 has the inclined sidewall 120S, the first conductive type connection region 122 may surround the inclined sidewall 120S of the entire trench 120, and thus may contact the source region 110. Therefore, the source region 110 can be electrically connected to the substrate 100 by the first conductive type connection region 122, and thereby the lifting device can be Reliability.

Continuing to refer to FIG. 4, in some embodiments, the acute angle θ of the sloped sidewall 120S of the trench 120 and the bottom surface 120B may be from about 45 degrees to about 88 degrees, such as from about 60 degrees to about 70 degrees. It should be noted that if the acute angle θ is too large, for example, greater than 88 degrees, the first conductive type connection region 122 cannot effectively contact the source region 110, so that the source region 110 cannot be electrically connected by the first conductive type connection region 122. Connecting to the substrate 100 can result in problems with device reliability. However, if the acute angle θ is too small, for example, less than 45 degrees, the trench 120 may occupy a large area of the semiconductor device, which may hinder the miniaturization of the semiconductor device.

In some embodiments, referring to FIG. 4, the first conductivity type connection region 122 can extend from the source region 110 into the substrate 100. In detail, in some embodiments, the first conductive type connection region 122 may extend into the substrate 100 from the upper surface 102T of the epitaxial layer 102.

Next, referring to FIG. 6, a source contact 126 and a drain contact 128 are formed. The source contact 126 is electrically connected to the first heavily doped region 116 and the source region 110, and the drain contact 128 is electrically connected to the second heavily doped region 118 and the drain region 112.

The materials of the source contact 126 and the drain contact 128 may each independently include, but are not limited to, copper, aluminum, molybdenum, tungsten, titanium, tantalum. , platinum or hafnium. The material of the source contact 126 and the drain contact 128 may be by the aforementioned chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition. The way is formed.

Referring to FIG. 6, in some embodiments, the source contact 126 can be filled. Into the trench 120, the portion of the source contact 126 disposed in the trench 120 is compliant with the inclined sidewall 120S of the trench 120 and the bottom surface 120B, as shown in FIG.

Then, a metal deuteration process is selectively performed to form a second vaporization layer 130 between the source contact 126 and the trench 120, and at the drain contact 128 and the second heavily doped region 118. A third vaporization layer 132 is formed therebetween. In other words, the second germanide layer 130 is disposed between the portion of the source contact 126 located in the trench 120 and the sloped sidewall 120S of the trench 120 and the bottom surface 120B. The second germanide layer 130 and the third germanide layer 132 can further reduce the on-resistance of the device.

The materials of the second vaporization layer 130 and the third vaporization layer 132 may include, but are not limited to, nickel silicide, cobalt silicide, tungsten tungsten, titanium silicide, and germanium. Tantalum silicide, platinum silicide, erbium silicide, or any other suitable metal halide.

Furthermore, a dielectric layer 134 can be formed on the source contact 126 in the trench 120, and a portion of the source contact 126 disposed in the trench 120 is disposed between the dielectric layer 134 and the trench 120. The material of the dielectric layer 134 may include, but is not limited to, hafnium oxide, tantalum nitride, hafnium oxynitride, or any other suitable material, or a combination thereof. The dielectric layer 134 can be formed by chemical vapor deposition (CVD), which can be, for example, low pressure chemical vapor deposition (LPCVD) or low temperature chemical vapor deposition ( Low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (plasma enhanced chemical) Vapor deposition (PECVD), atomic layer deposition (ALD) or other commonly used methods.

Referring to FIG. 6, the semiconductor device 200 includes a substrate 100 having a first conductivity type, an epitaxial layer 102 having a first conductivity type disposed on the substrate 100, and a gate electrode 106 disposed on the epitaxial layer 102. The semiconductor device 200 further includes a source region 110 and a drain region 112 disposed in the epitaxial layer 102 on the opposite side of the gate electrode 106. The source region 110 has a first conductivity type, and the drain region 112 has a second conductivity type, and the first conductivity type is different from the second conductivity type. The semiconductor device 200 further includes a trench 120 extending from the upper surface 102T of the epitaxial layer 102 through the source region 110 and extending into the epitaxial layer 102, and the trench 120 has a sloped sidewall 120S and a bottom surface 120B. The semiconductor device 200 further includes a first conductive type connection region 122 having a first conductivity type. This first conductive type connection region 122 surrounds the inclined sidewall 120S of the trench 120 and contacts the bottom surface 120B of the trench 120. The first conductive type connection region 122 is electrically connected to the source region 110 and the substrate 100. The inclined sidewall 120S of the trench 120 intersects the bottom surface 120B of the trench 120 and has an acute angle θ, wherein the acute angle θ is 45 degrees to 88 degrees.

The semiconductor device 200 can further include a first heavily doped region 116 disposed in the source region 110. The first heavily doped region 116 has a second conductivity type, and the trench 120 can extend through the first heavily doped region 116 in the source region 110. The semiconductor device 200 can further include a second heavily doped region 118 disposed in the drain region 112, and the second heavily doped region 118 has a second conductivity type.

The semiconductor device 200 can further include a source contact 126. The source contact 126 is filled in the trench 120 and electrically connected to the first heavily doped region 116 and the source region 110. The semiconductor device 200 may further include a drain contact 128 (drain contact), the drain contact 128 is electrically connected to the second heavily doped region 118 and the drain region 112.

The semiconductor device 200 further includes a dielectric layer 134 disposed on the source contact 126 of the trench 120, and a portion of the source contact 126 disposed in the trench 120 is disposed on the dielectric layer 134 and the trench 120. between.

The semiconductor device 200 may further include a first germanide layer 108 disposed on the gate electrode 106, a second germanide layer 130 disposed between the source contact 126 and the trench 120, and a drain contact 128. A third germanide layer 132 is formed between the second heavily doped region 118.

In addition, it should be noted that although in the above embodiments, the first conductivity type is P type and the second conductivity type is N type, however, those skilled in the art can understand the first conductivity. The type can also be N-type, while the second conductivity type is P-type.

In summary, since the trench of the semiconductor device of the present disclosure has inclined sidewalls, the first conductive type connection region can surround the inclined sidewall of the trench and thus can contact the source region. Therefore, the source region can be electrically connected to the substrate by the first conductive type connection region, and thereby the reliability of the device can be improved.

It should be noted that the component sizes, component parameters, and component shapes described above are not limitations of the disclosure. Those of ordinary skill in the art can adjust these settings according to different needs. Further, the semiconductor device and the method of manufacturing the same according to the present disclosure are not limited to the state illustrated in FIGS. 1-6. The disclosure may include only any one or more of the features of any one of the Figures 1-6. In other words, not all illustrated features must be simultaneously implemented in the semiconductor device and method of fabricating the same.

Although the embodiments of the present disclosure and its advantages are disclosed above, it should be understood that those skilled in the art can make changes, substitutions, and refinements without departing from the spirit and scope of the disclosure. In addition, the scope of the disclosure is not limited to the processes, machines, manufactures, compositions, devices, methods, and steps in the specific embodiments described in the specification, and those of ordinary skill in the art may disclose the disclosure It is understood that the processes, machines, manufactures, compositions, devices, methods, and procedures that are presently or in the future may be used in accordance with the present disclosure as long as they can perform substantially the same function or achieve substantially the same results in the embodiments described herein. Accordingly, the scope of protection of the present disclosure includes the above-described processes, machines, manufacturing, material compositions, devices, methods, and procedures. In addition, each patent application scope constitutes an individual embodiment, and the scope of protection of the disclosure also includes a combination of the scope of the patent application and the embodiments.

100‧‧‧Base

102‧‧‧The first conductivity type epitaxial layer

102T‧‧‧ upper surface

104‧‧‧ gate dielectric layer

106‧‧‧gate electrode

108‧‧‧First telluride layer

110‧‧‧ source area

112‧‧‧Bungee Area

114‧‧‧ spacer layer

116‧‧‧First heavily doped area

118‧‧‧Second heavily doped area

120‧‧‧ trench

120S‧‧‧ sloping side wall

120B‧‧‧ bottom surface

122‧‧‧First Conductive Connection Area

126‧‧‧Source contact

128‧‧‧汲pole contacts

130‧‧‧Second telluride layer

132‧‧‧ Third telluride layer

134‧‧‧ dielectric layer

200‧‧‧Semiconductor device

Θ‧‧‧ acute angle

Claims (20)

A semiconductor device comprising: a substrate having a first conductivity type; an epitaxial layer disposed on the substrate and having the first conductivity type; a gate electrode disposed on the epitaxial layer; a source a region and a drain region disposed in the epitaxial layer on the opposite side of the gate electrode, wherein the source region has the first conductivity type, and the drain region has a second conductivity type, and the a conductive type is different from the second conductive type; a trench extending from an upper surface of the epitaxial layer through the source region and extending into the epitaxial layer, wherein the trench has a sloped sidewall and a trench a bottom surface; and a first conductive type connection region, wherein the first conductive type connection region surrounds the inclined sidewall of the trench and contacts the bottom surface of the trench, wherein the first conductive type connection region is electrically connected to the bottom surface a source region and the substrate, wherein the first conductive type connection region is a doped region having the first conductivity type and located in the epitaxial layer, and the first conductive type connection region directly contacts the source region. The semiconductor device of claim 1, wherein the inclined sidewall of the trench intersects the bottom surface of the trench and is at an acute angle, wherein the acute angle is 45 degrees to 88 degrees. The semiconductor device of claim 1, wherein an upper portion of the trench has a width wider than a width of the bottom surface of the trench. The semiconductor device of claim 1, wherein the first conductive type connection region extends from the source region into the substrate. The semiconductor device according to claim 4, wherein the first guide An electrical connection region extends into the substrate from the upper surface of the epitaxial layer. The semiconductor device of claim 1, further comprising: a first heavily doped region disposed in the source region, wherein the first heavily doped region has the second conductivity type; a double doped region disposed in the drain region, wherein the second heavily doped region has the second conductivity type; wherein the trench extends through the first heavily doped region in the source region. The semiconductor device of claim 6, further comprising: a source contact, filled in the trench and electrically connected to the first heavily doped region and the source region; And a drain contact electrically connected to the second heavily doped region and the drain region. The semiconductor device of claim 7, wherein the portion of the source contact disposed in the trench conforms to the inclined sidewall and the bottom surface of the trench; wherein the semiconductor device further comprises: The dielectric layer is disposed on the source contact in the trench, wherein a portion of the source contact disposed in the trench is disposed between the dielectric layer and the trench. The semiconductor device of claim 1, further comprising: a first germanide layer disposed on the gate electrode. The semiconductor device of claim 7, further comprising: a second germanide layer disposed between the source contact and the trench; and a third germanide layer disposed on the drain A junction between the junction and the second heavily doped region. A method of fabricating a semiconductor device, comprising: Providing a substrate having a first conductivity type; forming an epitaxial layer on the substrate, wherein the epitaxial layer has the first conductivity type; forming a gate electrode on the epitaxial layer; forming a source a pole region and a drain region in the epitaxial layer on the opposite side of the gate electrode, wherein the source region has the first conductivity type, and the drain region has a second conductivity type, and the first The conductive type is different from the second conductive type; forming a trench extending from an upper surface of the epitaxial layer through the source region and extending into the epitaxial layer, wherein the trench has a tilt a sidewall and a bottom surface; and forming a first conductive type connection region, wherein the first conductive type connection region surrounds the inclined sidewall of the trench and contacts the bottom surface of the trench, wherein the first conductive type connection region Electrically connecting the source region and the substrate, wherein the first conductive type connection region is a doped region having the first conductivity type and located in the epitaxial layer, and the first conductive type connection region directly contacts the source Polar zone. The method of fabricating a semiconductor device according to claim 11, wherein the inclined sidewall of the trench intersects the bottom surface of the trench and is at an acute angle, wherein the acute angle is 45 degrees to 88 degrees. The method of fabricating a semiconductor device according to claim 11, wherein a width of an upper portion of the trench is wider than a width of the bottom surface of the trench. The method of fabricating a semiconductor device according to claim 11, wherein the first conductive type connection region extends from the source region into the substrate. The method of fabricating a semiconductor device according to claim 14, wherein the first conductive type connection region extends into the substrate from the upper surface of the epitaxial layer. The method of fabricating a semiconductor device according to claim 11, further comprising: forming a first heavily doped region in the source region, wherein the first heavily doped region has the second conductivity type; Forming a second heavily doped region in the drain region, wherein the second heavily doped region has the second conductivity type; wherein the trench extends through the first heavily doped region in the source region . The method of manufacturing the semiconductor device of claim 16, further comprising: forming a source contact, wherein the source contact is filled in the trench and electrically connected to the first a heavily doped region and the source region; and a drain contact is formed, wherein the drain contact is electrically connected to the second heavily doped region and the drain region. The method of fabricating a semiconductor device according to claim 17, wherein: the portion of the source contact disposed in the trench conforms to cover the inclined sidewall and the bottom surface of the trench; wherein the semiconductor device The manufacturing method further includes: forming a dielectric layer on the source contact in the trench, wherein a portion of the source contact disposed in the trench is disposed between the dielectric layer and the trench . The method of fabricating a semiconductor device according to claim 11, further comprising: forming a first germanide layer on the gate electrode. The method for manufacturing a semiconductor device according to claim 17 of the patent application, The method includes: forming a second germanide layer between the source contact and the trench; and forming a third germanide layer between the drain contact and the second heavily doped region.