TWI570744B - Integrated circuit, system including the same, and operation method of the system - Google Patents

Description

Integrated circuit, system including the integrated circuit, and operating method of the system

Illustrative embodiments of the present invention relate to an integrated circuit chip, and more particularly to a technique for setting the optimal latency for the performance of an integrated circuit chip.

The present application claims priority to Korean Patent Application No. 10-2011-0081, filed on Aug.

Integrated circuit wafers communicate with adjacent wafers by transmitting data or signals or receiving data or signals from adjacent wafers. For example, when the memory controller applies a read command to the memory, the memory transfers the stored data to the memory controller. Here, the memory can output data to the memory controller in the case of a delay, wherein in response to the read command, the delay can occur when the stored data is retrieved and prepared for output.

When wafer A and wafer B interact with each other, wafer A requests wafer B to perform the desired operation. There is a delay until the wafer B performs an operation in response to a request from the wafer A. This delay is called latency. For example, when the CAS latency CL is set to 7 for the instruction between the memory and the memory controller and the memory controller applies the read command to the memory, the memory is from the time when the read command is applied. Data is transferred to the memory controller after 7 clocks.

According to recent trends, integrated circuit chips can operate at several power supply voltage levels. However, when the power supply voltage of the integrated circuit chip is changed The operating speed of the integrated circuit chip can be changed at any time. Here, it is useful to optimally set the latency between wafers regardless of the change in operating speed.

One embodiment of the present invention is directed to a configuration in which a master wafer applies an operational command to a controlled wafer and sets an optimal latency based on information regarding the operating speed of the controlled wafer.

According to an example, the master wafer can detect a change in the operating speed of the controlled wafer, the change originating from a change in the power supply voltage applied to the controlled wafer; and setting the operation for the controlled wafer An optimum potential for each of the power supply voltages.

In accordance with an embodiment of the present invention, a system includes: a first wafer configured to supply a training command; and a second wafer configured to be responsive to the training instruction to perform an operation A measurement time is transmitted to the first wafer.

In accordance with another embodiment of the present invention, an integrated circuit die includes: a decoder configured to generate a signal by decoding one or more command signals; an internal circuit configured to perform a corresponding Operating in one of the training instructions; and a storage circuit configured to store the time measured for performing one of the operations.

According to still another embodiment of the present invention, a method for operating an integrated circuit chip includes: supplying a first power supply voltage to the integrated circuit wafer; and the first power supply voltage is applied to the integrated circuit chip Simultaneously outputting a training command to the integrated circuit chip; measuring a first operation of the integrated circuit chip for performing an operation corresponding to one of the training instructions Storing the first operation time; supplying a second power supply voltage to the integrated circuit chip; supplying the training command to the integrated circuit while the integrated circuit chip is operating with the second power supply voltage a wafer; measuring a second operation time of the integrated circuit chip for performing an operation corresponding to one of the training instructions; and storing the second operation time.

In accordance with still another embodiment of the present invention, a memory system includes: a memory configured to transmit a time from when a training command is outputted to the memory to a time in response to the output of the training command A measurement data output time; and a memory controller configured to output the training command to the memory and receive the data from the memory.

In accordance with still another embodiment of the present invention, a memory includes: a memory cell array region configured to store data; an instruction decoder configured to output a training by decoding one or more signals An instruction circuit configured to generate a data output signal by delaying the training instruction; a data output circuit configured to output from the memory cell array region in response to the data output signal Reading the data; a measuring circuit configured to measure a data output time from a time when the training command is output to a time when the data output circuit outputs the data; and a storage circuit It is configured to store the measured data output time.

Exemplary embodiments of the present invention are described in more detail below with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. The fact is that these embodiments are provided to The present invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout the drawings, like reference numerals refer to like parts throughout the claims

1 is a block diagram showing an integrated circuit system including a first wafer and a second wafer in accordance with a first embodiment of the present invention.

Referring to FIG. 1, the integrated circuit system includes a first wafer 110, a second wafer 120, and a power supply 130.

The first wafer 110 is a master wafer that instructs the second wafer 120 to perform a specific operation, and the second wafer 120 is a controlled wafer that performs an operation corresponding to the instructions of the first wafer 110. For example, the first wafer 110 can be a memory controller, and the second wafer 120 can be a memory that performs a read operation or a write operation under the instruction of the memory controller.

The power supply 130 supplies power supply voltages VDD1 and VDD2 to the first wafer 110 and the second wafer 120. The level of the first power supply voltage VDD1 supplied from the power supply 130 to the first wafer 110 and the level of the second power supply voltage VDD2 supplied from the power supply 130 to the second wafer 120 may be the same or different from each other. The levels of the first power supply voltage VDD1 and the second power supply voltage VDD2 supplied by the power supply 130 may be changed in response to a control signal from the first wafer 110. According to another example, the level of the first power supply voltage VDD1 supplied from the power supply 130 to the first wafer 110 may be constant, and the first wafer 110 may control the power supply 130 to change the supply to the second wafer 120. The level of the second power supply voltage VDD2. In the drawings, "CONTROL" means determining the bit of the power supply provided by the power supply 130 under the control of the first wafer 110. quasi.

The first wafer 110 outputs a training command to perform a training operation on the operation X of the second wafer 120. Here, operation X may be any operation performed by the second wafer 120 upon receiving an instruction from the first wafer 110. This operation is represented in the drawing by the X training instruction. The second wafer 120 then performs operation X, measures the time it takes to perform the operation X (referred to as the time for performing the operation X), and transmits the measurement result to the first wafer 110. This interaction between the first wafer 110 and the second wafer 120 is repeated while changing the level of the second power supply voltage VDD2 applied to the second wafer 120. The first wafer 110 may then determine a manner of changing the time of the second wafer 120 for performing the operation X according to the second power supply voltage VDD2.

The second wafer 120 can transmit a signal corresponding to the "time for performing the operation X" to the first wafer 110 in the following two methods.

(1) Whenever the first wafer 110 applies the X training command to the second wafer 120, the second wafer 120 measures the time for performing the operation X, and transmits the "time for performing the operation X" to the first Wafer 110. In other words, even in the case where there is no individual instruction from the first wafer 110 to the second wafer 120 to transmit a signal corresponding to the time for performing the operation X, the second wafer 120 ends measuring it for performing the operation X. At time, the second wafer 120 still automatically transfers the time for performing the operation X to the first wafer 110.

(2) When the first wafer 110 applies an X training instruction to the second wafer 120, the second wafer 120 measures the time for performing the operation X and internally stores the measured time for performing the operation X, and When the first wafer 110 transmits an operation time read command to the second wafer 120 to transfer the time for performing the operation X At the time, the second wafer 120 transfers the stored time for performing the operation X.

Table 1 below exemplarily shows the time for performing the operation X measured according to the level of the second power supply voltage VDD2. In Table 1, the unit for the time at which operation X is performed may be any suitable time unit for quantifying the time. For example, the unit can be ms, μs, or the number of clocks.

When the first wafer 110 receives the information shown in Table 1, the first wafer 110 can determine the time of the second wafer 120 for performing the operation X. Therefore, the first wafer 110 can easily control the latency of the operation X of the second wafer 120. For example, when the second power supply voltage VDD2 of the second wafer 120 is 1.0 V, the first wafer 110 sets the latency of the operation X of the second wafer 120 to a value of 9 or more units. Here, the latency of operation X means the total time taken by the second wafer 120 to transfer the resulting value of the operation X to the first wafer 110 from the time the first wafer 110 gives the second wafer 120 instruction to perform the operation X. When the second power supply voltage VDD2 of the second wafer 120 is 1.3 V, the first wafer 110 sets the latency of the operation X of the second wafer 120 to a value of 6 or more units. Here, even if the second power supply voltage VDD2 of the second wafer 120 is changed, the first wafer 110 can consistently optimize the latency value of the operation X of the second wafer 120.

In FIG. 1, information transmitted between the first wafer 110 and the second wafer 120 for the purpose of determining the time of the second wafer 120 for performing the operation X by the first wafer 110 is illustrated. The "X training command" and the "operation time reading command" transmitted from the first wafer 110 to the second wafer 120 may be transmitted via a command channel or a control channel including a plurality of signal lines, and transmitted from the second wafer 120 to the first The "time for performing operation X" of the wafer 110 can be transmitted via a data channel or a control channel. Here, regardless of the type of data or control channel, the "X training command" and the "operation time reading command" are transmitted from the first wafer 110 to the second wafer 120, and "the time for performing the operation X" from the second wafer 120 is transferred to the first wafer 110.

The power supply voltage level information "VDD INFO" transmitted from the first wafer 110 to the second wafer 120 in FIG. 1 is information on the level of the second power supply voltage VDD2 currently applied to the second wafer 120.

FIG. 2 is a block diagram illustrating the second wafer 120 shown in FIG. 1.

Referring to FIG. 2, the second wafer 120 includes buffers 201 to 203, an instruction decoder 210, a case decoder 220, a circuit 230 for performing operation X, a counter 240, a storage circuit 250, and an output circuit 260.

The buffers 201 to 203 receive signals transmitted from the outside of the second wafer 120. The first buffer 201 receives one or more command signals CMD transmitted from the first wafer 110. In the drawing, "X M" indicates that there are M number of command signals. The second buffer 202 receives one or more control signals transmitted from the first wafer 110. In the figure, "X N" indicates that there are N number of control signals. The third buffer 203 receives the clock CLK transmitted from the first wafer 110 or another external wafer.

The instruction decoder 210 outputs an "X training instruction" by decoding one or more instruction signals CMD input via the first buffer 201 to perform a training operation for the operation X. Further, the command decoder 210 outputs the operation time read command "TIME RD" by decoding one or a plurality of command signals CMD input via the first buffer 201. The instruction decoder 210 decodes not only the X training instruction and the operation time read instruction TIME RD, but also an instruction that directs the operation to be performed by the second wafer 120, such as an instruction to perform the operation X. However, further description of the instructions is not necessary to explain the exemplary embodiments of the invention, and no such instructions are illustrated in the drawings.

The status decoder 220 outputs the power supply voltage level information "VDD INFO" by decoding one or more control signals input via the second buffer 202, the information "VDD INFO" indicating the current application to the second wafer 120. The level of the two power supply voltage VDD2.

The circuit 230 for performing the operation X is a circuit that performs the operation X under the instruction of the first wafer 110. When the instruction decoder 210 outputs the X training instruction, the circuit 230 for performing the operation X performs the operation X. In other words, when the instruction decoder 210 outputs an instruction to instruct the execution of the operation X, and when the instruction decoder 210 outputs the X training instruction, the circuit 230 for performing the operation X performs the same operation. The signal output from circuit 230 for performing operation X is the result obtained from circuit 230 for performing operation X after performing operation X in response to the X training instruction. For example, if the circuit 230 for performing operation X is a circuit for performing an operation based on a particular equation, then when the X training instruction is received, the circuit 230 for performing operation X begins based on a particular equation. Operation. When the circuit 230 for performing the operation X ends the operation, the result of the output operation of the circuit 230 for performing the operation X is taken as the output signal OUT. When the instruction decoder 210 outputs an instruction to perform operation X, the circuit 230 for performing operation X operates in the same manner.

Counter 240 is a circuit for measuring the time for performing operation X of circuit 230 for performing operation X. The counter 240 counts the number of times the clock CLK is enabled from the time when the X training command is enabled to the output signal OUT for outputting the circuit 230 of the operation X, and generates the time information TIME<0:3>. Here, according to an example, the time information TIME<0:3> is 4 bits.

The storage circuit 250 stores the time information TIME<0:3> measured in the counter 240. The storage circuit 250 also receives the power supply voltage level information VDD INFO, and the storage circuit 250 can match the time information TIME<0:3> with the power supply voltage level information VDD INFO and store the two kinds of information. In other words, the time TIME<0:3> and the power supply voltage information for performing the operation X as shown in Table 1 can be matched with each other and stored together in the storage circuit 250. When the operation time read command TIME RD is transferred to the storage circuit 250, the information stored in the storage circuit 250 is transferred to the output circuit 260, and the output circuit 260 transmits the information to the first wafer 110. During normal operation (i.e., not a training operation), the output circuit 260 transmits an output signal OUT generated by performing the operation X in the circuit 230 for performing the operation X to the first wafer 110.

3 is a flow chart illustrating the operation of the integrated circuit system shown in FIGS. 1 and 2. Referring to Figure 3, the integrated circuit system shown in Figures 1 and 2 will be described. The overall operation of the system.

In step S310, a second power supply voltage VDD2 having a first level (for example, 1.0 V) is applied to the second wafer 120. As described above, the level of the second power supply voltage VDD2 applied to the second wafer 120 is determined by the first wafer 110 controlling the power supply 130.

While the second wafer 120 is operating with the second power supply voltage VDD2 having the first level (for example, 1.0 V), the processing procedures of steps S311 to S313 are performed. In step S311, an X training instruction indicating the measurement of the time for performing the operation X is applied from the first wafer 110 to the second wafer 120. In step S312, the second wafer 120 internally performs an operation X and measures the time for performing the operation X. As described earlier with reference to Fig. 2, the time for performing operation X is measured from the time when the X training command is applied to the time at which the output signal OUT for the circuit 230 of operation X is output. In step S313, the time for performing the operation X measured in step S312 is stored in the storage circuit 250 inside the second wafer 120. At this time, the operation of measuring the amount of time taken by the second wafer 120 to perform the operation X at the second power supply voltage VDD2 having the first level (for example, 1.0 V) is terminated.

In step S320, the level of the second power supply voltage VDD2 applied to the second wafer 120 is changed from a first level (for example, 1.0 V) to a second level (for example, 1.2 V). The change in the level of the second power supply voltage VDD2 applied to the second wafer 120 is controlled by a control signal/instruction from the first wafer 110 to the power supply 130.

Here, when the second wafer 120 is operated with the second power supply voltage VDD2 having the second level (for example, 1.2 V), steps S321 to S323 are performed. Processing program. In step S321, an X training instruction indicating the measurement of the time for performing the operation X is applied from the first wafer 110 to the second wafer 120. In step S322, the second wafer 120 internally performs an operation X and measures the time for performing the operation X. In step S323, the time for performing the operation X measured in step S322 is stored in the storage circuit 250 inside the second wafer 120. At this time, the operation of measuring the amount of time taken by the second wafer 120 to perform the operation X at the second power supply voltage VDD2 having the second level (for example, 1.2 V) is terminated.

In step S330, an operation time read command TIME RD is applied from the first wafer 110 to the second wafer 120. In step S340, the time for performing operation X from each of the second power supply voltages VDD2 is transmitted from the second wafer 120 to the first wafer 110 in response to the operation time read command TIME RD. Here, the information shown in Table 1 is transferred from the second wafer 120 to the first wafer 110.

In step S350, based on the information transmitted from the second wafer 120, the first wafer 110 sets parameters regarding the operation X of the second wafer 120. For example, when the second power supply voltage VDD2 is at a level of 1.0 V, the first wafer 110 can set the latency of the operation X of the second wafer 120 to 8 units. When the second power supply voltage VDD2 is at a level of 1.2 V, the first wafer 110 can set the latency of the operation X of the second wafer 120 to 6 units.

Although FIG. 3 illustrates an example of measuring the time for performing operation X of the second wafer 120 under the second power supply voltage VDD2 having two levels, the time for performing the operation X of the second wafer 120 may be Have more than two levels The second power supply voltage VDD2 is measured. Here, the operation illustrated in FIG. 3 can improve the control of the second wafer 120 by the first wafer 110 by determining the execution of the second wafer 120 at each of the second power supply voltages VDD2. According to an example, the operations of FIG. 3 may be performed during an initial phase of interaction between the first wafer 110 and the second wafer 120.

4 is a block diagram showing an integrated circuit system including a first wafer 410 and a second wafer 420 in accordance with a second embodiment of the present invention.

In the embodiment shown in FIG. 4, the time for performing operation X of the second wafer 420 is not measured, and the time for performing operation X has been stored in the second wafer 420, and the stored information Transfer to the first wafer 410.

Referring to FIG. 4, the integrated circuit system includes a first wafer 410, a second wafer 420, and a power supply 430.

The first wafer 410 is a master wafer that gives instructions to the second wafer 420 to perform a particular operation, and the second wafer 420 is a controlled wafer that performs operations corresponding to instructions from the first wafer 410. For example, the first wafer 410 can be a memory controller, and the second wafer 420 can be a memory that performs a read operation or a write operation under the instruction of the memory controller.

The power supplier 430 supplies the power supply voltages VDD1 and VDD2 to the first wafer 410 and the second wafer 420. The level of the first power supply voltage VDD1 supplied from the power supply 430 to the first wafer 410 and the level of the second power supply voltage VDD2 supplied from the power supply 430 to the second wafer 420 may be the same or different from each other. The levels of the first power supply voltage VDD1 and the second power supply voltage VDD2 supplied to the first wafer 410 and the second wafer 420 by the power supplier 430 may be changed by the first wafer 410. According to another In one example, the level of the first power supply voltage VDD1 supplied from the power supply 430 to the first wafer 410 may be a constant voltage, and the first wafer 410 may be changed from the power supply 430 to the second of the second wafer 420. The level of the power supply voltage VDD2. In the drawings, "CONTROL" means determining the level of power supply provided by the power supply 430 under the control of the first wafer 410.

The first wafer 410 transmits an "operation time read command" requesting information about the time taken to perform the operation X to the second wafer 420, and the operation X may be an instruction on the first wafer 410 by the second wafer 420. Any action performed below. The second wafer 420 then transmits its stored information about the time at which operation X was performed. The time for performing operation X from the second wafer 420 to the first wafer 410 may be the same information as shown in Table 1 that matches the second power supply voltage VDD2. The first wafer 410 receives the time for performing the operation X, and determines the execution of the second wafer 420 for each level of the second power supply voltage VDD2 applied to the second wafer 420, and the first wafer 410 is determined based on The control of the second wafer 420 is performed.

The second wafer 420 stores the time for performing the operation X for each of the second power supply voltage VDD2. According to an example, the test can be performed after the second wafer 420 is fabricated, and the operation X of the second wafer 420 is tested, and the manufacturer can perform the operation X with respect to the second wafer 420 for each of the second power supply voltages VDD2. Information on the time spent is stored in the second wafer 420.

FIG. 5 is a block diagram illustrating the second wafer 420 shown in FIG.

Referring to FIG. 5, the second wafer 420 includes a buffer 501 and an instruction decoder. 510. Circuit 530, storage circuit 550, and output circuit 560 for performing operation X.

The buffer 501 receives one or more command signals CMD transmitted from the first wafer 410. In the drawing, "X M" indicates that there are M number of command signals.

The command decoder 510 outputs an "operation time read command TIME RD" by decoding one or more command signals CMD input via the buffer 501, and the "operation time read command TIME RD" requests for the second wafer 420. Information on the time it takes to perform the operation X. The instruction decoder 510 not only outputs the operation time read instruction TIME RD, but also outputs many other instructions that direct the operation to be performed by the second wafer 420. However, to the extent that the further description of the instructions is not necessary to explain the exemplary embodiments, the instructions are not illustrated in the drawings.

Circuitry 530 for performing operation X is a circuit that performs operation X under the instruction of instruction decoder 510. "Operation X" in the figure shows an operation X in response to an instruction being transmitted to the output from the instruction decoder 510 for the operation of the circuit 530 of operation X.

The storage circuit 550 stores information about the time for performing the operation X according to each level of the second power supply voltage VDD2 applied to the second wafer 420, wherein the time is, for example, as discussed above by the manufacturer To measure and store. Here, the storage circuit 550 stores the information shown in Table 1. When the instruction decoder 510 outputs the operation time read command TIME RD, the information stored in the storage circuit 550 is transferred to the first wafer 410 via the output circuit 560. During normal operation (i.e., not a training operation), output circuit 560 can perform operation X due to operation in circuit 530 for performing operation X. The generated output signal OUT is transmitted to the first wafer 410.

Figure 6 is a flow chart illustrating the operation of the integrated circuit system shown in Figures 4 and 5. Referring to Figure 6, the overall operation of the integrated circuit system is described.

In step S610, an operation time read command TIME RD is applied from the first wafer 410 to the second wafer 420. In step S620, the information stored in the storage circuit 550 of the second wafer 420 is returned in response to the operation time reading command TIME RD (where, for example, the information can be measured and detected by the manufacturer as described above). Transfer to the first wafer 410.

In step S630, based on the information transmitted from the second wafer 420, the first wafer 410 sets parameters for the operation X of the second wafer 420. For example, when the second power supply voltage VDD2 is at a level of 1.0 V, the first wafer 410 can set the latency of the operation X of the second wafer 420 to 8 units. When the second power supply voltage VDD2 is at a level of 1.2 V, the first wafer 410 can set the latency of the operation X of the second wafer 420 to 6 units.

Figure 7 is a block diagram showing a memory system in accordance with a first embodiment of the present invention.

The memory system of Figure 7 corresponds to the integrated circuit system of Figure 1. The first wafer 110 corresponds to the memory controller 710 and the second wafer 120 corresponds to the memory 720. In the absence of conflict, the same description of the time to perform operation X as to be described in connection with FIG. 1 applies to the time as described in connection with FIG. 7 for performing a read operation.

Referring to FIG. 7, the memory system includes a memory controller 710, a memory 720, and a power supply 730.

The memory controller 710 controls the memory 720 by applying instructions, addresses, and data to the memory 720. The memory 720 stores the data and transfers the stored data to the memory controller 710 under the control of the memory controller 710.

The power supply 730 supplies power supply voltages VDD1 and VDD2 to the memory controller 710 and the memory 720. The level of the first power supply voltage VDD1 supplied from the power supply 730 to the memory controller 710 and the level of the second power supply voltage VDD2 supplied from the power supply 730 to the memory 720 may be the same or different from each other. The levels of the first power supply voltage VDD1 and the second power supply voltage VDD2 supplied by the power supply 730 can be changed by the memory controller 710. According to another example, the level of the first power supply voltage VDD1 provided from the power supply 730 to the memory controller 710 can be constant, and the memory controller 710 can be changed from the power supply 730 to the memory 720. The level of the second power supply voltage VDD2. In the drawings, "CONTROL" means determining the level of the second power supply VDD2 provided by the power supply 730 under the control of the memory controller 710.

The memory controller 710 applies a training instruction for giving a training operation to instruct an instruction to perform a read operation to the memory 720. Here, the training command is expressed as "read training command" in the drawing. The memory 720 then performs a read operation, measures the time for performing the read operation, and transmits the measurement result to the memory controller 710. This interaction between the memory controller 710 and the memory 720 is repeated while changing the level of the second power supply voltage VDD2 applied to the memory 720. The memory controller 710 determines that the second battery is The force supply voltage VDD2 changes the manner in which the memory 720 is used to perform the read operation.

The memory 720 can transfer the "time for performing the read operation" to the memory controller 710 in the following two ways.

(1) Whenever the memory controller 710 applies the read training command to the memory 720, the memory 720 measures the time for performing the read operation, and transmits the "time for performing the read operation" to Memory controller 710. In other words, although the memory controller 710 does not individually request the time for performing the read operation from the memory 720, the memory 720 will be used when the memory 720 ends measuring the time for performing the read operation. The time at which the read operation is performed is automatically transferred to the memory controller 710.

(2) When the memory controller 710 applies the read training command to the memory 720, the memory 720 measures the time for performing the read operation and internally stores the measured time for performing the read operation. And when the memory controller 710 requests the memory 720 for the time for performing the read operation (that is, when the memory controller 710 applies the operation time read command to the memory 720), the memory 720 transmits The time stored to perform the read operation.

Table 2 below exemplarily shows the time for performing the read operation measured in accordance with the level of the second power supply voltage VDD2. In Table 2, the unit for the time for performing the read operation is the number of clocks. Here, the time for performing the read operation means the address access time tAA, which represents the time from the time when the read command is applied to the time when the memory 720 can output the corresponding material.

When the memory controller 710 receives the information displayed in Table 2, the memory controller 710 can determine the time of the memory 720 for performing the read operation. Therefore, the memory controller 710 can easily control the latency of the read operation of the memory 720. For example, when the second power supply voltage VDD2 of the memory 720 is 1.1 V, the memory controller 710 sets the latency of the read operation of the memory 720 to 11 clocks. When the second power supply voltage VDD2 of the memory 720 is 1.3 V, the memory controller 710 sets the latency of the read operation of the memory 720 to 7 clocks. Here, although the second power supply voltage VDD2 of the memory 720 is changed, the memory controller 710 can consistently optimize the CAS latency of the read operation of the memory 720.

In FIG. 7, the information transmitted between the memory controller 710 and the memory 720 for the memory controller 710 is described to determine the time at which the memory 720 is used to perform the read operation in the memory controller 710. . The "read training command" and the "operating time read command" applied from the memory controller 710 to the memory 720 can be transmitted via the command channel and transmitted from the memory 720 to the memory controller 710 for "execution of reading." The time of the operation can be transmitted via the data channel. The power supply voltage level information "VDD INFO" transmitted from the memory controller 710 to the memory 720 in FIG. 7 is about Information previously applied to the level of the second power supply voltage VDD2 of the memory 720. The power supply voltage level information can be transmitted via the address channel.

FIG. 8 is a block diagram showing the memory 720 shown in FIG.

Referring to FIG. 8, the memory 720 includes buffers 801, 802, and 803, an instruction decoder 810, a status decoder 820, a read control circuit 830, a counter 840, a storage circuit 850, an output circuit 860, a memory cell array 870, and a tube. A pipe latch 880.

Buffers 801, 802, and 803 receive signals transmitted from memory controller 710. The first buffer 801 receives one or more command signals CMD transmitted from the memory controller 710. In the drawing, "X M" indicates that there are M number of command signals. The second buffer 802 receives one or more address signals ADD transmitted from the memory controller 710. In the figure, "X N" indicates that there are N number of address signals. The third buffer 803 receives the clock CLK transmitted from the memory controller 710.

The instruction decoder 810 outputs a "read training instruction" for performing a training operation of a read operation by decoding one or more instruction signals CMD input via the first buffer 801. Further, the command decoder 810 outputs the "operation time read command TIME RD" by decoding one or more command signals CMD input via the first buffer 801. The instruction decoder 810 decodes not only the read training instruction and the operation time read instruction TIME RD but also the different operations (such as normal read operations, active operations, write operations, etc.) to be performed by the memory 720. instruction. However, further description based on the instructions is not necessary to explain the exemplary embodiments, and thus the instructions are not illustrated in the drawings.

The status decoder 820 outputs the power supply voltage level information "VDD INFO" by decoding one or more address signals ADD input via the second buffer 802, and the information "VDD INFO" indicates that it is currently applied to the memory 720. The level of the second power supply voltage VDD2.

The read control circuit 830 is a logic circuit for performing a self-memory cell array 870 by delaying a read command (or training command) when the memory controller 710 gives an instruction to perform a read operation. The read data is input to the tube latch 880. Here, the read control circuit 830 is a circuit for generating a control signal regarding a read operation. When the read control circuit 830 outputs a read training instruction, the read control circuit 830 performs a read operation. Here, when the instruction decoder 810 outputs an instruction to instruct execution of a read operation and when the instruction decoder 810 outputs a read training instruction, the read control circuit 830 performs the same operation.

The counter 840 is a circuit for measuring the time of the read control circuit 830 for performing a read operation. The counter 840 counts the number of times the clock CLK is enabled from the time when the read training command is enabled to the time when the output signal OUT of the system input signal PIN of the read control circuit 830 is enabled, and generates time information TIME<0:3>. According to an example, the time information TIME<0:3> is 4 bits.

Tube latch 880 stores the data read from memory cell array 870 during a read operation. Tube latch 880 is a circuit that arranges data in the form of an output. Since the tube latch 880 operates in synchronization with the clock CLK, the time during which the output data stays in the tube latch 880 is always constant. Therefore, the level of the second power supply voltage VDD2 applied to the memory 720 is The change does not affect the operating time of the tube latch 880.

The storage circuit 850 stores the time information TIME<0:3> measured in the counter 840. The storage circuit 850 also receives the power supply voltage level information VDD INFO, and the storage circuit 850 can match the time information TIME<0:3> with the power supply voltage level information VDD INFO and store the time information TIME<0:3> and the power Supply voltage level information VDD INFO. Here, the information as shown in Table 2 can be matched and stored in the storage circuit 850. The time of the memory 720 for performing the read operation ranges from the time when the read command is received from the memory 720 to the time when the operations of the read control circuit 830 and the tube latch 880 are terminated. The storage circuit 850 can store a value obtained by summing the following: time information TIME<0:3> measured in the counter 840, which indicates the operation time of the read control circuit 830; and the tube lock The operating time of the register 880, which is described above as a constant value.

When the operation time read command TIME RD is transferred to the storage circuit 850, the information stored in the storage circuit 850 is transferred to the output circuit 860, and the output circuit 860 transmits the information to the memory controller 710. During normal operation (i.e., not training operation), output circuit 860 outputs data output from memory cell array 870 and arranged by tube latch 880.

Figure 9 is a flow chart illustrating the operation of the memory system shown in Figures 7 and 8. Referring to Figure 9, the overall operation of the memory system shown in Figures 7 and 8 will be described.

In step S910, a second power supply voltage VDD2 having a first level (for example, 1.0 V) is applied to the memory 720. As described above, the level of the second power supply voltage VDD2 applied to the memory 720 is based on memory. The body controller 710 controls the power supply 730 to determine.

While the memory 720 is operating with the second power supply voltage VDD2 having the first level (for example, 1.0 V), the processing procedures of steps S911 to S913 are performed. In step S911, a read training instruction indicating the measurement of the time for performing the read operation is applied from the memory controller 710 to the memory 720. The read training command can be applied as a single command, or the read training command can be applied after the memory controller 710 controls the memory 720 to enter the training mode. For example, the read training command can be a read command applied to the memory 720 after the memory 720 enters the training mode.

In step S912, the memory 720 internally performs a read operation, and measures the time for performing the read operation in response to the read training instruction applied in step S911. As described earlier with reference to FIG. 8, the time for performing the read operation is measured from the time when the read training command is applied to the time at which the output signal OUT of the system input signal of the control circuit 830 is outputted (eg, enabled). . In step S913, the time for performing the read operation measured in step S912 is stored in the storage circuit 850 inside the memory 720. At this time, the operation of the measurement memory 720 for performing the read operation at the second power supply voltage VDD2 having the first level (for example, 1.0 V) is terminated.

In step S920, the level of the second power supply voltage VDD2 applied to the memory 720 is changed from the first level (for example, 1.0 V) to the second level (for example, 1.2 V). As the memory controller 710 controls the power supply 730, a change in the level of the second power supply voltage VDD2 applied to the memory 720 can be performed.

When the memory 720 operates with the second power supply voltage VDD2 having the second level (for example, 1.2 V), the processing procedures of steps S921 to S923 are performed. In step S921, a read training instruction indicating the measurement of the time for performing the read operation is applied from the memory controller 710 to the memory 720. In step S922, the memory 720 internally performs a read operation and measures the time for performing the read operation. In step S923, the time for performing the read operation measured in step S922 is stored in the storage circuit 850 inside the memory 720. At this time, the operation of the measurement memory 720 for performing the read operation at the second power supply voltage VDD2 having the second level (for example, 1.2 V) is terminated.

In step S930, the operation time read command TIME RD is applied from the memory controller 710 to the memory 720. In step S940, the time for performing the read operation from each of the second power supply voltage VDD2 is transmitted from the memory 720 to the memory controller 710 in response to the operation time read command TIME RD. Here, the information shown in Table 2 is transferred from the memory 720 to the memory controller 710.

In step S950, based on the information transmitted from the memory 720, the memory controller 710 sets parameters regarding the read operation of the memory 720. For example, when the second power supply voltage VDD2 is at a level of 1.0 V, the memory controller 710 can set the latency of the CAS latency of the read operation of the memory 720 to 13 clocks. When the second power supply voltage VDD2 is at a level of 1.2 V, the memory controller 710 can set the latency of the read operation of the memory 720 to 9 clocks.

Although FIG. 9 illustrates the second power supply voltage VDD2 having two levels An example of the time at which the memory 720 is used to perform the read operation is measured, but the time of the memory 720 for performing the read operation may be measured at the second power supply voltage VDD2 having more than two levels. . Moreover, the operation illustrated in FIG. 9 can improve the control of the memory controller 710 by the memory controller 710 by determining the execution of the read operation of the memory 720 at each of the second power supply voltages VDD2. According to an example, the operations of FIG. 9 may be performed during an initial phase of interaction between memory controller 710 and memory 720.

Figure 10 is a block diagram showing a memory system in accordance with a second embodiment of the present invention.

In the embodiment shown in FIG. 10, the time for performing the read operation of the memory 1020 is not measured by the memory 1020, and the time for performing the read operation has been stored in the memory 1020. Medium (for example, can be measured and stored by the manufacturer), and the stored information is transmitted to the memory controller 1010.

Referring to FIG. 10, the memory 720 includes a memory controller 1010, a memory 1020, and a power supply 1030.

The memory controller 1010 controls the memory 1020 by applying instructions, addresses, and data. The memory 1020 stores the data and transfers the stored data to the memory controller 1010 under the control of the memory controller 1010.

The power supply 1030 supplies power supply voltages VDD1 and VDD2 to the memory controller 1010 and the memory 1020. The level of the first power supply voltage VDD1 supplied from the power supply 1030 to the memory controller 1010 and the level of the second power supply voltage VDD2 supplied from the power supply 1030 to the memory 1020 may be the same or different from each other. Provided by the power supply 1030 The levels of the first power supply voltage VDD1 and the second power supply voltage VDD2 to the memory controller 1010 and the memory 1020 can be changed by the memory controller 1010. According to another example, the level of the first power supply voltage VDD1 provided from the power supply 1030 to the memory controller 1010 can be constant, and the memory controller 1010 can be changed from the power supply 1030 to the memory 1020. The level of the second power supply voltage VDD2. In the drawings, "CONTROL" means determining the level of the second power supply VDD2 provided by the power supply 1030 under the control of the memory controller 1010.

The memory controller 1010 transmits an "operation time read command" requesting information about the time for performing the read operation from the memory 1020. The memory 1020 then transmits the stored information about the time at which the read operation was performed. The time from the memory 1020 to the memory controller 1010 for performing the read operation may be the same information as shown in Table 2 that matches the second power supply voltage VDD2. The memory controller 1010 receives the time for performing the read operation, and determines the execution of the memory 1020 for each of the second power supply voltages VDD2 applied to the memory 1020, and the memory controller 1010 can be executed based on As a result, the memory 1020 is effectively controlled.

The memory 1020 stores the time for performing the read operation for each of the second power supply voltage VDD2. This operation can be performed by the manufacturer of the memory 1020. Different tests can be performed during the manufacture of the memory, and after the memory 1020 is fabricated and the read operation of the memory 1020 is tested, the manufacturer can perform a read on the memory 1020 for each of the second power supply voltages VDD2. Information about the time taken to take the operation is stored in memory In body 1020.

FIG. 11 is a block diagram showing the memory 1020 shown in FIG.

In the drawings, among the constituent elements of the memory 1020, the constituent elements for "the time for performing the read operation" stored in the inside of the memory 1020 are described.

Referring to FIG. 11, the memory 1020 includes a buffer 1101, an instruction decoder 1110, a storage circuit 1150, and an output circuit 1160.

The buffer 1101 receives one or more command signals CMD transmitted from the memory controller 1010. In the drawing, "X M" indicates that there are M number of command signals.

The instruction decoder 1110 outputs an operation time read instruction TIME RD by decoding one or more instruction signals CMD input via the buffer 1101. The operation time read command TIME RD outputted by the instruction decoder 1110 is transferred to the storage circuit 1150, and is stored in the storage circuit 1150 for performing the read operation in response to the received operation time read command TIME RD. The information of the time is transmitted to the memory controller 1010 via the output circuit 1160.

Since the information stored in the storage circuit 1150 as shown in Table 2 is stored during the manufacture of the memory 1020, the fuse circuit can be used as the storage circuit 1150.

Figure 12 is a flow chart illustrating the operation of the memory system shown in Figures 10 and 11. Referring to Figure 12, the overall operation of the memory system is described.

In step S1210, the operation time read command TIME RD is applied from the memory controller 1010 to the memory 1020. In step S1220, the response The information stored in the storage circuit 1150 of the memory 1020 is transferred to the memory controller 1010 at the operation time reading command TIME RD.

In step S1230, based on the information transmitted from the memory 1020, the memory controller 1010 sets parameters regarding the read operation of the memory 1020. For example, when the second power supply voltage VDD2 is at a level of 1.0 V, the memory controller 1010 can set the CAS latency of the memory 1020 to 13 clocks. When the second power supply voltage VDD2 is at a level of 1.2 V, the memory controller 1010 can set the CAS latency of the memory 1020 to 9 clocks.

Since the read operation is described in the processing procedures of steps S1210 to S1230 while the memory controller 1010 has the information about the read operation of the memory 1020, the operation of FIG. 12 can be performed in the memory controller according to an example. 1010 is executed with the initial operational phase of memory 1020.

According to an embodiment of the present invention, after the instruction from the master wafer, the operating speed of the specific operation of the controlled wafer is measured for each bit of the power supply voltage, and the measurement result is transmitted to the master wafer. Or, the operating speed of each level of the power supply voltage for a particular operation stored in the controlled wafer is transferred to the master wafer.

Thus, the master wafer can determine the execution of the particular operation of the controlled wafer for each bit of the power supply voltage, and as a result, the master wafer can effectively control the latency of the controlled wafer, such as the controlled wafer.

Although the present invention has been described in terms of a particular embodiment, it will be apparent to those skilled in the art that various modifications can be made without departing from the spirit and scope of the invention as defined in the following claims. Change and modify.

110‧‧‧First chip

120‧‧‧second chip

130‧‧‧Power supply

201‧‧‧First buffer

202‧‧‧Second buffer

203‧‧‧ third buffer

210‧‧‧ instruction decoder

220‧‧‧ condition decoder

230‧‧‧Circuit for performing operation X

240‧‧‧ counter

250‧‧‧Storage circuit

260‧‧‧Output circuit

410‧‧‧First chip

420‧‧‧second chip

430‧‧‧Power supply

501‧‧‧buffer

510‧‧‧ instruction decoder

530‧‧‧Circuit for performing operation X

550‧‧‧Storage circuit

560‧‧‧Output circuit

710‧‧‧ memory controller

720‧‧‧ memory

730‧‧‧Power supply

801‧‧‧ first buffer

802‧‧‧ second buffer

803‧‧‧ third buffer

810‧‧‧ instruction decoder

820‧‧‧ condition decoder

830‧‧‧Read control circuit

840‧‧‧ counter

850‧‧‧ storage circuit

860‧‧‧Output circuit

870‧‧‧ memory cell array

880‧‧‧ tube latch

1010‧‧‧ memory controller

1020‧‧‧ memory

1030‧‧‧Power supply

1101‧‧‧buffer

1110‧‧‧Command decoder

1150‧‧‧Storage circuit

1160‧‧‧Output circuit

ADD‧‧‧ address signal

CLK‧‧‧ clock

CMD‧‧‧ command signal

OUT‧‧‧ output signal

PIN‧‧‧ tube input signal

TIME RD‧‧‧Operation time read command

TIME<0:3>‧‧‧Time Information

VDD INFO‧‧‧Power supply voltage level information

VDD1‧‧‧Power supply voltage / first power supply voltage

VDD2‧‧‧Power supply voltage / second power supply voltage / second power Force supply

1 is a block diagram showing an integrated circuit system including a first wafer and a second wafer in accordance with a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating the second wafer 120 shown in FIG. 1.

3 is a flow chart illustrating the operation of the integrated circuit system shown in FIGS. 1 and 2.

4 is a block diagram showing an integrated circuit system including a first wafer and a second wafer in accordance with a second embodiment of the present invention.

FIG. 5 is a block diagram illustrating the second wafer 420 shown in FIG.

Figure 6 is a flow chart illustrating the operation of the integrated circuit system shown in Figures 4 and 5.

Figure 7 is a block diagram showing a memory system in accordance with a first embodiment of the present invention.

FIG. 8 is a block diagram showing the memory 720 shown in FIG.

Figure 9 is a flow chart illustrating the operation of the memory system shown in Figures 7 and 8.

Figure 10 is a block diagram showing a memory system in accordance with a second embodiment of the present invention.

FIG. 11 is a block diagram showing the memory 1020 shown in FIG.

Figure 12 is a flow chart illustrating the operation of the memory system shown in Figures 10 and 11.

110‧‧‧First chip

120‧‧‧second chip

130‧‧‧Power supply

VDD1‧‧‧Power supply voltage / first power supply voltage

VDD2‧‧‧Power supply voltage / second power supply voltage / second power supply

Claims (16)

An integrated circuit system comprising: a first wafer configured to supply a training command; and a second wafer configured to respond to the training instruction to be used to perform an operation The measurement time is transmitted to the first wafer, wherein the first wafer is further configured to set a latency of the operation of the second wafer in response to the measured time. The integrated circuit system of claim 1, wherein the first wafer is further configured to control the second wafer such that the output of the training instruction from the first wafer and the transmission of the measured time are directed to supply The different voltage levels of the power supply voltage of one of the second wafers are repeatedly performed, respectively. The integrated circuit system of claim 1, wherein the transmission of the training command from the first wafer and the measurement of the measured time is performed in an operational time measurement mode. The integrated circuit system of claim 2, further comprising: a power supply configured to supply the power supply voltage to the second wafer, wherein the first wafer is further configured to control the power supply The supply of voltage from the power supply to the second wafer. An integrated circuit system comprising: a first wafer configured to supply a training command; and a second wafer configured to store a desired operating time corresponding to one of the training instructions Where the training instruction is from the supply of the first wafer and the required operation The time by the storage of the second wafer is repeatedly performed for different voltage levels supplied to one of the second wafers, wherein each of the power supply voltages stored in the second wafer is The required operating time of the level is transferred to the first wafer, and wherein the first wafer sets a latent time of the corresponding operation of the second wafer based on the required operating time transmitted from the second wafer . An integrated circuit system comprising: a first wafer configured to supply a training command; a second wafer configured to store a desired operating time corresponding to one of the training instructions; And a power supply configured to supply a power supply voltage to the second wafer, wherein the supply of the training command from the first wafer and the required operational time are by the storage of the second wafer The respective voltage levels of the power supply voltage supplied to the second wafer are repeatedly performed separately. A method for operating an integrated circuit chip, comprising: supplying a first power supply voltage to the integrated circuit chip; outputting a training command while the integrated circuit chip operates at the first power supply voltage Up to the integrated circuit chip; measuring a first operation time of the integrated circuit chip for performing an operation corresponding to one of the training instructions; storing the first operation time; supplying a second power supply voltage to the An integrated circuit chip; while the integrated circuit wafer is operated with the second power supply voltage Supplying the training instruction to the integrated circuit chip; measuring a second operation time of the integrated circuit chip for performing an operation corresponding to one of the training instructions; storing the second operation time; and the first The operation time and the second operation time are transmitted to a control wafer that controls the integrated circuit wafer, wherein the control wafer sets the current based on the first operation time while the integrated circuit wafer is supplied with the first power supply voltage a latent time of the operation of the integrated circuit chip, and the control wafer sets one of the operations of the integrated circuit wafer based on the second operation time while the integrated circuit wafer is supplied with the second power supply voltage Latent time. An integrated circuit system comprising: a first wafer configured to perform a predetermined operation; and a second wafer configured to command the predetermined operation of the first wafer, wherein the first wafer Included as a storage circuit configured to store a desired operational time of the predetermined operation at a power supply voltage having a different voltage level, and the first wafer transmits information stored in the storage circuit And to the second wafer, wherein the second wafer sets a latent time of the predetermined operation of the first wafer based on the required time transmitted from the first wafer. A memory system includes: a memory configured to transmit a command from a training command to the a time at which the memory outputs a time at which the data is output in response to the training command; a memory controller configured to output the training command to the memory and from the memory Receiving the measured data output time; and a power supply configured to supply the power supply voltage to the memory, wherein the memory controller is further configured to control the memory such that the The transmission of the training command from the memory controller and the output time of the measured data is repeatedly performed for different voltage levels supplied to one of the power supply voltages of the memory, and the memory control The device is further configured to control one of the voltage levels of the power supply voltage. The memory system of claim 9, wherein the output of the training command from the memory controller and the transmission of the measured data from the memory are performed in a training mode. The memory system of claim 9, wherein the memory controller is configured to set the memory for the power supply voltage in response to the measured data output time for different voltage levels of the power supply voltage, respectively The row address strobe (CAS) latency of the different voltage levels. A memory system comprising: a memory configured to store a measured data output time from a time when a training instruction is applied to the memory to a time at which data can be output; and a memory controller configured to output the training command to the a memory, wherein the application of the training command from the memory controller and the measured data output time are respectively determined by the storage system of the memory for different voltage levels of a power supply voltage supplied to one of the memory Repeatedly executing, wherein the measured data output time stored in the memory corresponding to each level of the power supply voltage is transmitted to the memory controller, and the memory controller is based on the memory And transmitting, by the body, the measured data output time under each of the power supply voltages to set a row address sing (CAS) latency of the memory at each level of the power supply voltage . A memory comprising: a memory cell array configured to store data; an instruction decoder configured to output a training command by decoding one or more signals; a control circuit Configuring to generate a data output signal by delaying the training command; a data output circuit configured to output the data read from the memory cell array region in response to the data output signal; a measurement circuit configured to measure a data output time from a time when the training command is output to a time when the data output circuit outputs the data; and a storage circuit configured to store When the measured data is output between. The memory of claim 13, wherein the measurement circuit is further configured to measure a time from when one of the training instructions is enabled to when the data output signal is enabled. The memory of claim 13, wherein the storage circuit is configured to store the measured data output time for different voltage levels supplied to one of the memory power supply voltages. The memory of claim 13, further comprising: a status decoder configured to determine by decoding at least one of the group of free one or more address signals and one or more command signals in the future Power supply voltage information, the power supply voltage information indicating a voltage level applied to the power supply voltage of the memory, wherein the storage circuit is configured to match the power supply voltage information to the measured data output time, And storing the power supply voltage information and the measured data output time.