CN115017069B - Level adaptation device, storage system and power supply method - Google Patents

Level adaptation device, storage system and power supply method Download PDF

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Publication number
CN115017069B
CN115017069B CN202210752325.XA CN202210752325A CN115017069B CN 115017069 B CN115017069 B CN 115017069B CN 202210752325 A CN202210752325 A CN 202210752325A CN 115017069 B CN115017069 B CN 115017069B
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interface
level
component
electronic device
adaptation
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CN115017069A (en
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郑海军
武恒文
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202311322735.1A priority Critical patent/CN117453591A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Sources (AREA)
  • Logic Circuits (AREA)

Abstract

The application discloses a level adaptation device, a storage system and a power supply method. Wherein the level adaptation means comprises: comprising the following steps: the device comprises a first interface, a second interface, a third interface and an adaptation circuit, wherein; the adaptation circuit is connected with the first interface, the second interface and the third interface and is used for: providing a first level adapted to a first electronic device to a second electronic device through the third interface when the first interface is accessed to the first level supported by the first electronic device; providing a second level adapted to the first electronic device to the second electronic device through the third interface when the first interface is not connected to the first level; the second level is a level supported by the first electronic device that is accessed from the second interface.

Description

Level adaptation device, storage system and power supply method
Technical Field
The present application relates to the field of memory related circuits, and in particular, to a level adaptation device, a memory system, and a power supply method.
Background
With the advent of the big data age, the requirement for data storage is higher and higher, and the hard disk is one of media for storing data, so that the attention in the industry is widely paid, and especially, the attention to the solid state disk (SSD, solid State Drives) is more widely paid. However, since the types of communication levels supported by the platform for communicating with the SSD are relatively large, the use of the platform for the SSD is limited, so how to adapt the SSD to the platform to complete the communication is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present application provides a level adapting device, a storage system and a power supply method, so as to automatically adapt the communication level of the SSD to the level supported by the platform, thereby completing the communication between the platform and the SSD.
In order to achieve the above purpose, the technical scheme of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a level adaptation apparatus, including: the device comprises a first interface, a second interface, a third interface and an adaptation circuit, wherein;
the adaptation circuit is connected with the first interface, the second interface and the third interface and is used for: providing a first level adapted to a first electronic device to a second electronic device through the third interface when the first interface is accessed to the first level supported by the first electronic device; providing a second level adapted to the first electronic device to the second electronic device through the third interface when the first interface is not connected to the first level; the second level is a level supported by the first electronic device that is accessed from the second interface.
In a second aspect, an embodiment of the present application provides a memory system, including a level adaptation device according to any one of the preceding claims.
In a third aspect, an embodiment of the present application further provides a power supply method of a storage system, which is applied to a level adaptation device, where the level adaptation device includes a first interface, a second interface, a third interface, and an adaptation circuit, and the adaptation circuit is connected to the first interface, the second interface, and the third interface; the power supply method comprises the following steps:
when the first interface is connected to a first level supported by a first electronic device, the adaptation circuit provides the first level adapted to the first electronic device for a storage system contained in a second electronic device through the third interface;
the adaptation circuit provides a second level adapted to the first electronic device to the storage system via the third interface when the first interface is not connected to the first level; the second level is a level supported by the first electronic device that is accessed from the second interface.
The embodiment of the application provides a level adaptation device, a storage system and a power supply method. Wherein the level adaptation means comprises: the device comprises a first interface, a second interface, a third interface and an adaptation circuit, wherein; the adaptation circuit is connected with the first interface, the second interface and the third interface and is used for: providing a first level adapted to a first electronic device to a second electronic device through the third interface when the first interface is accessed to the first level supported by the first electronic device; providing a second level adapted to the first electronic device to the second electronic device through the third interface when the first interface is not connected to the first level; the second level is a level supported by the first electronic device that is accessed from the second interface. According to the level adapting device and the power supply method of the storage system, provided by the embodiment of the application, according to the level adapting device arranged between the first electronic equipment (platform system) and the second electronic equipment (storage system), the second electronic equipment can automatically obtain the level (the first level or the second level) adapting to the first electronic equipment according to whether the first interface of the level adapting device has the first level access supported by the first electronic equipment or not, so that a user using the second electronic equipment does not need to screen the level supported by the first electronic equipment, and further the communication of the first signal between the first electronic equipment and the second electronic equipment is completed. In this way, the second electronic device is enabled to be adapted to support the first electronic device of a different level type.
Drawings
Fig. 1 is a schematic structural diagram of a level adaptation device according to an embodiment of the present application;
fig. 2 is a schematic diagram of a problem existing between a first electronic device and a second electronic device according to an embodiment of the present application;
fig. 3 is a schematic diagram II of a problem existing between a first electronic device and a second electronic device according to an embodiment of the present application;
fig. 4 is a schematic diagram III of a problem existing between a first electronic device and a second electronic device according to an embodiment of the present application;
fig. 5 is a schematic diagram of an operation principle of a level adaptation device according to an embodiment of the present application;
fig. 6 is a schematic diagram of an adaptive circuit according to an embodiment of the present application;
fig. 7 is a schematic diagram of a second structure of the adaptive circuit according to the embodiment of the present application;
fig. 8 is a schematic diagram III of an adaptive circuit according to an embodiment of the present application;
fig. 9 is a schematic flow chart of a level adaptation method according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of a solid state disk according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments of the present application. All other embodiments, which can be made by a person skilled in the art without any inventive effort, are intended to be within the scope of the present application, based on the embodiments of the present application. Embodiments of the application and features of the embodiments may be combined with one another arbitrarily without conflict. The flow diagrams in the figures show a logical order, but in some cases the steps shown or described may be performed in a different order than that shown or described.
Referring to fig. 1, as shown therein, an embodiment of the present application provides a level adaptation apparatus 100, which includes: a first interface 101, a second interface 102, a third interface 103 and an adaptation circuit 104, wherein;
the adaptation circuit is connected with the first interface, the second interface and the third interface and is used for: providing a first level adapted to a first electronic device to a second electronic device through the third interface when the first interface is accessed to the first level supported by the first electronic device; providing a second level adapted to the first electronic device to the second electronic device through the third interface when the first interface is not connected to the first level; the second level is a level supported by the first electronic device that is accessed from the second interface.
It should be noted that, the first electronic device and the second electronic device may be any devices such as a terminal or a platform capable of communicating using a certain interface protocol, for example, the first electronic device may be a platform having a high-speed serial computer expansion bus standard (PCIe, peripheral Component Interconnect express) m.2 interface; the second electronic device may be an SSD with a PCIe m.2 interface. For another example, the first electronic device may also be a platform with a PCIe M.3 interface; the second electronic device may be an SSD of a PCIe M.3 interface, or the like. It should be clear that the level adaptation means in the embodiments of the application may also be applied to devices with other types of interfaces. Furthermore, the principle of operation of the level adaptation means is the same, irrespective of the type of device the first electronic device and the second electronic device are. Only the first electronic equipment is taken as a platform with a PCIe M.2 interface; the second electronic device is an example of an SSD with a PCIe m.2 interface to illustrate the working principle and structure of the level adaptation device. Under the condition that the description is not specific, the first electronic device is a platform with a PCIe M.2 interface; the second electronic device is an SSD with a PCIe M.2 interface.
When using SSDs for PCIe M.2 interfaces, they have all or part of the relevant signals PEWAKE#, CLKREQ#, PERST#, PLA_S3#, PLN#, PWRDIS, etc., for auxiliary communication with the platform side, commonly referred to as Sideband signals. The communication of the Sideband Signal is normally completed, and the communication levels of Sideband input/output (IO) interfaces of the SSD end and the platform end are correctly matched, as shown in FIG. 2, that is, the two interfaces have the same level. Based on the matching requirement of the Sideband Signal communication level, the SSD with different communication levels and the platform cannot normally communicate, so that the SSD supporting the A communication level cannot work on the platform supporting the B communication level; and SSDs supporting the B communication level cannot operate on platforms supporting the a communication level. Specific examples can be seen in fig. 3 and 4.
Based on this, the level adapting device provided by the embodiment of the application can enable the SSD to automatically adapt the communication level of the platform end for the communication of the Sideband Signal, so that the SSD and the platform can complete the communication of the Sideband Signal.
Specifically, the working principle of the level adaptation device provided by the embodiment of the application is as follows: providing a first level to the second electronic device through the third interface when a first interface accesses the first level supported by the first electronic device; providing a second level to the second electronic device through the third interface when the first interface does not access the first level supported by the first electronic device; the second level is a level supported by the first electronic device accessed from a second interface. That is, when the first electronic device supports the first level, the adapting circuit automatically configures the first level for the second electronic device; when the first electronic device does not support the first level, the first electronic device supports either the first level or the second level, and then the adaptation circuit automatically configures the second level for the second electronic device at this time so as to match the levels of the first electronic device and the second electronic device.
Wherein in some embodiments, the first interface is connected to the first electronic device and is configured to access the first level or not access the first level. When the first electronic device supports the first level, the first electronic device can output the first level, and the first interface is connected with the first level; when the first electronic device does not support the first level, the first electronic device does not output the first level, and the first interface does not access the first level.
It should be noted that, since the first electronic device, that is, the platform end, supports two levels at present, when one of the levels is not supported, the other level is necessarily supported, that is, the embodiment of the present application provides a level adaptation device having only two levels. When the first electronic device supports more levels, an implementation circuit thereof can be constructed based on the inventive concept of the embodiment of the present application. The key point of the embodiment of the present application is that the first electronic device supports a circuit configuration of two levels, that is, in the following description, the first electronic device supports the first level or the second level, unless specifically described otherwise. For example, the first level may be 1.8 volts (V); the second level may be 3.3V. The first level may be 3.3V and the second level may be 1.8V.
For example, as shown in fig. 5, after the platform is started, when the first electronic device outputs 1.8V, it is indicated that the first electronic device supports 1.8V, at this time, the first interface is connected to the 1.8V, after the first interface is connected to the 1.8V, under the action of the adapting circuit, the first interface outputs 1.8V, and the first interface provides the first interface with the second electronic device as a communication level; when the first electronic device does not output 1.8V, the first electronic device is not supported by 1.8V, then the first electronic device supports 3.3V, the first interface is not connected with a level, at the moment, 3.3V is output at the third interface under the action of the adapting circuit, and the 3.3V is provided for the second electronic device, and 3.3V is used as a communication level of the second electronic device. It should be understood that fig. 5 is only an example, and the implementation principle may be implemented according to whether the first electronic device outputs 3.3V, or other levels, which needs to be adjusted according to the actual situation, which is not described herein.
In some embodiments, the level adaptation means is located at the first electronic device; or at a second electronic device; or independent of the first electronic device and the second electronic device.
It is understood that the level adaptation means may be provided in the first electronic device or in the second electronic device or may be independent of the first electronic device and the second electronic device. That is, the level adaptation device may be disposed inside the platform or the SSD, or may be disposed separately, so as to help the SSD achieve level adaptation.
In practical implementations, the adaptation circuit in the level adaptation means may have a variety of implementations.
In some embodiments, the adaptation circuit comprises: a first component, a second component and a third component, wherein;
a first end of the first component is connected with the first interface, and a second end of the first component is grounded or at a low level; the third end of the first component is connected with the enabling end of the third component; the first component is configured to enable the third component when the first interface is not connected to the first level;
the enabling end and the input end of the second component are connected with the first interface; the output end of the second component is connected with the third interface; the second component is used for enabling the enabling end and the input end to be connected with the first level when the first interface is connected with the first level; the output end provides the first level to the second electronic equipment through the third interface;
the enabling end of the third component is connected with the third end of the first component and is connected with the second interface through a first resistor; the input end of the third component is connected with the second interface; the output end of the third component is connected with the third interface; the third component is used for enabling when the first interface is not connected with the first level, and the input end is connected with a second level through a second interface; the output terminal provides the second level to the second electronic device via the third interface.
It should be noted that "first", "second", and "third" in the first component, the second component, and the third component are described herein for convenience only, and are not intended to limit the present application. The first component, the second component and the third component are all of switching characteristics, and therefore, the first component, the second component and the third component may be any components having switching characteristics capable of realizing the above-described circuit functions.
As an alternative embodiment, as shown in fig. 6, the first component is an N-type metal oxide semiconductor field effect transistor (MOSFET, metal Oxide Semiconductor Field Effect Transistor); the second component and the third component are both load switches.
Note that in fig. 6, 1041 is a second component, that is, load Switch1;1042 is a third component, namely Load Switch2;1043 are first components, namely NMOS transistors.
The working principle of the adaptive circuit with the structure can be as follows: when the first electronic device outputs a first level, the first interface is connected to the first level, the NMOS transistor is turned on, the enabling terminal of the Load Switch2 is grounded, so that the Load Switch2 is turned off, and a second level cannot be output to the second electronic device through a third interface; the method comprises the steps that the first level is input to an enabling end of the Load Switch1, so that the Load Switch1 is started, the first level is output, and a second electronic device (or SSD) is provided through a third interface; when the first electronic device does not output the first level, the first interface is not connected with the first level, the NMOS transistor is closed, and the enabling end of the Load Switch2 is provided with voltage input, so that the Load Switch2 is opened, the second level can be output to the second electronic device through the three interfaces, and as the first level is not output, the Load Switch1 is closed and the second level is not output, and at the moment, the whole adapting circuit outputs the second level to the second electronic device through the Load Switch 2.
For example, the first electronic device is a Platform (Platform); when the second electronic device is an SSD and the first level is 1.8V, the adaptation circuit according to fig. 6 may actually operate as follows: if the Platform supports 1.8V Sideband level, a VIO1.8V pin on an M.2 interface of Platform outputs 1.8V level after the Platform is started, the 1.8V level is output to Loadswitch1 and NMOS through a first interface, wherein NMOS is conducted, loadswitch2 is closed, at the moment, 3.3V level cannot be output to a Controller of SSD, meanwhile, under the operation of 1.8V, loadswitch1 works, 1.8V is output to the Controller of SSD through a third interface, and finally Sideband IO of SSD works at the level of 1.8V. If the Platform does not support the 1.8V Sideband level, a VIO1.8V pin on an M.2 interface of the Platform is suspended after the Platform is started; loadswitch1 does not have 1.8V level input, so does not output 1.8V level to the Controller of SSD; at this time, the NMOS has no 1.8V level input, the NMOS is turned off, the Loadswitch2 is turned on, the 3.3V level is output to the Controller of the SSD, and finally the Sideband IO of the SSD works at the 3.3V level.
It should be noted that, the first component may also be a P-type MOSFET, and the second component and the third component are both load switches, in which case, to achieve the above-mentioned functions, the drain terminal of the P-type MOSFET may be grounded; the source terminal of the P-type MOSFET is connected with the enabling terminal of the third component switch. The connection mode of the two components and the second component is unchanged.
In some embodiments, the adaptation circuit 104 may also include: a fourth component, a fifth component and a sixth component, wherein;
the fourth assembly includes: the device comprises a selection end, a first input end, a second input end and an output end; the selection end is connected with the first interface; when the first interface is connected to the first level, a first input end is connected with an output end; when the first interface is not connected with the first level, connecting a second input end with the output end; the first input end is connected with the feedback end of the fifth component through a first resistance element contained in the sixth component; the second input end is connected with the feedback end of the fifth component through a second resistance element contained in the sixth component; the output end is grounded;
the fifth component comprises an enabling end, an input end, an output end and a feedback end; the enabling end and the input end are connected with the second interface and used for accessing a second level; the feedback end is connected with the output end through a third resistance element contained in the sixth component; the output end is connected with the third interface and is used for providing the first level for second electronic equipment through the third interface based on the first resistance element and the third resistance element or providing the first level for second electronic equipment through the third interface based on the second resistance element and the third resistance element when the first interface is connected with the first level; and when the first interface is not connected with the first level, providing the second level for second electronic equipment through the third interface based on the second resistance element and the third resistance element, or providing the second level for second electronic equipment through the third interface based on the first resistance element and the third resistance element.
As an embodiment, as shown in fig. 7, the fourth component is an analog switch; the fifth component is a low voltage regulator. Wherein the sixth component comprises a first resistor, a second resistor and a third resistor.
Note that in fig. 7, 1044 is a fourth component, that is, analog Swich;1045 is a fifth component, i.e., LDO;1046 is a sixth component comprising resistors R1, R2, R3, R4.
Under the structure of the adaptive circuit, the working principle is as follows: the LDO voltage output control satisfies vout=vfb (1+r3/R1) or vout=vfb (1+r3/R2), where Vfb is a fixed value of the LDO design, and vout=1.8v or vout=3.3v can be achieved by selecting a suitable resistor combination R1, R2, R3; on the basis, if the Platform supports 1.8V Sideband level, the VIO1.8V pin IN the M.2 interface of Platform outputs 1.8V level after starting up, the 1.8V level is output to the selection pin given to Analog Switch through the first interface, the IN2 pin is conducted with the OUT pin, and the output Vout=Vfb (1+R3/R2) =1.8V of LDO is realized through the cooperation of R2 and R3; finally, the 1.8V is provided to the SSD through a third interface to operate the Sideband IO of the SSD at the 1.8V level. If the Platform does not support the 1.8V Sideband level, a VIO1.8V pin on an M.2 interface of the Platform is suspended after the Platform is started; at this time, the select pin IN Analog Switch has no level input, and IN1 pin and OUT pin are turned on according to design, and output vout=vfb (1+r3/R1) =3.3v of LDO is made by cooperation of R1 and R3; finally, the 3.3V is provided to the SSD through a third interface, so that the Sideband IO of the SSD works at the 3.3V level; it should be noted that the control logic of Analog Switch may be reversed, with the R1 and R2 resistances being swapped accordingly.
Wherein in some embodiments, the sixth component further comprises a fourth resistive element coupled between the second interface and an enable terminal of the fifth component for reducing a voltage coupled to the enable terminal.
It should be noted that, the use of the fourth resistor is for the safety of the first low voltage stabilizing component, and the second level is not directly input to the enabling end of the first low voltage stabilizing component, but the voltage is divided by a certain resistor, that is, the fourth resistor is connected in series between the second interface and the enabling end of the first low voltage stabilizing component. The size of the fourth resistor is designed according to actual requirements.
In other embodiments, the adaptation circuit may also include:
a seventh component and an eighth component, wherein;
the input end of the seventh component is connected with the input end of the eighth component; the output end of the seventh component is rich and the output end of the eighth component is connected;
the input end of the seventh component is connected with the input end of the eighth component and the second interface, and is used for accessing the second level;
the enabling end of the seventh component and the enabling end of the eighth component are connected with the first interface and are used for enabling the seventh component when the first interface is accessed to the first level; enabling the eighth component when the first interface does not access the first level;
the output end of the seventh component is connected with the third interface and is used for providing the first level for the second electronic equipment through the third interface when the seventh component is enabled;
and the output end of the eighth component is connected with the third interface and is used for providing the second level for the second electronic equipment through the third interface when the second level is enabled.
As an alternative embodiment, as shown in fig. 8, the seventh component is a low voltage regulator; the eighth component is a load switch having an inverted enable signal with the seventh component.
Note that, in fig. 8, 1047 is a seventh component, that is, LDO1.8V;1048 is the eighth component, namely Load Switch. The enabling signals of the seventh component and the eighth component are inverse signals, as shown in fig. 8, and the input end of LDO1.8V is connected with the input end of Load Switch; an output end of LDO1.8V is connected with an output end of the Load Switch; the input end enabling end of LDO1.8V and the enabling end of Load Switch are adjacent to the first electronic device through the first interface, but the enabling logic of the input end enabling end and the enabling end is opposite, namely, when LDO1.8V is enabled, the Load Switch is closed; when Load Switch is enabled, LDO1.8V is off.
Under the adaptation structure, the working principle is as follows: integrating LDO and Loadswitch by the integrated IC to form a gating circuit, wherein the LDO enable control is high-efficiency; the Loadswitch enable control is active low; if the Platform supports 1.8V Sideband level, a VIO1.8V pin on an M.2 interface of Platform outputs 1.8V after the Platform is started; the first interface is connected with 1.8V, at the moment, the LDO is enabled to be effective, the Loadswitch is enabled to be invalid and is closed, and a 1.8V power level is provided for the SDD through the third interface; finally, sidebandIO of SSD works at 1.8V level; if the Platform does not support the 1.8V Sideband level, a VIO1.8V pin on an M.2 interface of the Platform is suspended after the Platform is started, the first interface is not connected with 1.8V, and at the moment, loadswitch enable is effective, LDO enable is invalid and closed, and 3.3V is output; finally, the Sideband IO of SSD operates at 3.3V level.
It should be noted that, the foregoing adaptive circuits shown in fig. 6 to 8 are only three implementation circuits, and other forms of modification may be configured according to the concept of the present application, which is not described herein.
According to the level adapting device provided by the embodiment of the application, according to the level adapting device arranged between the first electronic equipment (platform system) and the second electronic equipment (storage system), the second electronic equipment automatically obtains the level (the first level or the second level) adapted to the first electronic equipment according to whether the first interface of the level adapting device has the first level access supported by the first electronic equipment, so that a user using the second electronic equipment does not need to screen the level supported by the first electronic equipment, and further the communication of the first signal between the first electronic equipment and the second electronic equipment is completed. In this way, the second electronic device is enabled to be adapted to support the first electronic device of a different level type.
Based on the same inventive concept, the embodiment of the present application also provides a power supply method of a storage system, as shown in fig. 9,
the level adaptation device comprises a first interface, a second interface, a third interface and an adaptation circuit, wherein the adaptation circuit is connected with the first interface, the second interface and the third interface; the power supply method comprises the following steps:
s901: when the first interface is connected to a first level supported by a first electronic device, the adapting circuit provides the first level adapted to the first electronic device to the memory system contained in a second electronic device through the third interface;
s902: the adaptation circuitry providing a second level adapted to the first electronic device to the memory system through the third interface when the first interface is not connected to the first level; the second level is a level supported by the first electronic device that is accessed from the second interface.
It should be noted that, the power supply method provided by the embodiment of the present application and the level adapting device belong to the same inventive concept, and the terms appearing herein have been explained in detail in the foregoing, and for brevity of description, reference should not be made to the foregoing description for details.
Based on this, the embodiment of the application also provides a storage system, which comprises the level adapting device of any one of the previous claims.
In some embodiments, the storage system may further comprise a PCIe m.2 interface.
In some embodiments, the memory system may further include one or more three-dimensional NAND memories and memory controls.
In some embodiments, the storage system is a solid state disk, SSD.
As mentioned above, the SSD may also include other interfaces, and in this case, the interface used by the platform corresponds to the SSD.
Among other things, the storage system may have one or more three-dimensional (3D) NAND flash memories and a memory controller, as in an example shown in fig. 10, the memory controller 1002 and the plurality of three-dimensional memories 1001 are integrated into the SSD 1000.
Wherein the memory controller is coupled to the memory and configured to control the memory. The memory controller may manage data stored in the memory. In some implementations, the memory controller may be designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) flash drive, or other medium for use in an electronic device such as a personal computer, digital camera, mobile phone, or the like. In some implementations, the memory controller is designed to operate in a high duty cycle environment, SSD, or embedded multimedia card (eMMC), which serves as a data storage and enterprise storage array for mobile devices such as smartphones, tablet computers, laptop computers, and the like. The memory controller may be configured to control operations of the memory, such as read, erase, and program operations. The memory controller may also be configured to manage various functions with respect to data stored or to be stored in memory, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some implementations, the memory controller is further configured to process Error Correction Codes (ECC) with respect to data read from or written to the memory. The memory controller may also perform any other suitable function, such as formatting the memory. The memory controller may communicate with external devices (e.g., hosts) according to a particular communication protocol. For example, the memory controller may communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.
In addition, SSD1000 can also include SSD connector 1003 that couples SSD1000 with a host (e.g., a host).
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the present application.

Claims (14)

1. A level adaptation device, comprising: the device comprises a first interface, a second interface, a third interface and an adaptation circuit, wherein;
the adaptation circuit is connected with the first interface, the second interface and the third interface and is used for: providing a first level adapted to a first electronic device to a second electronic device through the third interface when the first interface is accessed to the first level supported by the first electronic device; providing a second level adapted to the first electronic device to the second electronic device through the third interface when the first interface is not connected to the first level; the second level is a level supported by the first electronic device that is accessed from the second interface.
2. The level adaptation apparatus according to claim 1, wherein the level adaptation apparatus is located in a first electronic device; or at a second electronic device; or independent of the first electronic device and the second electronic device.
3. The level adaptation apparatus according to claim 1, wherein the adaptation circuit comprises: a first component, a second component and a third component, wherein;
a first end of the first component is connected with the first interface, and a second end of the first component is grounded or at a low level; the third end of the first component is connected with the enabling end of the third component; the first component is configured to enable the third component when the first interface is not connected to the first level;
the enabling end and the input end of the second component are connected with the first interface; the output end of the second component is connected with the third interface; the second component is used for enabling the enabling end and the input end to be connected with the first level when the first interface is connected with the first level; the output end provides the first level to the second electronic equipment through the third interface;
the enabling end of the third component is connected with the third end of the first component and is connected with the second interface through a first resistor; the input end of the third component is connected with the second interface; the output end of the third component is connected with the third interface; the third component is used for enabling when the first interface is not connected with the first level, and the input end is connected with a second level through a second interface; the output terminal provides the second level to the second electronic device via the third interface.
4. A level adaptation device according to claim 3, wherein the first component is an N-type metal oxide semiconductor field effect transistor MOSFET; the second component and the third component are both load switches.
5. The level adaptation apparatus according to claim 1, wherein the adaptation circuit comprises: a fourth component, a fifth component and a sixth component, wherein;
the fourth assembly includes: the device comprises a selection end, a first input end, a second input end and an output end; the selection end is connected with the first interface; when the first interface is connected to the first level, a first input end is connected with an output end; when the first interface is not connected with the first level, connecting a second input end with the output end; the first input end is connected with the feedback end of the fifth component through a first resistance element contained in the sixth component; the second input end is connected with the feedback end of the fifth component through a second resistance element contained in the sixth component; the output end is grounded;
the fifth component comprises an enabling end, an input end, an output end and a feedback end; the enabling end and the input end are connected with the second interface and used for accessing a second level; the feedback end is connected with the output end through a third resistance element contained in the sixth component; the output end is connected with the third interface and is used for providing the first level for second electronic equipment through the third interface based on the first resistance element and the third resistance element or providing the first level for second electronic equipment through the third interface based on the second resistance element and the third resistance element when the first interface is connected with the first level; and when the first interface is not connected with the first level, providing the second level for second electronic equipment through the third interface based on the second resistance element and the third resistance element, or providing the second level for second electronic equipment through the third interface based on the first resistance element and the third resistance element.
6. The level adaptation device according to claim 5, wherein the fourth component is an analog switch; the fifth component is a low voltage regulator.
7. The level adaptation apparatus according to claim 5, wherein the sixth component further comprises a fourth resistive element coupled between the second interface and an enable terminal of the fifth component for reducing a voltage coupled to the enable terminal.
8. The level adaptation apparatus according to claim 1, wherein the adaptation circuit comprises: a seventh component and an eighth component, wherein;
the input end of the seventh component is connected with the input end of the eighth component; the output end of the seventh component is rich and the output end of the eighth component is connected;
the input end of the seventh component is connected with the input end of the eighth component and the second interface, and is used for accessing the second level;
the enabling end of the seventh component and the enabling end of the eighth component are connected with the first interface and are used for enabling the seventh component when the first interface is accessed to the first level; enabling the eighth component when the first interface does not access the first level;
the output end of the seventh component is connected with the third interface and is used for providing the first level for the second electronic equipment through the third interface when the seventh component is enabled;
and the output end of the eighth component is connected with the third interface and is used for providing the second level for the second electronic equipment through the third interface when the second level is enabled.
9. The level adaptation device according to claim 8, wherein the seventh component is a low voltage regulator; the eighth component is a load switch having an inverted enable signal with the seventh component.
10. A memory system, characterized in that the memory system comprises a level adaptation device as claimed in any one of claims 1 to 9.
11. The storage system of claim 10, wherein the storage system further comprises: one or more memories; and a memory controller coupled to the one or more memories; the memory controller is configured to control various operations of the one or more memories.
12. The storage system of claim 10, wherein the storage system further comprises: PCIe m.2 interface.
13. The storage system of claim 10, wherein the storage system is a solid state disk, SSD.
14. The power supply method of the storage system is characterized by being applied to a level adapting device, wherein the level adapting device comprises a first interface, a second interface, a third interface and an adapting circuit, and the adapting circuit is connected with the first interface, the second interface and the third interface; the power supply method comprises the following steps:
when the first interface is connected to a first level supported by a first electronic device, the adaptation circuit provides the first level adapted to the first electronic device for a storage system contained in a second electronic device through the third interface;
the adaptation circuit provides a second level adapted to the first electronic device to the storage system via the third interface when the first interface is not connected to the first level; the second level is a level supported by the first electronic device that is accessed from the second interface.
CN202210752325.XA 2022-06-28 2022-06-28 Level adaptation device, storage system and power supply method Active CN115017069B (en)

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