CN115017069A - Level adaptation device, storage system and power supply method - Google Patents

Level adaptation device, storage system and power supply method Download PDF

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Publication number
CN115017069A
CN115017069A CN202210752325.XA CN202210752325A CN115017069A CN 115017069 A CN115017069 A CN 115017069A CN 202210752325 A CN202210752325 A CN 202210752325A CN 115017069 A CN115017069 A CN 115017069A
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interface
level
component
electronic device
adaptation
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CN115017069B (en
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郑海军
武恒文
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a level adaptation device, a storage system and a power supply method. Wherein the level adaptation means comprises: the method comprises the following steps: the device comprises a first interface, a second interface, a third interface and an adapting circuit, wherein the first interface is connected with the second interface; the adaptation circuit is connected with the first interface, the second interface and the third interface, and is configured to: when the first interface is accessed to a first level supported by a first electronic device, the first level adaptive to the first electronic device is provided for a second electronic device through the third interface; when the first interface does not access the first level, providing a second level adaptive to the first electronic equipment to the second electronic equipment through the third interface; the second level is a level accessed from the second interface supported by the first electronic device.

Description

Level adaptation device, storage system and power supply method
Technical Field
The present invention relates to the field of memory-related circuits, and in particular, to a level adaptation device, a memory system, and a power supply method.
Background
With the advent of the big data era, the demand for data storage is becoming higher and higher, and the hard disk is gaining wide attention in the industry as one of the media for storing data, especially the attention on Solid State Drives (SSD). However, since the types of communication levels supported by the platform communicating with the SSD are many, the platform used by the SSD is limited, and therefore, how to adapt the SSD to complete the communication with the platform is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of this, the present invention provides a level adaptation apparatus, a storage system and a power supply method, so as to automatically adapt a communication level of an SSD to a level supported by a platform, thereby completing communication between the platform and the SSD.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a level adaptation apparatus, including: the device comprises a first interface, a second interface, a third interface and an adapting circuit, wherein the first interface is connected with the second interface;
the adaptation circuit is connected with the first interface, the second interface and the third interface, and is configured to: when the first interface is accessed to a first level supported by a first electronic device, the first level adaptive to the first electronic device is provided for a second electronic device through the third interface; when the first interface does not access the first level, providing a second level adaptive to the first electronic equipment to the second electronic equipment through the third interface; the second level is a level accessed from the second interface supported by the first electronic device.
In a second aspect, an embodiment of the present invention provides a memory system, including the level adaptation apparatus in any one of the foregoing embodiments.
In a third aspect, an embodiment of the present invention further provides a power supply method for a storage system, where the power supply method is applied to a level adaptation device, the level adaptation device includes a first interface, a second interface, a third interface, and an adaptation circuit, and the adaptation circuit is connected to the first interface, the second interface, and the third interface; the power supply method comprises the following steps:
when the first interface is accessed to a first level supported by a first electronic device, the adaptation circuit provides the first level adapted with the first electronic device to the storage system contained in a second electronic device through the third interface;
when the first interface does not access the first level, the adaptation circuit provides a second level adapted with the first electronic device to the storage system through the third interface; the second level is a level accessed from the second interface supported by the first electronic device.
The embodiment of the invention provides a level adaptation device, a storage system and a power supply method. Wherein the level adaptation means comprises: the device comprises a first interface, a second interface, a third interface and an adapting circuit, wherein the first interface is connected with the second interface; the adaptation circuit is connected with the first interface, the second interface and the third interface, and is configured to: when the first interface is accessed to a first level supported by a first electronic device, the first level adaptive to the first electronic device is provided for a second electronic device through the third interface; when the first interface does not access the first level, providing a second level adaptive to the first electronic equipment to the second electronic equipment through the third interface; the second level is a level accessed from the second interface supported by the first electronic device. According to the power supply method for the level adaptation device and the storage system, which are provided by the embodiment of the invention, the level adaptation device is arranged between the first electronic equipment (platform system) and the second electronic equipment (storage system), and the second electronic equipment is automatically enabled to obtain the level (the first level or the second level) adapted to the first electronic equipment according to whether the first interface of the level adaptation device is accessed by the first level supported by the first electronic equipment, so that a user using the second electronic equipment does not need to screen the level supported by the first electronic equipment, and further the communication of the first signal between the first electronic equipment and the second electronic equipment is completed. In this way, the second electronic device is enabled to adapt to the first electronic device supporting different level types.
Drawings
Fig. 1 is a schematic structural diagram of a level adaptation apparatus according to an embodiment of the present invention;
fig. 2 is a first schematic diagram illustrating a problem existing between a first electronic device and a second electronic device according to an embodiment of the present invention;
fig. 3 is a second schematic diagram illustrating a problem existing between a first electronic device and a second electronic device according to an embodiment of the present invention;
fig. 4 is a third schematic diagram illustrating a problem existing between the first electronic device and the second electronic device according to the embodiment of the present invention;
fig. 5 is a schematic diagram illustrating an operation principle of a level adaptation apparatus according to an embodiment of the present invention;
fig. 6 is a first schematic structural diagram of an adaptation circuit according to an embodiment of the present invention;
fig. 7 is a second schematic structural diagram of an adaptation circuit according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of an adaptation circuit according to an embodiment of the present invention;
fig. 9 is a flowchart illustrating a level adaptation method according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a solid state disk according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without any inventive step, are within the scope of the present invention. The embodiments and features of the embodiments of the present invention may be arbitrarily combined with each other without conflict. The flow charts in the figures show a logical order, but in some cases, the steps shown or described may be performed out of order here.
Referring to fig. 1, as shown therein, an embodiment of the present invention provides a level adaptation apparatus 100, which includes: a first interface 101, a second interface 102, a third interface 103 and an adaptation circuit 104, wherein;
the adaptation circuit is connected with the first interface, the second interface and the third interface, and is used for: when the first interface is accessed to a first level supported by a first electronic device, the first level adaptive to the first electronic device is provided for a second electronic device through the third interface; when the first interface does not access the first level, providing a second level adaptive to the first electronic equipment to the second electronic equipment through the third interface; the second level is a level accessed from the second interface supported by the first electronic device.
It should be noted that the first electronic device and the second electronic device may be any terminal or platform capable of communicating by using a certain interface protocol, for example, the first electronic device may be a platform having a Peripheral Component Interconnect express (PCIe) m.2 interface; the second electronic device may be an SSD having a PCIe m.2 interface. For another example, the first electronic device may also be a platform with a PCIe M.3 interface; the second electronic device may be an SSD of a PCIe M.3 interface, or the like. It should be clear that the level adaptation means in the embodiments of the present invention may also be applied to devices with other types of interfaces. Furthermore, the operating principle of the level adaptation means is the same regardless of which type of device the first electronic device and the second electronic device are. Only the first electronic equipment is taken as a platform with a PCIe M.2 interface; the second electronic device is an SSD with PCIe m.2 interface as an example to explain the operation principle and structure of the level adaptation apparatus. In a case that is not specifically described below, the first electronic device is a platform having a PCIe m.2 interface; the second electronic device is an SSD with a PCIe M.2 interface.
When using the SSD of the PCIe m.2 interface, it has all or part of relevant signals such as PEWAKE #, CLKREQ #, PERST #, PLA _ S3#, PLN #, PWRDIS, etc. for auxiliary communication with the platform end, which is generally called Sideband Signal (Sideband Signal). The Sideband Signal is to complete communication normally, and communication levels of the Sideband input/output (IO) interfaces of the SSD and the platform are to be matched correctly, as shown in fig. 2, that is, both have the same level. Based on the matching requirement of the Sineband Signal communication level, the SSD with different communication levels and the platform cannot normally communicate with each other, so that the SSD supporting the A communication level cannot work on the platform supporting the B communication level; the SSD supporting the B communication level cannot operate on the platform supporting the a communication level. Specific examples can be seen in fig. 3 and 4.
Based on this, the level adaptation device provided by the embodiment of the invention can enable the SSD to automatically adapt the communication level of the platform end for the Sideband Signal communication, so that the SSD and the platform can complete the Sideband Signal communication.
Specifically, the operation principle of the level adaptation device provided by the embodiment of the present invention is as follows: when a first interface is accessed to a first level supported by the first electronic equipment, providing the first level to the second electronic equipment through the third interface; providing a second level to the second electronic device through the third interface when the first interface does not access the first level supported by the first electronic device; a level supported by the first electronic device accessed from a second interface at the second level. That is, when the first electronic device supports the first level, the adaptation circuit automatically configures the first level for the second electronic device; when the first electronic device does not support the first level, since the first electronic device supports either the first level or the second level, the adaptation circuit automatically configures the second level for the second electronic device to match the levels of the first electronic device and the second electronic device.
In some embodiments, the first interface is connected to a first electronic device, and is used for accessing or not accessing the first level. When the first electronic device supports the first level, the first electronic device can output the first level, and the first interface is connected to the first level; when the first electronic device does not support the first level, the first electronic device does not output the first level, and the first interface does not access the first level.
It should be noted that, because the two levels supported by the first electronic device, i.e. the platform side, are currently two, when one of the two levels is not supported, the other level is necessarily supported, that is, the embodiment of the present invention provides the level adaptation apparatus with only two level adaptations. When the first electronic device supports more levels, its implementation circuit may be constructed based on the inventive concept of the embodiment of the present invention. The first electronic device supports a circuit configuration of two levels, that is, the first electronic device supports a first level or a second level without specific description in the following description. For example, the first level may be 1.8 volts (V); the second level may be 3.3V. The first level may be 3.3V, and the second level may be 1.8V.
For example, as shown in fig. 5, after the platform is powered on, when the first electronic device outputs 1.8V, it is indicated that the first electronic device supports 1.8V, at this time, the first interface is connected to the 1.8V, after the first interface is connected to 1.8V, under the action of the adaptation circuit, 1.8V is output at the third interface, and the 1.8V is provided to the second electronic device as a communication level thereof; when the first electronic device does not output 1.8V, it indicates that the first electronic device does not support 1.8V, and then it supports 3.3V, and at this time, the first interface does not switch in level, and at this time, under the action of the adaptation circuit, 3.3V is output at the third interface, and the 3.3V is provided to the second electronic device, and 3.3V is used as its communication level. It should be understood that fig. 5 is only an example, and the implementation principle may also be implemented according to whether the first electronic device outputs 3.3V, or other levels, which need to be adjusted according to actual situations, and details are not described here.
In some embodiments, the level adaptation means is located at the first electronic device; or at a second electronic device; or independent of the first electronic device and the second electronic device.
It is understood that the level adaptation means may be provided in the first electronic device or in the second electronic device, or may be independent of the first electronic device and the second electronic device. That is, the level adaptation device may be disposed inside the platform or the SSD, or may be separately disposed to help the SSD implement the level adaptation.
In practical implementation, the adaptation circuit in the level adaptation arrangement may have a variety of implementations.
In some embodiments, the adaptation circuit comprises: a first component, a second component, and a third component, wherein;
the first end of the first component is connected with the first interface, and the second end of the first component is grounded or at a low level; the third end of the first component is connected with the enabling end of the third component; the first component is used for enabling the third component when the first interface does not access the first level;
the enabling end and the input end of the second component are both connected with the first interface; the output end of the second component is connected with the third interface; the second component is used for enabling an enabling end and an input end to be connected to the first level when the first interface is connected to the first level; the output end provides the first level to second electronic equipment through the third interface;
an enabling end of the third component is connected with the third end of the first component and is connected with the second interface through a first resistor; the input end of the third component is connected with the second interface; the output end of the third component is connected with the third interface; the third component is used for enabling when the first interface does not access the first level, and the input end accesses a second level through a second interface; the output end provides the second level to the second electronic equipment through the third interface.
It should be noted that "first", "second", and "third" of the first component, the second component, and the third component are described herein for convenience of description only and are not intended to limit the present invention. The switching characteristics of the first, second, and third components are used regardless of the types of the components, and therefore, the first, second, and third components may be any components having switching characteristics that can implement the above-described circuit functions.
As an alternative embodiment, as shown in fig. 6, the first component is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET); the second assembly and the third assembly are both load switches.
It should be noted that, in fig. 6, 1041 is the second component, i.e. Load Switch 1; 1042 is the third element, Load Switch 2; 1043 is a first component, namely an NMOS transistor.
The working principle of the adapter circuit with the structure can be as follows: when the first electronic device outputs a first level, the first interface is switched on to the first level, the NMOS transistor is turned on, the enable end of the Load Switch2 is grounded, so that the Load Switch2 is turned off, and a second level cannot be output to a second electronic device through a third interface; the first level is also input to an enable end of the Load Switch1, so that the Load Switch1 is turned on, the first level is output, and the second electronic device (or SSD) is provided through the third interface; when the first electronic device does not output the first level, the first interface is not switched on the first level, the NMOS transistor is turned off, the enable terminal of the Load Switch2 has a voltage input, so that the Load Switch2 is turned on, the second level can be output to the second electronic device through the three interfaces, and because there is no first level, the Load Switch1 is turned off, there is no output level, and at this time, the whole adaptation circuit outputs the second level to the second electronic device through the Load Switch 2.
For example, the first electronic device is a Platform (Platform); when the second electronic device is an SSD and the first level is 1.8V, the actual operation of the adaptation circuit according to fig. 6 may be as follows: if the Platform supports a 1.8V Sineband level, VIO1.8V pins on an M.2 interface of Platform after startup can output a 1.8V level, the 1.8V level can be output to a Loadswitch1 and an NMOS through a first interface, wherein the NMOS is turned on to turn off the Loadswitch2, at this time, the 3.3V level cannot be output to a Controller of the SSD, meanwhile, under the work of 1.8V, the Loadswitch1 works to output a 1.8V to the Controller of the SSD through a third interface, and finally, the Sineband IO of the SSD works at the level of 1.8V. If the Platform does not support the 1.8V substation level, VIO1.8V pins on the M.2 interface of Platform are suspended after the Platform is started; the Loadswitch1 has no 1.8V level input, so does not output 1.8V level to the Controller of the SSD; at this time, the NMOS does not have a 1.8V level input, the NMOS is turned off, the Loadswitch2 is turned on, the 3.3V level is output to the Controller of the SSD, and finally, the Sideband IO of the SSD operates at the 3.3V level.
It should be noted that, here, the first component may also be a P-type MOSFET, and the second component and the third component are both load switches, in this case, to achieve the above function, a drain terminal of the P-type MOSFET may be connected to ground; the source terminal of the P-type MOSFET is connected to the enable terminal of the third component switch. The connection mode of the two components and the second component is unchanged.
In some embodiments, the adaptation circuit 104 may also include: a fourth component, a fifth component and a sixth component, wherein;
the fourth assembly comprises: the device comprises a selection end, a first input end, a second input end and an output end; the selection end is connected with the first interface; when the first interface is switched in the first level, connecting a first input end with an output end; connecting a second input terminal with the output terminal when the first interface does not access the first level; the first input end is connected with the feedback end of the fifth component through a first resistance element contained in the sixth component; the second input end is connected with the feedback end of the fifth component through a second resistance element contained in the sixth component; the output end is grounded;
the fifth component comprises an enabling end, an input end, an output end and a feedback end; the enabling end and the input end are connected with the second interface and used for accessing a second level; the feedback end is connected with the output end through a third resistance element contained in the sixth component; the output end is connected with the third interface, and is configured to provide the first level to a second electronic device through the third interface based on the first resistive element and the third resistive element, or provide the first level to the second electronic device through the third interface based on the second resistive element and the third resistive element, when the first interface is switched into the first level; when the first interface does not access the first level, providing the second level to a second electronic device through the third interface based on the second resistive element and the third resistive element, or providing the second level to the second electronic device through the third interface based on the first resistive element and the third resistive element.
As an example, as shown in fig. 7, the fourth component is an analog switch; and the fifth component is a low-voltage regulator. Wherein the sixth component comprises a first resistor, a second resistor, and a third resistor.
Note that, in fig. 7, 1044 is a fourth component, namely, Analog Swich; 1045 is a fifth component, also called LDO; 1046 is a sixth element including resistors R1, R2, R3, R4.
Under the structure of the adapter circuit, the working principle is as follows: the LDO voltage output control meets the conditions that Vout is Vfb (1+ R3/R1) or Vout is Vfb (1+ R3/R2), wherein Vfb is a fixed value of the LDO design, and Vout can be 1.8V or Vout can be 3.3V by selecting proper resistance combinations R1, R2 and R3; on this basis, it can be designed that if the Platform supports 1.8V Sideband level, after the Platform is turned on, the VIO1.8V pin IN the m.2 interface of Platform will output 1.8V level, and the 1.8V level is output to the selection pin given to Analog Switch through the first interface, so that the IN2 pin and the OUT pin are conducted, and through the cooperation of R2 and R3, the output Vout of the LDO is Vfb (1+ R3/R2) 1.8V; finally, the 1.8V is provided to the SSD through the third interface, so that the Sideband IO of the SSD operates at a 1.8V level. If the Platform does not support the 1.8V substation level, VIO1.8V pins on the M.2 interface of Platform are suspended after the Platform is started; at this time, the selection pin IN the Analog Switch has no level input, the IN1 pin is turned on with the OUT pin according to the design time, and the output Vout of the LDO is Vfb (1+ R3/R1) to 3.3V through the matching of R1 and R3; finally, the 3.3V is provided to the SSD through the third interface, so that the Sideband IO of the SSD operates at a 3.3V level; it should be noted that the control logic of Analog Switch can be reversed, and the R1 and R2 resistors can be exchanged accordingly.
In some embodiments, the sixth component further includes a fourth resistive element, connected between the second interface and the enable terminal of the fifth component, for reducing a voltage connected to the enable terminal.
It should be noted that, the fourth resistor is used for the safety of the first low-voltage stabilizing component, the second level is not directly input to the enable terminal of the first low-voltage stabilizing component, but the voltage is divided by a certain resistor, that is, the fourth resistor is connected in series between the second interface and the enable terminal of the first low-voltage stabilizing component. And the size of the fourth resistor is designed according to actual requirements.
In other embodiments, the adaptation circuit may also include:
a seventh component and an eighth component, wherein;
the input end of the seventh component is connected with the input end of the eighth component; the output end of the seventh component is connected with the output end of the eighth component;
the input end of the seventh component and the input end of the eighth component are connected with the second interface, and the seventh component and the eighth component are used for accessing the second level;
the enable terminal of the seventh component and the enable terminal of the eighth component are connected to the first interface, and are configured to enable the seventh component when the first interface is switched to the first level; enabling the eighth component when the first interface does not access the first level;
an output end of the seventh component, connected to the third interface, configured to provide the first level to the second electronic device through the third interface when enabled;
and the output end of the eighth component is connected with the third interface, and is used for providing the second level for the second electronic equipment through the third interface when the eighth component is enabled.
As an alternative embodiment, as shown in fig. 8, the seventh component is a low voltage regulator; the eighth component is a load switch having a reverse enable signal with the seventh component.
It should be noted that, in fig. 8, 1047 is a seventh component, that is, LDO1.8V; 1048 is the eighth element, Load Switch. The enable signals of the seventh and eighth elements are inverse signals, as shown in fig. 8, the input terminal of LDO1.8V is connected to the input terminal of Load Switch; LDO1.8V is connected with the output end of Load Switch; LDO1.8V, the input end enable end and the Load Switch enable end are adjacent to the first electronic device through the first interface, but the enable logics of the two are exactly opposite, that is, when LDO1.8V is enabled, the Load Switch is closed; when Load Switch is enabled, LDO1.8V is closed.
Under this adaptation structure, its theory of operation is as follows: an integrated IC integrates the LDO and the Loadswitch to form a gating circuit, and the LDO is enabled and controlled to be highly effective; loadswitch enable control is active low; if the Platform supports 1.8V SIDeband level, VIO1.8V pin on Platform's M.2 interface will output 1.8V after starting up; the first interface is accessed with 1.8V, at the moment, the LDO is enabled to be effective, the Loadswitch is disabled to be closed, and the SDD is provided with 1.8V power supply level through the third interface; finally, the SidebandIO of the SSD works at a 1.8V level; if the Platform does not support 1.8V substation level, VIO1.8V pins on an M.2 interface of Platform are suspended after the Platform is started, the first interface is not accessed by 1.8V, at the moment, the Loadswitch enable is effective, the LDO enable is disabled and closed, and 3.3V is output; finally, the Sideband IO of the SSD operates at 3.3V level.
It should be noted that the adaptation circuits shown in fig. 6 to fig. 8 are only three implementation circuits, and other modifications may also be configured according to the idea of the present invention, and are not described herein again.
According to the level adaptation device provided by the embodiment of the invention, the level adaptation device is arranged between the first electronic device (platform system) and the second electronic device (storage system), and the second electronic device is automatically enabled to obtain the level (the first level or the second level) adapted to the first electronic device according to whether the first interface of the level adaptation device is accessed by the first level supported by the first electronic device, so that a user using the second electronic device does not need to screen the level supported by the first electronic device, and further the communication of the first signal between the first electronic device and the second electronic device is completed. In this way, the second electronic device is enabled to adapt to the first electronic device supporting different level types.
Based on the same inventive concept, the embodiment of the present invention further provides a power supply method of a storage system, as shown in fig. 9,
the level adaptation device is applied to a level adaptation device, the level adaptation device comprises a first interface, a second interface, a third interface and an adaptation circuit, and the adaptation circuit is connected with the first interface, the second interface and the third interface; the power supply method comprises the following steps:
s901: when the first interface accesses a first level supported by a first electronic device, the adaptation circuit provides the first level adapted with the first electronic device to the memory system contained in a second electronic device through the third interface;
s902: the adaptation circuit provides a second level adapted with the first electronic device to the memory system through the third interface when the first interface does not access the first level; the second level is a level accessed from the second interface supported by the first electronic device.
It should be noted that the power supply method provided by the embodiment of the present invention belongs to the same inventive concept as the aforementioned level adaptation apparatus, and the terms appearing herein have been explained in detail in the foregoing, so that for the sake of brevity of the description, no repeated explanation is needed here, and specifically, refer to the foregoing description.
Based on this, an embodiment of the present invention further provides a storage system, including the level adaptation apparatus described in any one of the foregoing.
In some embodiments, the storage system may further include a PCIe m.2 interface.
In some embodiments, the memory system may also include one or more three-dimensional NAND memories and memory controls.
In some embodiments, the storage system is a solid state disk, SSD.
As described above, the SSD may include other interfaces, and in this case, the interface used by the platform corresponds to the SSD.
Among them, the storage system may have one or more three-dimensional (3D) NAND flash memories and a memory controller, as in an example shown in fig. 10, a memory controller 1002 and a plurality of three-dimensional memories 1001 are integrated into an SSD 1000.
Wherein the memory controller is coupled to the memory and configured to control the memory. The memory controller may manage data stored in the memory. In some implementations, the memory controller may be designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and so forth. In some embodiments, the memory controller is designed for operation in a high duty cycle environment SSD or embedded multimedia card (eMMC) that is used as a data storage and enterprise storage array for mobile devices such as smart phones, tablet computers, laptop computers, and the like. The memory controller may be configured to control operations of the memory, such as read, erase, and program operations. The memory controller may also be configured to manage various functions with respect to data stored or to be stored in the memory, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some embodiments, the memory controller is further configured to process an Error Correction Code (ECC) with respect to data read from or written to the memory. The memory controller may also perform any other suitable function, such as formatting the memory. The memory controller may communicate with external devices (e.g., hosts) according to a particular communication protocol. For example, the memory controller may communicate with the external device via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system small interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and so forth.
Furthermore, SSD1000 may also include SSD connector 1003 that couples SSD1000 with a host (e.g., host).
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (14)

1. A level adaptation apparatus, comprising: the device comprises a first interface, a second interface, a third interface and an adapting circuit, wherein the first interface is connected with the second interface;
the adaptation circuit is connected with the first interface, the second interface and the third interface, and is configured to: when the first interface is accessed to a first level supported by a first electronic device, the first level adaptive to the first electronic device is provided for a second electronic device through the third interface; when the first interface does not access the first level, providing a second level adaptive to the first electronic equipment to the second electronic equipment through the third interface; the second level is a level supported by the first electronic device accessed from the second interface.
2. The level adaptation device of claim 1, wherein the level adaptation device is located in a first electronic device; or at a second electronic device; or independent of the first electronic device and the second electronic device.
3. The level adaptation device of claim 1, wherein the adaptation circuit comprises: a first component, a second component, and a third component, wherein;
the first end of the first component is connected with the first interface, and the second end of the first component is grounded or at a low level; the third end of the first component is connected with the enabling end of the third component; the first component is used for enabling the third component when the first interface does not access the first level;
the enabling end and the input end of the second component are both connected with the first interface; the output end of the second component is connected with the third interface; the second component is used for enabling an enabling end and an input end to be connected to the first level when the first interface is connected to the first level; the output end provides the first level to second electronic equipment through the third interface;
an enabling end of the third component is connected with the third end of the first component and is connected with the second interface through a first resistor; the input end of the third component is connected with the second interface; the output end of the third component is connected with the third interface; the third component is used for enabling when the first interface does not access the first level, and the input end accesses a second level through a second interface; the output end provides the second level to the second electronic equipment through the third interface.
4. The level adaptation device of claim 3, wherein the first component is an N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET); the second assembly and the third assembly are both load switches.
5. The level adaptation device of claim 1, wherein the adaptation circuit comprises: a fourth component, a fifth component and a sixth component, wherein;
the fourth assembly comprises: the device comprises a selection end, a first input end, a second input end and an output end; the selection end is connected with the first interface; when the first interface is switched in the first level, connecting a first input end with an output end; when the first interface is not accessed to the first level, connecting a second input end with the output end; the first input end is connected with the feedback end of the fifth component through a first resistance element contained in the sixth component; the second input end is connected with the feedback end of the fifth component through a second resistance element contained in the sixth component; the output end is grounded;
the fifth component comprises an enabling end, an input end, an output end and a feedback end; the enabling end and the input end are connected with the second interface and used for accessing a second level; the feedback end is connected with the output end through a third resistance element contained in the sixth component; the output end is connected with the third interface, and is configured to provide the first level to a second electronic device through the third interface based on the first resistive element and the third resistive element, or provide the first level to the second electronic device through the third interface based on the second resistive element and the third resistive element, when the first interface is switched into the first level; when the first interface does not access the first level, providing the second level to a second electronic device through the third interface based on the second resistive element and the third resistive element, or providing the second level to the second electronic device through the third interface based on the first resistive element and the third resistive element.
6. The level adaptation device of claim 5, wherein the fourth component is an analog switch; and the fifth component is a low-voltage regulator.
7. The apparatus according to claim 5, wherein the sixth module further comprises a fourth resistor element connected between the second interface and the enable terminal of the fifth module for reducing the voltage connected to the enable terminal.
8. The level adaptation device of claim 1, wherein the adaptation circuit comprises: a seventh component and an eighth component, wherein;
the input end of the seventh component is connected with the input end of the eighth component; the output end of the seventh component is connected with the output end of the eighth component;
the input end of the seventh component and the input end of the eighth component are connected with the second interface, and the seventh component and the eighth component are used for accessing the second level;
the enable terminal of the seventh component and the enable terminal of the eighth component are connected to the first interface, and are configured to enable the seventh component when the first interface is switched to the first level; enabling the eighth component when the first interface does not access the first level;
an output end of the seventh component, connected to the third interface, configured to provide the first level to the second electronic device through the third interface when enabled;
and the output end of the eighth component is connected with the third interface, and is used for providing the second level for the second electronic equipment through the third interface when the eighth component is enabled.
9. The level adaptation device of claim 8, wherein the seventh component is a low voltage regulator; the eighth component is a load switch having a reverse enable signal with the seventh component.
10. A memory system, characterized in that the memory system comprises a level adaptation device according to any one of claims 1 to 9.
11. The storage system according to claim 10, further comprising: one or more memories; and a memory controller coupled with the one or more memories; the memory controller is configured to control various operations of the one or more memories.
12. The storage system according to claim 10, further comprising: PCIe m.2 interface.
13. The storage system of claim 10, wherein the storage system is a Solid State Disk (SSD).
14. The power supply method of the storage system is characterized by being applied to a level adaptation device, wherein the level adaptation device comprises a first interface, a second interface, a third interface and an adaptation circuit, and the adaptation circuit is connected with the first interface, the second interface and the third interface; the power supply method comprises the following steps:
when the first interface is accessed to a first level supported by a first electronic device, the adaptation circuit provides the first level adapted with the first electronic device to the storage system contained in a second electronic device through the third interface;
when the first interface does not access the first level, the adaptation circuit provides a second level adapted with the first electronic device to the storage system through the third interface; the second level is a level accessed from the second interface supported by the first electronic device.
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CN103150274A (en) * 2011-08-16 2013-06-12 爱思开海力士有限公司 Integrated circuit, system including the same, and operation method of the system
US20160259385A1 (en) * 2015-03-05 2016-09-08 Micron Technology, Inc. Impedance adjustment
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