TWI570418B - Device and method of detecting signal delay - Google Patents

Description

Device and method for measuring signal delay time

The present invention relates to a signal testing apparatus and method, and more particularly to a testing apparatus and method for delay time of a circuit output signal.

With the rapid development of semiconductor technology, the implementation functions and performance requirements of Integrated Circuits (ICs) are also increasing. However, as semiconductor processes shrink, the effects of parasitic capacitance of semiconductor components are more pronounced. The parasitic capacitance of some components in an integrated circuit can cause a delay in the signal in the integrated circuit. Signal delay time is one of the important parameters when evaluating the performance of an integrated circuit. Therefore, how to accurately and efficiently measure the delay time of the output signal of the integrated circuit is an important issue.

Currently, the industry mostly uses an oscilloscope to measure the delay time. The oscilloscope samples the signal at a sampling rate for the input signal and displays the waveform sampled on the oscilloscope's screen. The oscilloscope measures and calculates the sampled and displayed waveforms to obtain various parameters of the input signal (such as frequency, amplitude, delay time, etc.). However, the price of an oscilloscope is quite expensive. If you only need to measure the delay time of the output signal of the circuit, and do not need to obtain other parameters or waveforms of the output signal, adding an oscilloscope for this demand will greatly increase the cost and reduce the competitiveness.

In addition, with the development of technology, signal processing speed and transmission speed have also increased significantly. Generally, the sampling rate of an oscilloscope cannot accurately sample the input signal, so the sampled waveform is inevitably subject to distortion. This distortion may lead to the desired measurement. The signal parameters are not accurate.

There are two general methods for solving this problem, one is to use an oscilloscope with a higher sampling rate, and the other is to down-convert the input signal and then sample. However, an oscilloscope with a high sampling rate means a more expensive price or a higher cost, as described above, which will greatly increase the cost and reduce the competitiveness. If the input signal is down-converted and then sampled, the frequency, voltage level, phase, etc. deviation generated during the frequency reduction process will cause the measurement result to have an error value.

Accordingly, it is an object of the present invention to provide a method for accurately measuring the delay time of a signal, which can reduce costs and thereby enhance competitiveness.

An embodiment of the present disclosure is a method for measuring a signal delay time, comprising: inputting a first signal and a second signal to a logic circuit to obtain an output signal; measuring an average voltage of the output signal Obtaining a first voltage; and determining a delay time of the second signal relative to the first signal according to a difference between the first voltage and a reference voltage.

One embodiment of the present disclosure is a device for measuring signal delay time, comprising: a circuit to be tested, a clock generator, a logic circuit, and a voltage measuring device. The circuit to be tested includes an input terminal and an output terminal. The clock generator includes an output connected to an input of the circuit under test. The logic circuit comprises a first input end, a second input end and an output end, the first input end is connected to the output end of the clock generator, and the second input end is connected to the output end of the circuit to be tested. The voltage measuring device is connected to the output of the logic circuit.

1‧‧‧ test board

2‧‧‧ clock generator

3‧‧‧circuit to be tested

4‧‧‧Power supply

5‧‧‧Logical circuits

6‧‧‧ voltmeter

S1‧‧‧ measures the average voltage of the first signal to obtain the reference voltage

S2‧‧‧ input the first signal to the circuit to be tested to obtain the second signal

S3‧‧‧ input the first signal and the second signal to the logic circuit to obtain the output signal

S4‧‧‧Measure the average voltage of the output signal to obtain the first voltage

S5‧‧‧Actain the duty cycle of the output signal based on the difference between the reference voltage and the first voltage

S6‧‧‧ according to the duty cycle, to determine the delay time of the second signal relative to the first signal

1 is a block diagram of a measurement signal delay time in accordance with an embodiment of the present disclosure.

2 is a schematic diagram of a method of measuring a signal delay time in accordance with an embodiment of the present disclosure.

3 is a schematic diagram of a logic circuit in accordance with an embodiment of the present invention.

4 is a schematic diagram of a logic circuit in accordance with an embodiment of the present invention.

Figure 5 is a schematic illustration of a logic circuit in accordance with an embodiment of the present invention.

1 discloses a block diagram of a measurement signal delay time in accordance with an embodiment of the present disclosure. As shown in FIG. 1, the test board 1 may include a clock generator 2, a circuit under test 3, a power supply 4, and a logic circuit 5.

The test board 1 can be a printed circuit board or other suitable circuit board. The printed circuit board can be, but is not limited to, a single panel, a double panel, or a multilayer board.

The clock generator 2 is any circuit that can generate signals of different frequencies according to requirements. The output of the clock generator 2 is connected to the input of the circuit under test 3 and the first input of the logic circuit 5.

The circuit under test 3 can be a discrete circuit or an integrated circuit. The output of the circuit under test 3 is connected to the second input of the logic circuit 5.

The power supply 4 is used to supply power to the clock generator 2, the circuit under test 3, and the logic circuit 5.

The logic circuit 5 can determine a duty cycle of the output signal according to the phase difference between the input signal of the first input terminal and the input signal of the second input terminal. In other words, the logic circuit 5 can determine the logic value of the output signal according to the logical value relationship between the input signal of the first input terminal and the input signal of the second input terminal. According to an embodiment of the present disclosure, the logic circuit 5 may be an AND gate, a NAND gate, an OR gate, a NOR gate, a mutual exclusion or a gate (XOR gate). ), one of the flip flops, or a combination thereof.

The voltmeter 6 is a voltmeter that measures the average voltage. According to another embodiment of the present disclosure, the voltmeter is a three-meter power meter. According to another embodiment of the present disclosure, the voltmeter is a three-meter power meter that can measure a voltage of less than 10 millivolts. The voltmeter 6 is connected to the output of the logic circuit 5.

The clock generator 2 is configured to generate a first signal having a selected frequency and input the first signal to an input end of the circuit under test 3 and a first input end of the logic circuit 5. 3 circuits to be tested The second signal is generated according to the first signal, and the second signal is input to the second input of the logic circuit 5. The logic circuit 5 generates an output signal according to the first signal of the first input end and the second signal of the second input end. The voltmeter 6 is used to measure an average voltage value of an output signal of the logic circuit 5.

2 is a schematic diagram of a method of measuring a signal delay time in accordance with an embodiment of the present disclosure. In step S1, the average voltage of the first signal generated by the clock generator is measured to obtain a reference voltage. In step S2, the first signal generated by the clock generator is input to the input end of the circuit to be tested, and the second signal is obtained at the output end of the circuit to be tested. In step S3, the first signal and the second signal are input to a logic circuit to obtain an output signal. In step S4, the average voltage of the output signal is measured to obtain a first voltage. In step S5, the duty cycle of the output signal is obtained according to the difference between the reference voltage and the first voltage. In step S6, the delay time of the second signal relative to the first signal is determined according to the duty cycle.

According to an embodiment of the present invention, the first signal input to the first input end of the logic circuit, the second signal input to the second input end of the logic circuit, and the output signal of the logic circuit are square waves.

3 is a schematic diagram of a logic circuit in accordance with an embodiment of the present invention. As shown in FIG. 3, the logic circuit 5 shown in FIG. 1 may include an OR gate as shown in FIG. In Fig. 3, the first signal is a square wave having a frequency of 100 kHz (period of 10 μs) and an amplitude of 1.8 V generated by the clock generator 2 shown in Fig. 1. The second signal is a square wave obtained by inputting the first signal to the circuit under test 3 as shown in FIG. 1 and having a delay time (Td). According to the characteristics of the OR gate, when the first signal and the second signal as shown in FIG. 3 are input, an output signal as shown in FIG. 3 can be obtained. If the first signal generated by the clock generator 2 is a square wave having a duty cycle of 50%, the average voltage of the first signal (ie, the reference voltage) is 900 mV.

The voltmeter 6 shown in FIG. 1 can be used to measure the average voltage of the first signal to obtain a reference voltage and measure the average voltage of the output signal to obtain a first voltage, and obtain an output according to the difference between the reference voltage and the first voltage. The duty cycle of the signal, which in turn determines the relative response of the second signal The delay time of the first signal.

Table 1 lists three embodiments to illustrate the relationship between the difference between the average voltage (first voltage) of the OR gate output signal of FIG. 3 and the reference voltage and the duty cycle and delay time.

According to the second column of Table 1, the average voltage value of the output signal measured at the output of the logic circuit is 900mV, and the difference from the reference voltage is 0V. Therefore, the duty cycle of the output signal is 50%, and thus the second signal is not delayed relative to the first signal. .

According to the third column of Table 1, the average voltage value of the output signal measured at the output of the logic circuit is 936 mV, and the difference from the reference voltage is 36 mV. Therefore, the duty cycle of the output signal is 52%. According to the duty cycle of the output signal is 52%, the delay time of the second signal relative to the first signal is 200 ns.

Similarly, according to the average voltage value of the output signal measured at the output of the logic circuit in the fourth column of Table 1, the delay time of the second signal relative to the first signal is 500 ns.

4 is a schematic diagram of a logic circuit in accordance with an embodiment of the present invention. As shown in FIG. 4, the logic circuit 5 shown in FIG. 1 may include an AND gate as shown in FIG. In Fig. 4, the first signal is a square wave having a frequency of 100 kHz (period of 10 μs) and an amplitude of 1.8 V generated by the clock generator 2 shown in Fig. 1. The second signal is a square wave obtained by inputting the first signal to the circuit under test 3 as shown in FIG. 1 and having a delay time (Td). According to the characteristics of the gate, when the first signal and the second signal as shown in FIG. 4 are input, as shown in FIG. 4, The output signal. If the first signal generated by the clock generator 2 is a square wave having a duty cycle of 50%, the average voltage of the first signal (ie, the reference voltage) is 900 mV.

The voltmeter 6 shown in FIG. 1 can be used to measure the average voltage of the first signal to obtain a reference voltage and measure the average voltage of the output signal to obtain a first voltage, and obtain an output according to the difference between the reference voltage and the first voltage. The duty cycle of the signal, in turn, determines the delay time of the second signal relative to the first signal.

Table 2 lists three embodiments to illustrate the relationship between the difference between the average voltage (first voltage) of the gate output signal of FIG. 4 and the reference voltage and the duty cycle and delay time.

According to the second column of Table 2, the average voltage value of the output signal measured at the output of the logic circuit is 900 mV, and the difference from the reference voltage is 0V. Therefore, the duty cycle of the output signal is 50%, and it is known that the second signal has no delay with respect to the first signal.

According to column 3 of Table 2, the average voltage of the output signal measured at the output of the logic circuit is 864 mV, which is 36 mV from the reference voltage. Therefore, the duty cycle of the output signal is 48%. According to the duty cycle of the output signal is 48%, the delay time of the second signal relative to the first signal is 200 ns.

Similarly, according to the average voltage value of the output signal measured at the output of the logic circuit in the fourth column of Table 2, the delay time of the second signal relative to the first signal is 500 ns.

Figure 5 is a schematic illustration of a logic circuit in accordance with an embodiment of the present invention. As shown in Figure 5 It can be noted that the logic circuit 5 shown in FIG. 1 can include the XOR gate shown in FIG. 5. In Fig. 5, the first signal is generated by the clock generator 2 shown in Fig. 1 with a square wave having a frequency of 100 kHz (period of 10 μs) and an amplitude of 1.8 V. The second signal is a square wave obtained by inputting the first signal to the circuit under test 3 as shown in FIG. 1 and having a delay time (Td). According to the characteristics of the mutual exclusion or the gate, when the first signal and the second signal as shown in FIG. 5 are input, an output signal as shown in FIG. 5 can be obtained. If the first signal generated by the clock generator 2 is a square wave having a duty cycle of 50%, the average voltage of the first signal (ie, the reference voltage) is 900 mV.

The voltmeter 6 shown in FIG. 1 can be used to measure the average voltage of the first signal to obtain a reference voltage and measure the average voltage of the output signal to obtain a first voltage, and obtain an output according to the difference between the reference voltage and the first voltage. The duty cycle of the signal, in turn, determines the delay time of the second signal relative to the first signal.

Table 3 lists three embodiments to illustrate the relationship between the average voltage (first voltage) of the mutex or gate output signal of Figure 5 and the reference voltage as a function of duty cycle and delay time.

According to the second column of Table 3, the average voltage value of the output signal measured at the output of the logic circuit is 0 mV, and the difference from the reference voltage is 900 mV. Therefore, the duty cycle of the output signal is 0%, and thus the second signal is not delayed relative to the first signal.

According to the third column of Table 3, the average of the output signals measured at the output of the logic circuit The voltage value is 72mV, which is 828mV from the reference voltage. Therefore, the duty cycle of the output signal is 4%. According to the duty cycle of the output signal is 4%, the delay time of the second signal relative to the first signal is 200 ns.

Similarly, according to the average voltage value of the output signal measured at the output of the logic circuit in the fourth column of Table 2, the delay time of the second signal relative to the first signal is 500 ns.

According to the embodiment of FIG. 3-5, the relationship between the delay time of the second signal and the average voltage of the output signal and the reference voltage difference is different due to the difference in the composition of the logic circuit. Those skilled in the art to which the present invention pertains should be aware that other circuits suitable for detecting the phase difference of the input signal may be used as the logic circuit of the present disclosure, except for the implementation of FIGS. 3-5. Therefore, the embodiments of the present invention are not limited to the scope of the disclosure.

According to the disclosure, the logic circuit and the voltmeter can be used to estimate the delay time of the circuit to be tested by measuring the average voltage of the output signal of the logic circuit. If you only need to measure the delay time of the circuit under test, you do not need to use an expensive oscilloscope. The cost of an oscilloscope and a voltmeter differs several times to tens of times. Therefore, the measurement method of the present disclosure can greatly reduce the test cost.

In addition, as disclosed in the present disclosure, the average voltage of the output signal of the measurement logic circuit can be used to derive the delay time of the circuit to be tested. Conversely, if a delay time is given, the average voltage value of the output signal of the logic circuit can be reversed. Therefore, the user only needs to measure the average voltage of the output signal of the logic circuit to know whether the circuit to be tested meets the specified delay time, and does not need to sample and display the output signal of the circuit to be tested on the oscilloscope. Calculate its delay time. In this way, in addition to reducing the cost of testing, it can also improve work efficiency.

Furthermore, when a general oscilloscope measures a high-frequency signal, its sampling rate cannot accurately sample the input signal, so the sampled waveform may be distorted. Therefore, you must use an oscilloscope with a higher sampling rate or down-convert the input signal before sampling. Of course However, using an oscilloscope with a high sampling rate will greatly increase the test cost, and the input signal will be down-converted and then sampled, or the measurement results will have errors due to deviations in frequency, voltage level, phase, etc. generated during the down-conversion process. value. Since the present disclosure only needs to use a voltmeter to measure the average voltage of the output signal, it does not need to sample the output signal. Therefore, the frequency of the circuit to be tested has no influence on the measurement method of the present disclosure. That is, the present disclosure can more accurately measure the high frequency circuit under test.

While the invention has been described with respect to the embodiments of the present invention, it will be apparent to those skilled in the art of the invention. Therefore, the scope of the invention is not limited to the disclosed embodiments, and other changes and modifications may be made without departing from the scope of the invention.

S1‧‧‧ measures the average voltage of the first signal to obtain the reference voltage

S2‧‧‧ input the first signal to the circuit to be tested to obtain the second signal

S3‧‧‧ input the first signal and the second signal to the logic circuit to obtain the output signal

S4‧‧‧Measure the average voltage of the output signal to obtain the first voltage

S5‧‧‧Actain the duty cycle of the output signal based on the difference between the reference voltage and the first voltage

S6‧‧‧ according to the duty cycle, to determine the delay time of the second signal relative to the first signal

Claims (20)

A method for measuring a signal delay time, comprising: inputting a first signal and a second signal to a logic circuit to obtain an output signal; measuring an average voltage of the output signal to obtain a first voltage; And determining a delay time of the second signal relative to the first signal according to a difference between the first voltage and a reference voltage. The method of claim 1, wherein the reference voltage is an average voltage of the first signal. The method of claim 1 or 2, wherein the logic circuit is operative to determine a duty cycle of the output signal based on a phase difference between the first signal and the second signal. The method of claim 3, further comprising determining a delay time of the second signal relative to the first signal based on the duty cycle of the output signal. The method of claim 1 or 2, wherein the logic circuit is operative to determine a logic value of the output signal based on a logical value relationship between the first signal and the second signal. The method of claim 5, wherein the logic circuit can be an AND gate, a NAND gate, an OR gate, a NOR gate, a mutual exclusion or a gate (XOR gate). ), one of the flip flops, or a combination thereof. The method of claim 1 or 2, wherein the first signal and the second signal are square waves. The method of claim 1 or 2, wherein the first voltage is measured by a voltmeter that measures the average voltage. The method of claim 8, wherein the voltmeter is a three-meter power meter. The method of claim 8, wherein the voltmeter can measure less than 10 millivolts of electricity Pressure. A device for measuring a signal delay time includes: a circuit to be tested, the circuit to be tested includes an input end and an output end, wherein the signal of the output end has a delay time relative to the signal of the input end; a generator, the clock generator includes an output connected to an input end of the circuit to be tested; a logic circuit including a first input terminal, a second input terminal, and an output terminal, the first input terminal An output terminal of the clock generator is connected, the second input terminal is connected to an output end of the circuit to be tested, and a voltage measuring device is connected to the output end of the logic circuit. The device of claim 11, wherein the logic circuit receives a first signal and a second signal to obtain an output signal. The device of claim 12, wherein the voltage measuring device measures an average voltage of the output signal to obtain a first voltage, and determines the second signal relative to the first voltage according to a difference between the first voltage and the reference voltage The delay time of the first signal. The device of claim 13, wherein the reference voltage is an average voltage of the first signal. The apparatus of claim 11, further comprising a power supply coupled to the clock generator, the circuit to be tested, and the logic circuit. The device of claim 11, wherein the logic circuit can be an AND gate, a NAND gate, an OR gate, a NOR gate, a mutual exclusion or a gate (XOR gate). ), one of the flip flops, or a combination thereof. The apparatus of claim 12, wherein the logic circuit is operative to determine a duty cycle of the output signal based on a phase difference between the first signal and the second signal. The device of claim 17, further comprising the work week based on the output signal And determining a delay time of the second signal relative to the first signal. The apparatus of claim 12, wherein the logic circuit is operative to determine a logic value of the output signal based on a logical value relationship between the first signal and the second signal. The device of claim 11, wherein the voltage measuring device is a voltmeter or a three-meter.