TWI567844B - Layout structure of electronic element and testing method of the same thereof - Google Patents

Description

Layout structure of electronic components and test methods thereof

The present invention relates to a layout structure of an electronic component and a method of testing the electronic component, and more particularly to a layout structure of an electronic component having an array of electronic components, and a method of testing the electronic component array.

In the semiconductor process, in order to evaluate the performance of the component after passing the process, the wafer is subjected to Wafer Acceptance Test (WAT) to confirm the stability of the semiconductor process.

The accuracy of the wafer acceptance test will directly affect the choice of the semiconductor component order for the Golden Die. For example, if there is an error in the wafer acceptance test process, the selection result of the gold crystal side will be inaccurate with the expected specification standard, which will affect the stability of the product. Therefore, accurate wafer acceptance test results are needed to maintain wafer quality and stability to meet market demands.

The present invention relates to a layout structure of an electronic component and a test method of the electronic component. The two ends of the electronic component array to be tested are coupled with a load, and the load includes two coupled test pads. By calculating the resistance of the load and pushing back the current of the electronic component array, the accuracy of the wafer acceptance test can be improved.

According to a first aspect of the present invention, a layout structure of an electronic component is provided, including an array of electronic components, a first load, and a second load. The first load is coupled to the first end of the electronic component array, and the first test pad and the second test pad are coupled to the first test pad. The second load is coupled to the second end of the electronic component array, and the second load includes a third test pad and a fourth test pad coupled to the third test pad.

According to a second aspect of the present invention, a method of testing an electronic component is provided, the method comprising the following steps. An electronic component layout structure is provided, including an electronic component array, a first load coupled to the first end of the electronic component array, and a second load coupled to the second end of the electronic component array. The first load includes a first test pad and a second test pad coupled to the first test pad, and the second load includes a third test pad and a fourth test pad coupled to the third test pad. The first probe is disposed on the first load, and the second probe is disposed on the second load. Calculating a first resistance, and calculating a second resistance, the first resistance is a resistance of the first load and a contact resistance between the first probe and the first load, the second resistance is a resistance of the second load, and the second probe and the second Contact resistance of the load. A pressure difference is applied between the first load and the second load. The measurement measures the current through one of the arrays of electronic components. The current corrected by one of the electronic component arrays is calculated based on the measured current, the differential pressure, the first resistance, and the second resistance.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

FIG. 1 is a circuit diagram of a layout structure 10 of an electronic component in accordance with an embodiment of the present invention. Electronic component layout structure 10 includes electronic components The array 100, the first load 102, the second load 104, the third load 106, and the fourth load 108. The first load 102 is coupled to the first end of the electronic component array 100, the second load 104 is coupled to the second end of the electronic component array 100, and the third load 106 is coupled to the third end of the electronic component array 100. The fourth load 108 is coupled to the fourth end of the electronic component array 100.

Referring to FIG. 1, the electronic component array 100 includes, for example, a plurality of transistors. In one embodiment, the electronic component array 100 can be a metal oxide semi-transistor array, including a plurality of metal-oxide-semiconductor field-MOSFET (MOSFET) 1002. The electronic component array 100 of FIG. 1 is exemplified by a gold oxide semi-transistor array, and is not limited thereto. In other embodiments, the electronic component array 100 may be another transistor array.

As shown in FIG. 1, the source S of the MOS transistor 1002 is connected to each other to form a common source connected to the first end of the electronic device array 100. The drains D of the MOS transistor 1002 are connected to each other to form a common drain which is connected to the second end of the electronic component array 100. The gates G of the MOS transistors 1002 are connected to each other to form a common gate which is connected to the third terminal of the electronic component array 100. The bases of the MOS transistors 1002 are connected to each other to form a common body, which is connected to the fourth end of the electronic component array 100.

FIG. 2 is a schematic view showing an embodiment of a layout structure of an electronic component as shown in FIG. 1. The layout structure 10 of the electronic component in FIG. 2 and the layout structure 10 of the electronic component in FIG. 1 are denoted by the same reference numerals and will not be described again.

As shown in FIG. 2, the first load 102 is coupled to the first end 100a of the electronic component array 100, and the first load 102 includes a first test pad 1020 and a second test pad 1022, and the second test pad 1022 is coupled. Connected to the first test pad 1020. The second load 104 is coupled to the second end 100b of the electronic component array 100. The second load 104 includes a third test pad 1040 and a fourth test pad 1042. The fourth test pad 1042 is coupled to the third test pad 1040. 106 and 108 are also test pads, which should be slightly explained and explained that they are also connected by an interconnect.

In one embodiment, the first test pad 1020 is coupled to the second test pad 1022 by a first interconnecting line L1, and the third test pad 1040 is coupled to the fourth test pad by the second interconnecting line L2. 1042 is coupled. Moreover, the first test pad 1020 is coupled to the electronic component array 100 by the third interconnecting line L3, and the third test pad 1040 is coupled to the electronic component array 100 by the fourth interconnecting line L4. The third load 106 is coupled to the third end 100c (common gate) of the electronic component array 100 by the fifth interconnect L5. The fourth load 108 is coupled to the fourth end 100d (common base) of the electronic component array 100 by the sixth interconnect L6. The first interconnecting line L1, the second interconnecting line L2, the third interconnecting line L3, the fourth interconnecting line L4, the fifth interconnecting line L5, and the sixth interconnecting line L6 may include a plurality of metal wires arranged in parallel And such metal wires are metal wires having a low resistance value.

The test method of the layout structure 10 of the electronic component will be described below with reference to the embodiments. Please refer to FIG. 3, which is a schematic diagram showing a test method for the layout structure of an electronic component according to an embodiment of the invention. The same components as those in the first and second figures in Fig. 3 are denoted by the same reference numerals and will not be described again.

Please also refer to pictures 2~3, the first load 102 is used with the first A probe (not shown) is in contact and the second load 104 is used to contact a second probe (not shown). The resistor Rp1 represents the resistance of the first test pad 1020 and the contact resistance of the first probe to the first test pad 1020. The resistor Rp2 represents the resistance of the second test pad 1022 and the contact resistance of the first probe and the second test pad 1022. The resistor Rp3 represents the resistance of the third test pad 1040 and the contact resistance of the second probe to the third test pad 1040. The resistor Rp4 represents the resistance of the fourth test pad 1042 and the contact resistance of the second probe and the fourth test pad 1042.

The resistor Rm1 represents the resistance of the first interconnect L1, the resistor Rm2 represents the resistance of the second interconnect L2, the resistor Rm3 represents the resistance of the third interconnect L3, and the resistor Rm4 represents the fourth interconnect L4. Resistance. The resistance values of the resistor Rm1, the resistor Rm2, the resistor Rm3, and the resistor Rm4 can be estimated according to the specification of the Electronic Design Rule (EDR).

In one embodiment, the resistance of the first load 102 and the contact resistance of the first probe to the first load 102 can be calculated as the resistance of the first resistor Rt1. In other words, the resistance of the first resistor Rt1 is the resistance of the contact resistance of the first probe and the first test pad 1020, the resistance of the contact resistance of the first probe and the second test pad 1022, and the first test pad. The resistance of 1020, the resistance of the second test pad 1022, and the resistance of the resistance Rm1 of the first interconnect L1.

Similarly, the resistance of the second load 104 and the contact resistance of the second probe and the second load 104 can be calculated as the resistance of the second resistor Rt2. In other words, the resistance of the second resistor Rt2 can be the resistance of the contact resistance of the second probe and the third test pad 1040, the second probe and the fourth test. The resistance of the contact resistance of the pad 1042, the resistance of the third test pad 1040, the resistance of the fourth test pad 1042, and the resistance of the resistance Rm2 of the second interconnect L2 are summed.

FIG. 4 is a schematic diagram showing a test method of a layout structure of an electronic component according to an embodiment of the invention. As shown in Fig. 4, a test press can be utilized to apply a pressure differential between the first load 102' and the second load 104'. Specifically, the first external voltage Vs can be applied to the first load 102'. Also, a second external voltage Vd can be applied to the second load 104'. That is, the voltage difference is the potential difference between the first external voltage applied to the first load 102' and the second external voltage applied to the second load 104'. The first load 102' in FIG. 4 includes the first load 102 and the third interconnect line L3 of FIG. 2, and the second load 104' includes the second load 104 and the fourth interconnect line L4 of FIG. . Therefore, the resistance of the resistor Rs is the resistance of the first resistor Rt1 and the resistor Rm3, and the resistance of the resistor Rd is the sum of the resistances of the second resistor Rt2 and the resistor Rm4.

In this embodiment, the electronic component array 100 is a gold oxide semi-transistor array. According to the characteristic curve of the gate current Id of the MOS transistor and the source voltage Vs, the drain current Id: Id=pVs'+n (1) can be obtained.

According to the characteristic curve of the drain current Id and the drain voltage Vd of the gold-oxide semi-transistor, the drain current Id: Id=qVd'+m (2) can be obtained.

Wherein p, n, q and m are constants.

By adding equation (1) to equation (2), the current It flowing through the array of electronic components 100 can be obtained: It=α Vs'+β+γ Vd’ (3)

Among them, α, β and γ are constants.

Referring to FIG. 4, according to Ohm's law, the first current 100a of the electronic component array 100 can be calculated according to the current It, the first external voltage Vs and the first resistor Rs flowing through the electronic component array 100. The load 102' is coupled to the terminal voltage Vs' of the first end 100a of the electronic component array 100: Vs' = ItxRs + Vs (4)

Where It is the current flowing through the electronic component array 100, for example, the sum of I1+I2+I3+I4+I5+I6 in Fig. 4.

The second load 104 ′ is coupled to the electronic component array 100 at the second end 100 b of the electronic component array 100 according to the current It, the second external voltage Vd and the second resistor Rd flowing through the electronic component array 100 . The terminal voltage Vd' of the second terminal 100b: Vd'=Vd-ItxRd (5), in the equations (4) and (5), the first terminal voltage Vs' and the second terminal voltage Vd' are substituted into the equation (3) A current correction equation can be established, the current correction equation being used to calculate the corrected current through the array of electronic components 100:

The current flowing through the electronic component array 100 is expressed as x times the first external voltage Vs, z times the second external voltage Vd and a parameter. Sum.

Three sets of first external voltage and second external voltage are respectively applied to the first load and the second load. In other words, the voltage values of the three sets of the first external voltage Vs and the second external voltage Vd are substituted into the equation (6), and the current It, the first external voltage Vs, and the second external voltage flowing through the electronic component array 100 are measured according to the measurement. Vd, the first resistor Rs and the second resistor Rd, the values of x, y and z can be obtained, and the obtained x, y and z are substituted into the current correction equation (6), that is, the corrected flow can be pushed back. The current Ic of the electronic component array 100 is used to calculate the current Ic corrected by one of the electronic component arrays 100.

The voltage values of the three sets of the first external voltage Vs and the second external voltage Vd may be applied in different times. For example, in the first applying step, the first level voltage (for example, Vdd) may be used as the first external voltage Vs, and the 0 volt (V) level voltage may be used as the second external voltage Vd. In the second applying step, the sum of the first level (for example, Vdd) and a bias value (for example, 0.05V) may be applied as the first external voltage Vs, and the 0 V level voltage is used as the second external portion. Voltage Vd. In the third application step, a first level (eg, Vdd) may be applied as the first external voltage Vs, and a second level voltage (eg, Vss) may be subtracted from the bias value (eg, 0.05). Poor as the second external voltage Vd.

By applying three sets of external voltages of different values, the value of the corrected current Ic can be pushed back. Since the corrected current Ic is excluded from the influence of the contact resistance of the test pad and the probe and the voltage drop caused by the resistance of the test pad, the corrected current Ic is measured. The current It is more accurate.

Figure 5 is a graph showing a comparison of statistical results according to an embodiment of the present invention and a comparative example. The statistical result of S1 represents the standard deviation of the original data, and the statistical result of S2 is expressed according to the present invention. The standard deviation calculated from the data obtained by the above method.

As shown in Figure 5, the statistical result S1 is the standard deviation calculated from the conventional wafer acceptance test data, including the in-wafer die to die. Global variation, as well as local variation of individual intra-die. In contrast, the statistical result S2 is a standard deviation calculated from the wafer acceptance test data of the above method of the present invention, and the standard deviation can eliminate the error variation of individual crystal grains, and only the error between the crystal grains and the crystal grains in the wafer is retained. .

Compared with the statistical result S2, the statistical result S1 has similar average behaviors. The statistical result S1 data is relatively discrete and has large errors, which is not conducive to the choice of Golden Die. In other words, when a transistor having a current of 510 microamperes (μA) through a transistor is selected as a gold crystal, an electronic component (for example, a metal oxide semi-transistor) which is tested by the method of the above embodiment of the present invention is used. The array has a smaller error margin than 510 μA. Therefore, the stability of the process can be ensured.

In summary, the layout structure of the electronic component of the above embodiment of the present invention and the electronic component testing method having the layout structure of the electronic component are coupled to the load to the two ends of the electronic component array to be tested, and the load includes two A test pad coupled to it. By calculating the resistance of the load, the more accurate current flowing through the array of electronic components can be pushed back, thereby improving the accuracy of the wafer acceptance test and contributing to the choice of the gold crystal.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. Those having ordinary skill in the art to which the present invention pertains can be made in various ways without departing from the spirit and scope of the invention. Change and retouch. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧Layout structure of electronic components

100‧‧‧Electronic component array

102, 102', 104, 104', 106, 108‧‧‧ loads

1002‧‧‧Gold oxygen semi-transistor

100a, 100b, 100c, 100d‧‧‧

1020, 1022, 1040, 1042‧‧‧ test pads

It‧‧‧ Current

L1, L2, L3, L4, L5, L6‧‧‧ interconnection

Rp1, Rp2, Rp3, Rp4, Rm1, Rm2, Rm3, Rm4, Rs, Rd‧‧ resistance

S1, S2‧‧‧ statistical results

Vs, Vs', Vd, Vd'‧‧‧ voltage

S‧‧‧ source

D‧‧‧汲

G‧‧‧ gate

FIG. 1 is a circuit diagram showing a layout structure of an electronic component according to an embodiment of the present invention.

FIG. 2 is a schematic view showing an embodiment of a layout structure of an electronic component as shown in FIG. 1.

FIG. 3 is a schematic diagram showing a test method of a layout structure of an electronic component according to an embodiment of the invention.

FIG. 4 is a schematic diagram showing a test method of a layout structure of an electronic component according to an embodiment of the invention.

Figure 5 is a graph showing a comparison of statistical results according to an embodiment of the present invention and a comparative example.

10‧‧‧Layout structure of electronic components

100‧‧‧Electronic component array

102, 104, 106, 108‧‧‧ load

1002‧‧‧Gold oxygen semi-transistor

S‧‧‧ source

D‧‧‧汲

G‧‧‧ gate

Claims (18)

An electronic component layout structure includes: an electronic component array; a first load coupled to the first end of the electronic component array, the first load including a first test pad and a second test pad coupled Up to the first test pad, the first test pad is coupled to the second test pad by a first interconnect; and a second load is coupled to the second end of the electronic component array. The second load includes a third test pad and a fourth test pad coupled to the third test pad. The third test pad is coupled to the fourth test pad by a second interconnect. The layout structure of the electronic component of claim 1, wherein the electronic component array comprises a plurality of transistors. The layout structure of the electronic component of claim 1, wherein the electronic component array is a gold oxide semi-transistor array. The layout structure of the electronic component of claim 3, wherein the first end is a source of the transistors, the second end is a drain of the transistors, and the electro-crystalline systems are A common source, a common buck, and a common gate arrangement. The layout structure of the electronic component of claim 1, wherein the first test pad is coupled to the electronic component array by a third interconnecting wire, and the third test pad is coupled by a first The four inner wires are coupled to the electronic component array. The layout structure of the electronic component of claim 5, wherein the first interconnecting line, the second interconnecting line, the third interconnecting line, and The fourth interconnect is a metal wire. The layout structure of the electronic component of claim 5, wherein the first interconnecting line, the second interconnecting line, the third interconnecting line, and the fourth interconnecting line respectively comprise a plurality of metals The wires are arranged in parallel. The layout structure of the electronic component of claim 1, wherein the first load is used to contact a first probe, the resistance of the first load, and the first probe and the first load The resistance of the contact resistance is the resistance of a first resistor. The layout structure of the electronic component of claim 8, wherein the resistance of the first resistor is a contact resistance between the first probe and the first test pad, the first probe and the second test The contact resistance of the pad, the resistance of the resistance of the first test pad, the resistance of the resistance of the second test pad, and the resistance of the first interconnect. The layout structure of the electronic component of claim 1, wherein the second load is used to contact a second probe, the resistance of the second load, and the second probe and the second load The resistance of the contact resistance is the resistance of a second resistor. The layout structure of the electronic component of claim 10, wherein the resistance of the second resistor is a resistance of a contact resistance of the second probe and the third test pad, and the second probe is The resistance of the contact resistance of the fourth test pad, the resistance of the third test pad, the resistance of the fourth test pad, and the resistance of the second interconnect. A method for testing an electronic component, comprising: providing an electronic component layout structure, including an electronic component array, a first load coupled to the first end of the electronic component array, and a second The load is coupled to the second end of the electronic component array, the first load includes a first test pad and a second test pad coupled to the first test pad, and the second load includes a third test pad and a fourth test pad is coupled to the third test pad; a first probe is disposed on the first load, and a second probe is disposed on the second load; calculating a resistance of the first resistor and a resistance of the second resistor, wherein the first resistor has a resistance about the first load and a contact resistance between the first probe and the first load, and the second resistor has a resistance about the second load and Contact resistance of the second probe and the second load; applying a voltage difference between the first load and the second load; measuring current through one of the array of electronic components; and measuring current according to the current The voltage difference, the first resistance, and the second resistance calculate a current corrected by one of the electronic component arrays. The method of testing an electronic component according to claim 12, wherein the differential pressure is applied to a potential difference between a first external voltage of the first load and a second external voltage applied to the second load. And calculating the corrected current through the array of electronic components, comprising: obtaining a first end at the first end of the array of electronic components according to the measured current, the first external voltage, and the first resistance a second terminal voltage is obtained at the second end of the electronic component array according to the measured current, the second external voltage, and the second resistor; and according to the first terminal voltage and the second terminal voltage, The corrected current through the array of electronic components is calculated. Testing of electronic components as described in claim 12 The method of providing a layout structure of the electronic component includes: providing a first interconnecting wire to couple the first test pad and the second test pad, and providing a second interconnecting wire to couple the third test pad With the fourth test pad. The method for testing an electronic component according to claim 12, wherein the calculating the resistance of the first resistor comprises: calculating a contact resistance of the first probe with the first test pad, the first probe a sum of a contact resistance of the second test pad, a resistance of the first test pad, a resistance of the second test pad, and a resistance of the first interconnect; a resistance of the first resistor; And calculating a resistance value of the second resistor, comprising: calculating a contact resistance between the second probe and the third test pad, a contact resistance between the second probe and the fourth test pad, and a third test pad The resistance, the resistance of the fourth test pad, and the resistance of the resistance of the second interconnect are used as the resistance of the second resistor. The method of testing an electronic component according to claim 12, wherein the differential pressure is applied to a potential difference between a first external voltage of the first load and a second external voltage applied to the second load. And calculating the corrected current through the array of electronic components includes: establishing a current correction equation according to Ohm's law and a transistor characteristic curve, wherein the current flowing through the array of electronic components is expressed as x times a first external voltage, z times the sum of the second external voltage and a parameter y; determining a value of x, y, and z according to the measured current, the first external voltage, and the second external voltage; The obtained x, y and z are substituted into the current correction equation to push back The corrected current flowing through the array of electronic components. The method for testing an electronic component according to claim 16, wherein the transistor characteristic curve includes a curve of a source voltage corresponding to a drain current, and a curve of a drain voltage corresponding to a drain current. The method of testing an electronic component according to claim 12, wherein the differential pressure is applied to a potential difference between a first external voltage of the first load and a second external voltage applied to the second load. And applying the differential pressure includes: applying a first level voltage as the first external voltage, and a 0V level voltage as the second external voltage in a first applying step; and in a second applying step, Applying the sum of the first level and a bias value to the first external voltage, the 0V level voltage as the second external voltage; and in a third applying step, applying the first level to the first The external voltage is applied by a second level voltage and the difference between the bias values is the second external voltage.