TWI567826B - Fabricating method of semiconductor elements - Google Patents

Description

Semiconductor component manufacturing method

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of fabricating a semiconductor device in an integrated circuit process.

In an integrated circuit, a MOS transistor is a commonly used circuit component. After the semiconductor industry enters the sub-micron process, the high-k gate dielectric/metal gate (HK/MG) has become an important technical means in gold oxide semi-transistors. The manufacturing time of the high-k gate dielectric and the metal gate is usually started after the silicide of the source/drain structure surface is completed, but The silicide of the self-aligned Silicidation (SALICIDE) is usually not resistant to high temperatures, so it is likely to produce a metal due to the high temperature of the high dielectric constant dielectric layer. Destruction of the silicide. To this end, the through-hole contact self-alignment metal contact process (Through contact SALICIDE) was developed.

In simple terms, the contact hole self-aligning metal tempering process is to move the time point to the contact hole above the source/drain structure, and then self-align the metal to the exposed source/drain structure surface in the contact hole. Deuteration process. However, as the size of the component is shrinking, the aperture of the contact hole is also reduced, so that the subsequent metal deuteration process is unfavorable, and the component performance cannot be improved. How to improve such a deficiency is the main purpose of the development of this case.

It is an object of the present invention to provide a method of fabricating a semiconductor device that is in contact The metal deuteration process can still be successfully completed with a shrinking aperture.

To achieve the above object, a semiconductor device manufacturing method is provided, comprising the steps of: providing a substrate having a metal gate structure and a source/drain structure formed thereon; and amorphizing the source/drain structure to form a non- a crystallization portion; an inner dielectric layer is formed over the surface of the source/drain structure, and a contact hole is formed in the inner dielectric layer; and the amorphization portion of the source/drain structure is formed by the contact hole A metal deuteration process is performed to form a metal telluride layer.

In another embodiment of the invention, the substrate is a germanium substrate, and the metal gate structure includes a metal gate and a high-k dielectric layer.

In another embodiment of the present invention, the source/drain structure is an embedded source drain structure completed in an epitaxial manner, and the material is one of germanium, germanium germanium or tantalum carbide.

In another embodiment of the present invention, the amorphization process performed by the source/drain structure is a pre-amorphization implantation process, which utilizes particle implantation to destroy the crystal of the source/drain structure.

In another embodiment of the invention, the particles used in the pre-amorphization implantation process are germanium or arsenic.

In another embodiment of the invention, the particle implantation in the pre-amorphization implantation process has an oblique angle.

In another embodiment of the present invention, the inner dielectric layer and the contact hole are formed after the amorphization process is completed.

In another embodiment of the present invention, the inner dielectric layer and the contact hole are formed first, followed by an amorphization process.

In another embodiment of the invention, the amorphization process is performed before the completion of the inner dielectric layer and after the formation of the contact hole.

In another embodiment of the present invention, the metal deuteration process includes the steps of: forming a metal layer; and performing a thermal process to make the metal layer and the amorphization Part of the reaction further forms the metal halide layer.

In another embodiment of the invention, the metal layer is nickel (Ni), cobalt (Co) or titanium (Ti), and the metal telluride layer is nickel (NiSi), cobalt (CoSi) or titanium telluride (TiSi). ).

In another embodiment of the invention, the thermal process is a rapid thermal process or a laser spike anneal. In another embodiment of the invention, the semiconductor device manufacturing method further includes the step of stripping a metal that does not form a metal telluride layer.

In another embodiment of the present invention, the method of forming the metal layer may be physical vapor deposition, chemical vapor deposition, or electroless metal deposition.

In the method for fabricating a semiconductor device of the present embodiment, by using amorphization implantation and metal layer deposition and heat treatment, a self-aligned metal telluride layer can be formed on the source/drain, even in the case where the contact hole diameter becomes small, The production of the metal telluride layer can be completed smoothly.

1A to FIG. 1G, which is a semiconductor device manufacturing method developed by the present invention. First, as shown in FIG. 1A, a substrate 1 is formed. A metal gate structure 10 is formed on the substrate 1. The source/drain structure 11 and the inner layer dielectric (ILD) 12. The substrate may be a germanium substrate, and the metal gate structure 10 includes a plurality of materials such as a metal gate and a high-k gate dielectric, which are not described herein. As for the source/drain structure 11, in the figure, an embedded source drain structure completed by an epitaxy method is taken as an example, and the material thereof may be tantalum, niobium or tantalum, but the case is not limited to this. structure.

Referring again to FIG. 1B, the inner layer dielectric is over the surface of the source/drain structure 11. A schematic view of the contact hole 13 is formed in the layer 12 by an etching process. As the size of the component is increasingly reduced, the aperture of the contact hole 13 is also reduced, which is very unfavorable for the metal deuteration process. Therefore, as shown in FIG. 1C, when the contact hole 13 is completed, the opening/depositing source/drain structure 11 is amorphized by the opening, and the source/drain structure 11 is amorphous. Part 110. The amorphization process may be a pre-Amorphization Implant (PAI), mainly using tetravalent particles (such as ruthenium or osmium), inert particles (such as argon), and N-type particles (such as arsenic). The larger atom is used to destroy the crystal of the source/drain structure 11 to complete the amorphization, but does not affect the electrical properties of the material, and the implantation depth of the pre-amorphization implantation process can be controlled in the metal deuteration. Within the range of formation of the substance, it will be less likely to have side effects. Since the implantation process can generally have an oblique angle, an amorphized portion 110 that is larger than the exposed area of the source/drain structure 11 can be caused. That is, the amorphized portion 110 is partially covered by the inner dielectric layer 12, but this may facilitate lateral growth of the metal telluride.

Next, a metal deuteration process is performed using the contact hole 13 and the amorphization portion 110 to form a metal telluride layer 112 as shown in FIG. 1F, such as common nickel (NiSi), cobalt (CoSi) or germanium. Titanium (TiSi) and the like. As for the metal deuteration process, the following steps may be included. First, as shown in FIG. 1D, physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD) or electroless metal plating is used. The method of depositing (Electroless Metal Deposition) deposits a metal layer 111 on the surface of the element, particularly the surface of the amorphized portion 110 exposed in the contact hole 13, and the metal layer 111 may be, for example, nickel, cobalt or titanium; As shown in FIG. 1E, a thermal process such as Rapid Thermal Processing (RTP) or Laser-Spike Annealing (LSA) is performed to make the metal layer 111 and the amorphized portion 110 sufficiently The reaction is carried out to complete the metal telluride layer 112 as shown in FIG. 1E. Then, as shown in FIG. 1F, the metal telluride layer 112 is not formed on the surface of other elements. The metal layer 111a is stripped, thereby completing the contact hole self-alignment metal rafting process. Further, in the mode shown in FIGS. 1D-1F, the metal layer 111 is sufficiently reacted with the amorphized portion 110, that is, there is no amorphized portion 110 in the element after completion. However, in another embodiment, as shown in FIG. 1G, the bottom of the amorphization portion 110 may also retain a thin layer that does not react with the metal layer 111, that is, the bottom of the metal telluride layer 112a has an amorphized thin layer 110a. .

In addition, the amorphization process of the source/drain structure 11 can also be performed at other time points. For example, when the inner dielectric layer 12 is not completed, the source/drain can also be partially performed. The structure 11 forms the amorphized portion 110, or the amorphization process is performed before the completion of the inner dielectric layer 12 and after the formation of the contact holes 13, thereby achieving the object of improving the conventional means.

In the semiconductor device manufacturing method of the present embodiment, the self-aligned metal telluride layer 112 can be formed on the source/drain 11 by amorphization implantation and metal layer deposition and heat treatment, even if the hole diameter of the contact hole 13 becomes small. In this case, the production of the metal telluride layer can still be completed smoothly.

In summary, after the technology of the present invention is improved, the problem of the conventional means can be effectively improved. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

1‧‧‧Substrate

10‧‧‧Metal gate structure

11‧‧‧Source/drain structure

12‧‧‧ Inner dielectric layer

13‧‧‧Contact hole

110‧‧‧Amorphized part

110a‧‧‧Amorphous thin layer

111, 111a‧‧‧ metal layer

112, 112a‧‧‧ metal telluride layer

FIG. 1A to FIG. 1G are the semiconductor component manufacturing methods developed in the present invention for improving the conventional means.

1‧‧‧Substrate

10‧‧‧Metal gate structure

11‧‧‧Source/drain structure

12‧‧‧ Inner dielectric layer

13‧‧‧Contact hole

110‧‧‧Amorphized part

111‧‧‧metal layer

Claims (12)

A semiconductor device manufacturing method comprising the steps of: providing a substrate having a metal gate structure and a source/drain structure formed thereon; and performing an amorphization pre-implantation process on the source/drain structure The particles are implanted to destroy the crystal of the source/drain structure to form an amorphized portion, wherein the seed implantation in the pre-amorphization implantation process has an oblique angle; and the source/drain structure Forming an inner dielectric layer over the surface and forming a contact hole in the inner dielectric layer; and performing a metal deuteration process on the amorphized portion of the source/drain structure by using the contact hole to A metal halide layer is formed. The method of fabricating a semiconductor device according to claim 1, wherein the substrate is a germanium substrate, and the metal gate structure comprises a metal gate and a high-k dielectric layer. The method of manufacturing a semiconductor device according to the first aspect of the invention, wherein the source/drain structure is an embedded source drain structure in an epitaxial manner, and the material is germanium, germanium germanium or tantalum carbide. One. The method of manufacturing a semiconductor device according to claim 1, wherein the particles used in the pre-amorphization implantation process are germanium or arsenic. The method of fabricating a semiconductor device according to claim 1, wherein the inner dielectric layer and the contact hole are formed after the pre-amorphization implantation process is performed. The method of fabricating a semiconductor device according to claim 1, wherein the inner dielectric layer and the contact hole are formed first, and then the pre-amorphization implantation process is performed. The method of fabricating a semiconductor device according to claim 1, wherein the pre-amorphization implantation process is performed before the completion of the inner dielectric layer and after the formation of the contact hole. The method of fabricating a semiconductor device according to claim 1, wherein the metal deuteration process comprises the steps of: forming a metal layer; and performing a thermal process for reacting the metal layer with the amorphized portion, thereby A metal halide layer is formed. The method of manufacturing a semiconductor device according to claim 8, wherein the metal layer is nickel (Ni), cobalt (Co) or titanium (Ti), and the metal telluride layer is nickel neodymium (NiSi) or cobalt telluride. (CoSi) or titanium telluride (TiSi). The method of fabricating a semiconductor device according to claim 8, wherein the thermal process is a rapid thermal process or a laser spike annealing. The method of manufacturing a semiconductor device according to claim 8, further comprising the step of: stripping a metal not forming the metal telluride layer. The method of manufacturing a semiconductor device according to claim 8, wherein the method of forming the metal layer is physical vapor deposition, chemical vapor deposition, or electroless metal deposition.