KR100628219B1 - method for forming silicide of semiconductor device - Google Patents
method for forming silicide of semiconductor device Download PDFInfo
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- KR100628219B1 KR100628219B1 KR1020040112062A KR20040112062A KR100628219B1 KR 100628219 B1 KR100628219 B1 KR 100628219B1 KR 1020040112062 A KR1020040112062 A KR 1020040112062A KR 20040112062 A KR20040112062 A KR 20040112062A KR 100628219 B1 KR100628219 B1 KR 100628219B1
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- silicide
- barrier layer
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- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 35
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 230000004888 barrier function Effects 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- 229910021645 metal ion Inorganic materials 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 230000007704 transition Effects 0.000 claims abstract description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 11
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 230000001934 delay Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- -1 silicon ions Chemical class 0.000 description 2
- VEQPNABPJHWNSG-UHFFFAOYSA-N Nickel(2+) Chemical compound [Ni+2] VEQPNABPJHWNSG-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910001453 nickel ion Inorganic materials 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Abstract
본 발명은 베리어층(barrier layer)을 통과한 금속과 실리콘과의 반응을 이용함으로써 얇은 실리사이드막을 형성하고 실리콘 함유량이 많은 상(phase)으로의 상 전이를 지연시키어 보다 우수한 공정 마진을 확보하도록 한 반도체 소자의 실리사이드 형성방법에 관한 것으로서, 폴리 실리콘층에 베리어층을 형성하는 단계와, 상기 베리어층상에 금속막을 형성하는 단계와, 상기 금속막에 어닐 공정을 실시하여 상기 베리어층을 통해 상기 금속막의 금속 이온을 폴리 실리콘층으로 확산시키어 상기 폴리 실리콘층의 표면에 금속 실리사이드막을 형성하는 단계와, 상기 폴리 실리콘층과 반응하지 않은 금속막 및 금속 이온이 트랩된 베리어층을 제거하는 단계를 포함하여 형성함을 특징으로 한다.The present invention uses a reaction between a metal passed through a barrier layer and silicon to form a thin silicide film, and delays phase transition to a phase containing a large amount of silicon, thereby securing a better process margin. A method of forming a silicide of a device, the method comprising: forming a barrier layer on a polysilicon layer, forming a metal film on the barrier layer, and performing an annealing process on the metal film to form a metal of the metal film through the barrier layer. Diffusing ions into the polysilicon layer to form a metal silicide film on the surface of the polysilicon layer; and removing the metal layer and the barrier layer trapped with the metal ions that do not react with the polysilicon layer. It is characterized by.
실리사이드, 베리어층, 확산Silicide, barrier layer, diffusion
Description
도 1a 내지 도 1b는 종래 기술에 의한 반도체 소자의 실리사이드 형성방법을 나타낸 공정단면도1A through 1B are cross-sectional views illustrating a method of forming silicide of a semiconductor device according to the related art.
도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 실리사이드 형성방법을 나타낸 공정단면도2A to 2C are cross-sectional views illustrating a method of forming silicide of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 설명Description of the main parts of the drawing
31 : 폴리 실리콘층 32 : 베리어층31
33 : 금속막 34 : 금속 실리사이드막33
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 공정 마진(margin)을 확보하도록 한 반도체 소자의 실리사이드 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming silicide of a semiconductor device to ensure a process margin.
일반적으로 반도체 소자의 고집적화에 따라 MOS 트랜지스터의 크기가 작아지고, MOS 트랜지스터의 소오스/드레인 영역의 접합깊이도 점점 얕아지게 되었다. In general, the higher the integration of semiconductor devices, the smaller the size of the MOS transistor and the shallower the junction depth of the source / drain regions of the MOS transistor.
이렇게 소오스/드레인 영역의 접합깊이가 점점 얕아지면, 접합의 면저항은 접합깊이에 반비례하기 때문에 면저항이 증가되므로 소자의 기생저항(parasitic resistance)이 증가하는 문제가 발생한다.As the junction depth of the source / drain regions becomes shallower in this manner, the sheet resistance of the junction is inversely proportional to the junction depth, resulting in an increase in the parasitic resistance of the device.
결국, 반도체 소자의 크기를 줄이기 위해서는 접합의 깊이도 얕아져야 하는 반면, 면저항도 줄여야 하므로 비저항을 줄여야 한다.As a result, in order to reduce the size of the semiconductor device, the depth of the junction must be shallow, while the sheet resistance must be reduced, so the specific resistance must be reduced.
따라서 실리사이드막을 얇은 접합의 소오스/드레인 영역에 형성함으로써 접합의 면저항을 감소시킬 수 있다.Therefore, the sheet resistance of the junction can be reduced by forming the silicide film in the source / drain regions of the thin junction.
상기와 같은 실리사이드막은 크게 고융점 금속과 폴리 실리콘과의 반응에 의해 형성되는 폴리사이드(polycide)와 고융점 금속과 실리콘과의 반응에 의해 형성되는 살리사이드(salicide : self-aligned silicide)로 나뉘어지며, 이러한 실리사이드막으로는 티타늄 실리사이드막(TiSi2)이 널리 알려져 있다.The silicide layer is divided into a polycide formed by the reaction between the high melting point metal and the polysilicon and a salicide (self-aligned silicide) formed by the reaction between the high melting point metal and the silicon. As such a silicide film, a titanium silicide film (TiSi 2 ) is widely known.
한편, 소오스/드레인 영역에 실리사이드막을 형성하게 되면 실리사이드막의 형성 두께에 대응하는 깊이만큼 실리콘으로 된 소오스/드레인 영역부분의 소모를 수반하게 된다. On the other hand, when the silicide film is formed in the source / drain region, the source / drain region portion of silicon is consumed by a depth corresponding to the formation thickness of the silicide film.
그러므로 실리사이드막의 형성두께 즉, 소오스/드레인 영역의 소모된 부분도 접합 깊이에 가산되므로 초고집적 소자를 제조하기 위해서는 두께가 얇으면서도 안정한 실리사이드막의 형성 기술이 요구된다.Therefore, since the formation thickness of the silicide film, that is, the consumed portion of the source / drain regions, is also added to the junction depth, a thin and stable silicide film formation technique is required to manufacture an ultra-high density device.
또한, 전기적인 측면에서도 얇은 접합의 소오스/드레인 영역에 형성되는 실리사이드막은 실리사이드와 실리콘과의 계면이 균일해야 한다.In terms of electrical aspects, the silicide film formed in the source / drain region of the thin junction should have a uniform interface between the silicide and silicon.
이하, 첨부된 도면을 참고하여 종래 기술에 의한 반도체 소자의 실리사이드 형성방법을 설명하면 다음과 같다.Hereinafter, a silicide forming method of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1b는 종래 기술에 의한 반도체 소자의 실리사이드 형성방법을 나타낸 공정단면도이다.1A to 1B are cross-sectional views illustrating a method of forming silicide of a semiconductor device according to the related art.
도 1a에 도시한 바와 같이, 폴리 실리콘(poly Si)층(11)상에 캡 실리콘(cap Si)층(12)을 형성한다.As shown in FIG. 1A, a
이어, 상기 캡 실리콘층(12)상에 니켈(Ni)막(13)을 증착한다.Subsequently, a nickel (Ni)
도 1b에 도시한 바와 같이, 600 ~ 1000℃의 온도에서 어닐 공정을 실시하여 상기 니켈막(13)의 니켈 이온과 상기 캡 실리콘층(12)의 실리콘 이온을 반응시키어 상기 폴리 실리콘층(11)상에 니켈 실리사이드(Ni silicide)막(14)을 형성한다.As shown in FIG. 1B, an annealing process is performed at a temperature of 600 to 1000 ° C. to react the nickel ions of the
그러나 상기와 같은 종래 기술에 의한 반도체 소자의 실리사이드 형성방법은 다음과 같은 문제점이 있었다.However, the silicide formation method of the semiconductor device according to the related art has the following problems.
즉, 실리사이드 공정은 정확한 두께 제어가 어려울 뿐만 아니라 캡 실리콘층으로 금속이온이 확산되어 형성되기 때문에 열 소모비용(thermal budget : 웨이퍼의 온도를 가공 온도까지 상승시키는데 걸리는 시간 + 고온에서 하강 가공된 웨이퍼의 온도를 상온으로 시키는데 걸리는 시간)이 증가한다.That is, the silicide process is not only difficult to control the thickness accurately, but also due to the diffusion of metal ions into the cap silicon layer, the thermal budget (thermal budget: time taken to raise the wafer temperature to the processing temperature + lowering of the wafer processed at a high temperature). Time to bring the temperature to room temperature) increases.
이러한 반응 방식은 소자의 집적화가 가속화됨에 따라 점점 더 커다란 문제점으로 나타나고 있다. 750℃하에서 실리콘 함유량이 많은(Si rich) 상(phase)으로의 상전이를 막기 위하여 많은 저온 어닐 공정기술이 선보이고 있으나 근본적으로 이는 캡 실리콘층의 소비량에 의한 두께 제어에 의존해야 하기 때문에 이를 위한 다른 해결방안이 급한 실정이다.This type of reaction is becoming a bigger problem as the integration of devices is accelerated. Many low temperature annealing process technologies have been introduced to prevent phase transition to Si rich phase at 750 ° C, but this is fundamentally due to the dependence on the thickness control by the consumption of the cap silicon layer. The room is urgent.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위한 것으로, 베리어막(barrier film)을 통과한 금속과 실리콘과의 반응을 이용함으로써 얇은 실리사이드막을 형성하고 실리콘 함유량이 많은 상(phase)으로의 상 전이를 지연시키어 보다 우수한 공정 마진을 확보하도록 한 반도체 소자의 실리사이드 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention is to solve the conventional problems as described above, by forming a thin silicide film by using a reaction of the metal and silicon passed through the barrier film (phase) to a phase with a high silicon content It is an object of the present invention to provide a method for forming a silicide of a semiconductor device to delay the delay and to secure a better process margin.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 실리사이드 형성방법은 폴리 실리콘층에 베리어층을 형성하는 단계와, 상기 베리어층상에 금속막을 형성하는 단계와, 상기 금속막에 어닐 공정을 실시하여 상기 베리어층을 통해 상기 금속막의 금속 이온을 폴리 실리콘층으로 확산시키어 상기 폴리 실리콘층의 표면에 금속 실리사이드막을 형성하는 단계와, 상기 폴리 실리콘층과 반응하지 않은 금속막 및 금속 이온이 트랩된 베리어층을 제거하는 단계를 포함하여 형성함을 특징으로 한다.According to an embodiment of the present invention, a method of forming a silicide of a semiconductor device may include forming a barrier layer on a polysilicon layer, forming a metal layer on the barrier layer, and performing an annealing process on the metal layer. Diffusing the metal ions of the metal film to the polysilicon layer through the barrier layer to form a metal silicide film on the surface of the polysilicon layer, and a barrier in which the metal film and the metal ions that do not react with the polysilicon layer are trapped. And removing the layer.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 제조방법을 보다 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 실리사이드 형성방법을 나타낸 공정단면도이다.2A to 2C are cross-sectional views illustrating a method of forming silicide of a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 폴리 실리콘층(31)상에 질화막과 같은 베리어층(32)을 형성하고, 상기 베리어층(32)상에 금속막(33)을 증착한다.As shown in FIG. 2A, a
여기서, 상기 금속막(33)을 구성하는 물질로 티타늄(Ti), 코발트(Co), 니켈(Ni), 텅스텐(W), 팔라듐(Pd), 지르코늄(Zr), 몰리브덴(Mo) 등의 천이족 금속군에서 선택된 어느 하나를 사용한다.Here, the material of the
도 2b에 도시한 바와 같이, 600 ~ 1000℃의 온도에서 어닐 공정을 실시하여 상기 금속막(33)내에 함유된 금속 이온을 상기 베리어층(32)을 관통하여 상기 폴리 실리콘층(31)으로 확산시키어 상기 폴리 실리콘층(31)의 표면내에 금속 실리사이드막(34)을 형성한다.As shown in FIG. 2B, an annealing process is performed at a temperature of 600 to 1000 ° C. to diffuse metal ions contained in the
이때 상기 베리어층(32)을 통해 상기 금속막(33)의 금속 이온들이 상기 폴리 실리콘층(31)으로 확산되는데, 상기 폴리 실리콘층(31)으로 확산되지 않은 금속 이온들은 베리어층(32)내에 트랩(trapped)된다.At this time, metal ions of the
그리고 상기 폴리 실리콘층(31)까지 확산된 상기 금속막(33)의 금속 이온과 폴리 실리콘층(31)의 실리콘 이온은 반응하여 금속 실리사이드막(34)을 형성하게 된다.In addition, the metal ions of the
도 2c에 도시한 바와 같이, 상기 폴리 실리콘층(31)과 반응하지 않은 금속막(33) 및 베리어층(32)을 제거하여 원하는 두께를 갖는 금속 실리사이드막(34)을 형성한다.As illustrated in FIG. 2C, the
여기서, 상기 폴리 실리콘층(31)과 반응하지 않은 금속막(33) 및 금속 이온이 트랩된 베리어층(32)은 NH4OH/H2O2, HCl/H2O2, 또는 H2SO4/H2O2를 이용하여 제거한다.Here, the
이상 설명한 내용을 통해 당업자라면 본 발명의 기술 사상을 이탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.
따라서, 본 발명의 기술적 범위는 실시예에 기재된 내용으로 한정하는 것이 아니라 특허 청구범위에 의해서 정해져야 한다.Therefore, the technical scope of the present invention should not be limited to the contents described in the examples, but should be defined by the claims.
이상에서 설명한 바와 같은 본 발명에 따른 반도체 소자의 실리사이드 형성방법에 있어서 다음과 같은 효과가 있다.As described above, the silicide forming method of the semiconductor device according to the present invention has the following effects.
즉, 열 소모비용(thermal budget)을 크게 줄이면서 원하는 두께를 갖는 실리사이드막을 형성할 수 있기 때문에 약 90㎚급 이하의 소자에 적용할 수 있고, 소자의 수율을 향상시킬 수 있다.That is, since the silicide film having a desired thickness can be formed while greatly reducing the thermal budget, it can be applied to devices of about 90 nm or less, and the yield of the devices can be improved.
Claims (4)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106611704A (en) * | 2015-10-26 | 2017-05-03 | 北京大学 | Method of preparing ultrathin silicide |
| CN110676162A (en) * | 2018-07-03 | 2020-01-10 | 合肥晶合集成电路有限公司 | Method for forming metal silicide layer, semiconductor device and method for forming semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106611704A (en) * | 2015-10-26 | 2017-05-03 | 北京大学 | Method of preparing ultrathin silicide |
| CN110676162A (en) * | 2018-07-03 | 2020-01-10 | 合肥晶合集成电路有限公司 | Method for forming metal silicide layer, semiconductor device and method for forming semiconductor device |
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