CN106611704A - Method of preparing ultrathin silicide - Google Patents
Method of preparing ultrathin silicide Download PDFInfo
- Publication number
- CN106611704A CN106611704A CN201510702268.4A CN201510702268A CN106611704A CN 106611704 A CN106611704 A CN 106611704A CN 201510702268 A CN201510702268 A CN 201510702268A CN 106611704 A CN106611704 A CN 106611704A
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- Prior art keywords
- metal
- silicide
- barrier layer
- annealing
- ultrathin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
Abstract
The invention discloses a method of preparing an ultrathin silicide. The method comprises the following steps: (1) preparing an insertion stop layer on a silicon substrate; (2) preparing a metal layer on the stop layer; (3) annealing the structure obtained in step (2) to make metal in the metal layer diffuse across the insertion stop layer and react with silicon to form an ultrathin silicide; and (4) removing excess metal and the insertion stop layer to get an ultrathin silicide. Through the method, an ultrathin silicide less than 2nm can be prepared. The amount of metal driven in is controlled by changing the thickness of the insertion stop layer, so that silicides made of the same metal but of different phases and thicknesses can be obtained. The process is of high controllability. The formed ultrathin silicide has the characteristics of low resistivity, low Schottky barrier, good uniformity, and good smoothness. Compared with the conventional ultrathin silicide preparation method, the meal deposition process window is widened greatly. The method is completely compatible with a bulk silicon CMOS process. The process is simple and low in cost.
Description
Technical field
The invention belongs to super large-scale integration manufacturing technology field, is related to one kind and prepares super thin metal silicide in integrated circuit
Method.
Background technology
When the process node of integrated circuit is advanced to 14nm, traditional planar transistor faces that short-channel effect is serious, performance degradation
Etc. problems, the requirement of scaled down can not be met.Multi-gate device by increase grid quantity method come strengthen grid with
Coupling ability between raceway groove, the main flow of mole epoch logical device after having become.As size constantly reduces, source and drain resistance
In all-in resistance, shared ratio is increasing, the ON state current serious degradation of multi-gate device, therefore reduces source and drain dead resistance pair
It is particularly significant in optimised devices ON state performance.Silicide technology is mutually compatible with traditional cmos process, and technical process autoregistration,
By the reaction of metal and silicon, it is possible to obtain lower contact resistance, the interface of low Schottky barrier, have become reduction source and drain and post
Raw resistance, the conventional means for improving device ON state current.
For small size FinFET (fin formula field effect transistor), SNWFET (enclosing gate nano line field-effect transistor) etc. three
For dimension silicon-based devices, its on-state characteristic is relevant with source-drain silicide thickness.With the gradually increase of silicide thickness, ON state electricity
Stream can be gradually reduced.For example, the SNWFET of 22nm long for grid, source-drain silicide thickness from 0nm increase to 5nm when,
ON state current have dropped 70%.Therefore it is extremely necessary that controllable ultra-thin silicide forming method is stablized in research.
Correlational study shows, after deposit super thin metal once annealing, the method such as twice annealing can form thickness after deposit metal
Relatively thin silicide.But the former has higher requirement for the thickness and uniformity of deposit metal；The characteristics of the latter is,
To form ultra-thin silicide, it is necessary to the strict temperature and time for holding first annealing controlling the amount of driving in of metal, while secondary
The temperature of annealing can not be too high, otherwise easily causes zones of different annealing temperature difference, and then caused interface spike.These are not
Foot part all limits their applications in large scale integrated circuit source and drain engineering.
The content of the invention
The present invention is directed to the problems referred to above, it is proposed that a kind of utilization interposed layer prepares ultra-thin silicide to the barrier effect that metal spreads
Method.The method reduces the requirement of source and drain dead resistance in disclosure satisfy that small size device.
Technical scheme is as follows：
A kind of method that utilization interposed layer prepares ultra-thin silicide to the barrier effect that metal spreads, comprises the following steps：
1. insertion barrier layer is prepared on a silicon substrate, its objective is to reduce the diffusion rate of metal while reducing the amount of driving in of metal,
Ultra-thin silicide is formed when reacting so as to subsequent silicidation；
2. a metal level is deposited on the barrier layer for preparing；
3. the structure that pair step 2 is obtained is annealed, and its objective is to make metal diffuse through insertion barrier layer and form super with pasc reaction
Thin silicide；
4. unnecessary metal and insertion barrier layer are removed.
Further, the insertion barrier layer preparation method described in step 1 can be atomic layer deposition (Atomic Layer
Deposition), low-pressure chemical vapor phase deposition (Low Pressure Chemical Vapor Deposition), plasma enhancing
Learning vapor deposition (Plasma Enhanced Chemical Vapor Deposition), inductively coupled plasma strengthens chemical gaseous phase
Deposit (Inductively Coupled Plasma Enhance Chemical Vapor Deposition), sputtering, thermal oxide etc..
Further, the insertion barrier layer described in step 1 can be aluminium oxide, hafnium oxide, silicon oxide etc. other to metal have
The insulating dielectric materials for having diffusion barrier to act on, choosing for barrier layer thickness should be considered with reference to its barrier properties to metal, to protect
Card metal can diffuse through in subsequent annealing process and silicification reaction occurs with substrate.Such as weaker for barrier effect oxygen
Change aluminum, within thickness should be chosen at 3nm as far as possible, and the hafnium oxide stronger for barrier effect, its thickness should be controlled as far as possible in 1nm
Within.
Further, the optional evaporation of metal deposition methods described in step 2, sputtering, plating, chemical vapor deposition (Chemical
Vapor Deposition) etc..
Further, the metal described in step 2 can be titanium, cobalt, platinum, nickel etc. other can with pasc reaction formed low-resistance silication
The material of thing, as titanium has live width effect, cobalt is big with consumption silicon amount during pasc reaction, platinum high cost, therefore preferably nickel is used as formation
The metal material of ultra-thin silicide.
Further, the annealing described in step 3 can be rapid thermal annealing (Rapid Thermal Annealing), and spike is moved back
The advanced annealing such as fiery (Spike Annealing), annealing of glittering (Flash Annealing), laser annealing (Laser Anealing)
Technology, annealing time and annealing temperature need the thickness according to barrier layer and its barrier properties to metal to determine.
Further, the method that excess metal and insertion barrier layer are removed in step 4 can adopt wet corrosion technique, for example,
When metal is nickel, and insertion barrier layer is aluminium oxide, corrosive liquid can adopt the mixed solution of sulphuric acid and hydrogen peroxide, both proportionings
For 4:1, there is corrosiveness to nickel and aluminium oxide.
Advantages of the present invention and good effect are as follows：
A) preparation of the ultra-thin silicide less than 2nm can be realized, the requirement of small size device source and drain critical process is met.
B) amount of metal for driving in can be controlled by changing the thickness for inserting barrier layer, same metal but difference can be obtained with this
The silicide of thing phase and different-thickness, process controllability are high.
C) the ultra-thin silicide for being formed has low-resistivity, low Schottky barrier, uniformity good and the characteristics of good flatness.
D) can control that the metal amount of driving in of silicification reaction is participated in by inserting barrier layer, being not as customary preparation methods needs to form sediment
Positive thin metal, therefore the requirement to metal deposition process can be relaxed significantly.
E) completely mutually compatible with Bulk CMOS technique, process is simple, cost price are little.
Description of the drawings
Fig. 1 is the preparation method flow chart of the present invention；
Fig. 2 is the structure chart after preparing insertion barrier layer；
Fig. 3 is the structure chart after depositing metal；
Fig. 4 is the structure chart after annealing；
Fig. 5 is to remove unnecessary metal and the structure chart behind insertion barrier layer.
Specific embodiment
The present invention is described in detail with instantiation below in conjunction with the accompanying drawings.
The flow process of the present invention as shown in figure 1, can realize the preparation of ultra-thin nickel silicide according to the following steps：
1) ALD on 4 cun of N-type (100) body silicon substratesAl2O3As barrier layer is inserted, as shown in Figure 2；
2) 50nm W metals are sputtered.As shown in Figure 3；
3) at 600 DEG C, rapid thermal annealing under conditions of 10min, is carried out, W metal is diffused through insertion barrier layer and given birth to pasc reaction
Into NiSi2, as shown in Figure 4；
4) it is H with proportioning2SO4：H2O2=4:1 solution removes unreacted Ni and Al2O3, etching time is 10min, such as
Shown in Fig. 5；
Ultra-thin NiSi of the thickness less than 2nm is realized finally2Preparation.
The embodiment of the present invention is not limited to the present invention.Any those of ordinary skill in the art, without departing from the technology of the present invention
In the case of aspects, many possible changes are made to technical solution of the present invention using the methods and techniques content of the disclosure above all
Dynamic and modification, or the Equivalent embodiments for being revised as equivalent variations.Therefore, every content without departing from technical solution of the present invention, according to
According to the technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, the present invention is still fallen within
In the range of technical scheme protection.
Claims (10)
1. a kind of preparation method of ultra-thin silicide, its step is：
1) insertion barrier layer is prepared on a silicon substrate；
2) metal level is prepared on the barrier layer for preparing；
3) to step 2) structure that obtains anneals, and makes the metal of the metal level diffuse through the insertion barrier layer and pasc reaction
Form ultra-thin silicide；
4) unnecessary metal and the insertion barrier layer are removed, obtains ultra-thin silicide.
2. the method for claim 1, it is characterised in that the method for preparing the insertion barrier layer is：Atomic layer deposition method,
Low-pressure chemical vapor phase deposition method, plasma body reinforced chemical vapor deposition method, inductively coupled plasma strengthen chemical gas
Phase deposition process, sputtering method or thermal oxidation process.
3. method as claimed in claim 1 or 2, it is characterised in that the insertion barrier material is the metal to the metal level
Insulating dielectric materials with diffusion barrier effect；The metal layer material is the material that low resistance silicide can be formed with pasc reaction
Material.
4. method as claimed in claim 3, it is characterised in that the material on the insertion barrier layer is aluminium oxide, hafnium oxide or oxidation
Silicon.
5. method as claimed in claim 3, it is characterised in that the material of the metal level is titanium, cobalt, nickel or platinum.
6. method as claimed in claim 3, it is characterised in that the metal is prepared using deposition process.
7. method as claimed in claim 6, it is characterised in that the deposition process is evaporation, sputtering, plating or chemical gaseous phase are formed sediment
Product method.
8. method as claimed in claim 3, it is characterised in that the method for carrying out the annealing is：Quick thermal annealing method, spike
Method for annealing, glitter method for annealing or laser anneal method.
9. method as claimed in claim 3, it is characterised in that unnecessary metal is removed using wet corrosion technique and the insertion stops
Layer.
10. method as claimed in claim 9, it is characterised in that the material of the metal level is nickel, the material on the insertion barrier layer
For aluminium oxide, the corrosive liquid in the wet corrosion technique is the mixed solution of sulphuric acid and hydrogen peroxide；Wherein, sulphuric acid and dioxygen
The proportioning of water is 4:1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510702268.4A CN106611704A (en) | 2015-10-26 | 2015-10-26 | Method of preparing ultrathin silicide |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510702268.4A CN106611704A (en) | 2015-10-26 | 2015-10-26 | Method of preparing ultrathin silicide |
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| CN106611704A true CN106611704A (en) | 2017-05-03 |
Family
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| CN201510702268.4A Pending CN106611704A (en) | 2015-10-26 | 2015-10-26 | Method of preparing ultrathin silicide |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110676162A (en) * | 2018-07-03 | 2020-01-10 | 合肥晶合集成电路有限公司 | Method for forming metal silicide layer, semiconductor device and method for forming semiconductor device |
| CN112666235A (en) * | 2021-01-19 | 2021-04-16 | 郑州轻工业大学 | PtNi bimetal-based two-electrode integrated enzyme-free glucose sensor and preparation method thereof |
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| US6156644A (en) * | 1995-12-07 | 2000-12-05 | Samsung Electronics Co., Ltd. | Method for forming interconnects for semiconductor devices using reaction control layers, and interconnects formed thereby |
| US6346465B1 (en) * | 1997-06-23 | 2002-02-12 | Nec Corportion | Semiconductor device with silicide contact structure and fabrication method thereof |
| US20050026428A1 (en) * | 2003-08-02 | 2005-02-03 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor device and semiconductor device manufactured using the same |
| US20050085058A1 (en) * | 2003-10-20 | 2005-04-21 | Derderian Garo J. | Methods of forming conductive metal silicides by reaction of metal with silicon |
| KR100628219B1 (en) * | 2004-12-24 | 2006-09-26 | 동부일렉트로닉스 주식회사 | method for forming silicide of semiconductor device |
| CN104347423A (en) * | 2013-08-09 | 2015-02-11 | 台湾积体电路制造股份有限公司 | Integrating junction formation of transistors with contact formation |
-
2015
- 2015-10-26 CN CN201510702268.4A patent/CN106611704A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6156644A (en) * | 1995-12-07 | 2000-12-05 | Samsung Electronics Co., Ltd. | Method for forming interconnects for semiconductor devices using reaction control layers, and interconnects formed thereby |
| US6346465B1 (en) * | 1997-06-23 | 2002-02-12 | Nec Corportion | Semiconductor device with silicide contact structure and fabrication method thereof |
| US20050026428A1 (en) * | 2003-08-02 | 2005-02-03 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor device and semiconductor device manufactured using the same |
| US20050085058A1 (en) * | 2003-10-20 | 2005-04-21 | Derderian Garo J. | Methods of forming conductive metal silicides by reaction of metal with silicon |
| KR100628219B1 (en) * | 2004-12-24 | 2006-09-26 | 동부일렉트로닉스 주식회사 | method for forming silicide of semiconductor device |
| CN104347423A (en) * | 2013-08-09 | 2015-02-11 | 台湾积体电路制造股份有限公司 | Integrating junction formation of transistors with contact formation |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110676162A (en) * | 2018-07-03 | 2020-01-10 | 合肥晶合集成电路有限公司 | Method for forming metal silicide layer, semiconductor device and method for forming semiconductor device |
| CN112666235A (en) * | 2021-01-19 | 2021-04-16 | 郑州轻工业大学 | PtNi bimetal-based two-electrode integrated enzyme-free glucose sensor and preparation method thereof |
| CN112666235B (en) * | 2021-01-19 | 2023-03-10 | 郑州轻工业大学 | PtNi bimetal-based two-electrode integrated enzyme-free glucose sensor and preparation method thereof |
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Application publication date: 20170503 |