TWI562299B - Electronic package and the manufacture thereof - Google Patents

Electronic package and the manufacture thereof

Info

Publication number
TWI562299B
TWI562299B TW104109161A TW104109161A TWI562299B TW I562299 B TWI562299 B TW I562299B TW 104109161 A TW104109161 A TW 104109161A TW 104109161 A TW104109161 A TW 104109161A TW I562299 B TWI562299 B TW I562299B
Authority
TW
Taiwan
Prior art keywords
manufacture
electronic package
package
electronic
Prior art date
Application number
TW104109161A
Other languages
English (en)
Other versions
TW201635456A (zh
Inventor
Shih Chao Chiu
Chia Cheng Chen
Chun Hsien Lin
Yu Cheng Pai
Chih Wen Fan
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW104109161A priority Critical patent/TWI562299B/zh
Priority to CN201510147274.8A priority patent/CN106158782B/zh
Publication of TW201635456A publication Critical patent/TW201635456A/zh
Application granted granted Critical
Publication of TWI562299B publication Critical patent/TWI562299B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
TW104109161A 2015-03-23 2015-03-23 Electronic package and the manufacture thereof TWI562299B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW104109161A TWI562299B (en) 2015-03-23 2015-03-23 Electronic package and the manufacture thereof
CN201510147274.8A CN106158782B (zh) 2015-03-23 2015-03-31 电子封装件及其制法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW104109161A TWI562299B (en) 2015-03-23 2015-03-23 Electronic package and the manufacture thereof

Publications (2)

Publication Number Publication Date
TW201635456A TW201635456A (zh) 2016-10-01
TWI562299B true TWI562299B (en) 2016-12-11

Family

ID=57337426

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104109161A TWI562299B (en) 2015-03-23 2015-03-23 Electronic package and the manufacture thereof

Country Status (2)

Country Link
CN (1) CN106158782B (zh)
TW (1) TWI562299B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI706523B (zh) * 2019-09-02 2020-10-01 矽品精密工業股份有限公司 電子封裝件

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001015650A (ja) * 1999-06-29 2001-01-19 Nec Corp ボールグリッドアレイパッケージとその製造方法
US20110155433A1 (en) * 2008-08-27 2011-06-30 Takuo Funaya Wiring board capable of containing functional element and method for manufacturing same
TWI451549B (zh) * 2010-11-12 2014-09-01 Unimicron Technology Corp 嵌埋半導體元件之封裝結構及其製法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4012496B2 (ja) * 2003-09-19 2007-11-21 カシオ計算機株式会社 半導体装置
US20110186960A1 (en) * 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
CN101930958A (zh) * 2010-07-08 2010-12-29 日月光半导体制造股份有限公司 半导体封装件及其制造方法
CN102386105B (zh) * 2010-09-01 2016-02-03 群成科技股份有限公司 四边扁平无接脚封装方法及其制成的结构

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001015650A (ja) * 1999-06-29 2001-01-19 Nec Corp ボールグリッドアレイパッケージとその製造方法
US20110155433A1 (en) * 2008-08-27 2011-06-30 Takuo Funaya Wiring board capable of containing functional element and method for manufacturing same
TWI451549B (zh) * 2010-11-12 2014-09-01 Unimicron Technology Corp 嵌埋半導體元件之封裝結構及其製法

Also Published As

Publication number Publication date
CN106158782B (zh) 2020-02-21
CN106158782A (zh) 2016-11-23
TW201635456A (zh) 2016-10-01

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