TWI559482B - Package structure and manufacturing method thereof - Google Patents

Description

Package structure and manufacturing method thereof

The present invention relates to a package structure and a method of fabricating the same, and more particularly to a package structure containing a zinc element in a metal layer under bumps and a method of fabricating the same.

In order to increase the number of transistors in the integrated circuit, the industry continues to reduce the line width of the wires inside the integrated circuit to achieve higher density of the transistor. At present, the process technology has been able to approach the nanometer process with a wire width approaching 0.13 mm, but the process technology of reducing the line width has also approached the physical limit, which will make the process technology face an unprecedented bottleneck. When the semiconductor process reached its limit, it forced the major manufacturers to actively open another way to improve the performance of electronic components. The current trend in the industry is three-dimensional packaging.

The three-dimensional package can package several semiconductor chips into a single package by stacking. This technology is represented by a stacked multi-chip package (S-MCP). A wafer made by a three-dimensional package is called a three-dimensional wafer.

Three-dimensional packaging does not require cutting edge technology, and the total cost is not high. The required functions can be included on each wafer in a three-dimensional package without having to place all functions in a single wafer. Since the wafer-to-wafer connection can be directly made in the package, the input/output of the package and the routing of the printed circuit board can be simplified. Again, a single three-dimensional seal The mounting system is made up of several wafers corresponding to the footprint, so the length and width of the printed circuit board can be reduced.

The difference between the three-dimensional package and the traditional planar package is mainly the reduction of the wafer area and the length of the wire, which can reduce the manufacturing cost of the entire system. In addition, as the length of the wire is greatly reduced, the signal transmission speed will be significantly improved, thereby enabling the chip to achieve faster and better performance.

However, as the three-dimensional packaging generation enters, the required electronic packaging process is relatively difficult. In particular, in order to allow the wafers to be stacked and operated smoothly, it is necessary to develop more advanced solder ball joint process technology to create an excellent Under Bump Metallurgy (UBM) and actively improve various bump contact materials. Ball placement technology to consolidate the underlying structure of the three-dimensional wafer.

In the three-dimensional packaging technology, the most important difference from the traditional packaging is the emergence of micro bumps. A micro-contact is a bump joint whose ball volume is much smaller than that of a conventional contact, that is, an under bump metallization layer (UBM) and a solder ball joint. The diameter of the solder balls used will be as small as 100 microns or less.

In conventional packaging techniques, the solder balls used in the contacts are approximately 600 microns in diameter. Due to the large shrinkage of the solder joints, the solder is likely to be completely converted to intermetallic compounds (IMCs) after bonding, instead of the original solder. In three-dimensional packaging, these micro-contacts play a key role in transmitting electronic signals and providing mechanical bonding between wafers. Therefore, the factors that determine the telecommunications transmission and joint strength in the three-dimensional package are no longer the solder itself, but newly generated. Mesometallic compound.

In the prior art, after a long time of reflow, a tin-copper compound (Cu ₆ Sn ₅ ), a tin-nickel compound (Ni ₃ Sn ₄ ) or a tin-silver compound (Ag ₃ ) is formed between the solder and the under bump metal layer. Sn). After a long time of heat treatment, the tin-copper compound (Cu ₆ Sn ₅ ) will gradually transform into copper 3 tin (Cu ₃ Sn) and generate a large number of kirkendall pores. This phenomenon will greatly weaken the micro-joining. The strength of the point.

The mechanical strength of the tin-nickel compound is weaker than that of the tin-copper compound. When the tin-nickel compound and the tin-copper compound coexist, cracking occurs, and the mechanical strength of the solder joint is greatly reduced. In addition, the tin-silver compound is born in the silver material. After the thermal cycle test or heat treatment, the tin-silver compound and the solder itself may cause the solder joint to rupture due to the difference in thermal expansion coefficient, causing the contact to be short-circuited or destroyed.

Therefore, there is a need to provide a package structure, and the material of the under bump metal layer of the package structure is different from that of the prior art under bump metal layer to solve the aforementioned problems.

It is an object of the present invention to provide a package structure that reduces the generation of intermetallic compound kirkendall voids.

To achieve the above object, the present invention provides a package structure comprising: a semiconductor substrate; a pad layer on the semiconductor substrate; a bump under metal layer on the pad layer, and electrically connecting the pad The underlayer metal layer comprises the following components: 3.5 to 30 wt% of zinc, and a balance of copper; and a solder on the underlying metal layer of the bump.

In the above package structure, the zinc content of the metal layer under the bump is preferably 3.5 to 15 wt%, or the zinc content of the metal layer under the bump is 3.5~5wt%.

The package structure described above further includes a package substrate positioned on the solder such that the solder is interposed between the semiconductor substrate and the package substrate. The package substrate includes a contact pad that abuts the solder and electrically connects the solder.

Another object of the present invention is to provide a method of fabricating a package structure that reduces the generation of kirkendall voids.

To achieve the above object, the present invention provides a method of fabricating a package structure, comprising the steps of: providing a semiconductor substrate; forming a pad layer on the semiconductor substrate; forming a bump underlying metal layer on the pad layer, The under bump metal layer comprises the following composition: 3.5 to 30 wt% zinc, and a balance of copper; and a solder is formed on the under bump metal layer.

In the above method for manufacturing a package structure, the content of zinc in the under-metal layer of the bump is preferably 3.5 to 15% by weight, or the content of zinc in the under-metal layer of the bump is 3.5 to 5 wt%.

In the above method for manufacturing a package structure, the under bump metal layer is formed by a sputtering process.

The manufacturing method of the package structure further includes the steps of: disposing a package substrate on the solder so that the solder is interposed between the semiconductor substrate and the package substrate, wherein the package substrate comprises a contact pad, the contact pad The solder is abutted and electrically connected to the solder.

The invention utilizes the addition of zinc element in the underlying metal layer of the bump, can inhibit the formation of the tin-copper alloy and the void, and form a copper-zinc-tin alloy. The copper zinc tin alloy is formed in the interface of a tin-copper alloy (Cu ₆ Sn ₅ ). The formation of the copper zinc-tin alloy can block the interdiffusion of copper and tin, thereby slowing the reaction of tin and copper in the interface. The copper-tin-zinc alloy is more stable than the copper-tin alloy, so as to reduce the formation of copper 3 tin alloy (Cu ₃ Sn) and at the same time reduce the generation of kirkendall pores in the substrate due to the thermodynamics between copper and zinc. Stable, inhibiting copper from diffusing outward from the substrate to form a metal, and improving the mechanical reliability of the joint.

If the solder contains silver metal components, zinc will be incorporated into the solder to greatly reduce the subcooling interval during the hot reflow process, while the lower supercooling interval can effectively suppress the large-sized tin-silver alloy in the solder. The growth of (Ag ₃ Sn) will increase the mechanical reliability of the welding system and the reliability of the thermal cycle.

100‧‧‧Package structure

110‧‧‧Semiconductor substrate

120‧‧‧pad layer

130‧‧‧Protective layer

131‧‧‧ openings

140‧‧‧Under bump metal layer

150‧‧‧ solder

160‧‧‧Package substrate

170‧‧‧Contact pads

210‧‧‧ tin-silver alloy

910‧‧‧ tin-silver alloy

920‧‧‧Copper 3 tin

S100~S108‧‧‧Steps

1 is a block diagram showing the flow of a method of fabricating a package structure according to an embodiment of the present invention.

2a-2d are schematic cross-sectional views showing a process of manufacturing a package structure according to an embodiment of the present invention.

Figure 3 is a photo of the interface between a conventional solder and a metal layer under the bump.

4 is a photograph of an interface between a solder and a metal under bump using the package structure of the present invention.

The above and other objects, features and advantages of the present invention will become more <RTIgt; Furthermore, the directional terms used in the present invention are, for example, "upper", "lower", "before", "after", "left", "right", "inside", "outside", "vertical" or " Horizontal, etc., only refers to the direction of the additional schema. Therefore, use The directional terms are used to illustrate and understand the present invention and are not intended to limit the invention.

1 is a block diagram showing the flow of a method of fabricating a package structure according to an embodiment of the present invention. 2a-2d are schematic cross-sectional views showing a process of manufacturing a package structure according to an embodiment of the present invention. Referring to FIG. 1, the manufacturing method of the package structure includes the following steps:

Step S100: providing a semiconductor substrate. As shown in FIG. 2a, in this step, the composition of the semiconductor substrate 110 may include a semiconductor material such as, but not limited to, a semiconductor wafer or a germanium substrate. The semiconductor substrate 110 may also contain a group III, group IV, or group V element. The semiconductor substrate 110 may include a plurality of insulating structures (not shown) such as a shallow trench isolation (STI) structure or a local yttrium oxide (LOCOS) structure. The insulating structure can be used to isolate a plurality of microelectronic units (not shown). The plurality of microelectronic units formed in the semiconductor substrate 110 include a transistor such as a MOSFET, a complementary MOS transistor, a bipolar-connected transistor (BJT), and a high voltage. Transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFET/NFETs), resistors, diodes, capacitors, inductors, fuses, or other suitable units. A variety of processes for forming a plurality of microelectronic units include deposition, etching, implantation, lithography, tempering, or other suitable processes. The microelectronic unit can form integrated circuit components such as logic components, input/output components, system single chip (SoC) components, combinations of the above, or other suitable types of components via interconnects.

Step S102: forming a pad layer on the semiconductor substrate. As shown in FIG. 2b, in this step, a pad layer 120 and a protective layer 130 are formed on the semiconductor substrate 110. The material of the pad layer 120 can be, but is not limited to, copper, aluminum, copper alloy, or other existing conductive materials. The composition of the pad layer 120 can also be Silver, gold, nickel, tungsten, alloys of the above, and/or multilayer structures as described above. In one embodiment, the integrated circuit of individual wafers can be wired to the external structure during the bonding process.

When the protective layer 130 is formed on the semiconductor substrate 110 and the pad layer 120, the protective layer 130 may be patterned to form an opening 131 and expose a portion of the pad layer 120 by a lithography and etching process. The composition of the protective layer 130 may be a non-organic material such as tantalum nitride, hafnium oxynitride, antimony oxide, or a combination thereof. In another embodiment, the protective layer 130 may be composed of an organic material such as an epoxy resin, a polyimide, or other softer organic dielectric material.

Step S104: forming a bump under metal layer on the pad layer. As shown in FIG. 2b, in this step, the under bump metallization layer (UBM) 140 can be formed on the pad layer 120 by any different method, such as electroless plating, sputtering, Or electroplating. In this embodiment, the under bump metal layer 140 can be formed by a sputtering process. The under bump metal layer 140 includes the following components: 3.5 to 30 wt% of zinc, and a balance of copper. Preferably, the under bump metal layer 140 has a zinc content of 3.5 to 15% by weight. Alternatively, the under bump metal layer 140 has a zinc content of 3.5 to 5 wt%.

Step S106: forming solder on the under-metal layer of the bump. In this step, a solder 150 may be formed on the under bump metal layer 140 by evaporation, electroplating, electroless plating, or screen printing. The solder 150 may be any different. Metal, metal alloy, or a mixture of metal and other materials. In the present embodiment, the solder 150 may be a composition of 63 by weight of tin and 37 parts by weight of lead, or a tin alloy of 5 parts by weight and 95 parts by weight of lead alloy. Finally, the solder 150 is reflowed by heating to form a sphere. During the thermal reflow process, copper and tin are mixed with each other to produce a tin-copper alloy, but since the under bump metal layer 140 contains zinc, the formation of tin-copper alloy and voids can be suppressed, and a copper-tin-zinc alloy can be formed. In the interface of the copper-tin-zinc alloy (Cu ₆ (Sn, Zn) ₅ ), the copper-tin-zinc alloy is more stable than the copper-tin alloy, so as to reduce the formation of copper 3 tin alloy (Cu ₃ Sn) and simultaneously reduce the Kendall In addition to the thermodynamic stability of copper and zinc in the substrate, zinc inhibits the diffusion of copper from the substrate to form a mesogen, which improves the mechanical reliability of the joint.

In addition, if the solder 150 contains a silver metal component, in the process of thermal reflow, zinc will be incorporated into the solder to greatly reduce the supercooling interval, and the lower supercooling interval can effectively suppress the large sheet in the solder. The growth of tin-silver alloy (Ag ₃ Sn) will increase the mechanical reliability of the welding system and the reliability of the thermal cycle.

Figure 3 is a photo of the interface between a conventional solder and a metal layer under the bump. It was taken using a scanning electron microscope and photographed at a magnification of three thousand times. 4 is a photograph of an interface between a solder and a metal under bump using the package structure of the present invention. It was also photographed using a scanning electron microscope at a magnification of three thousand times.

As can be seen from the comparison of FIGS. 3 and 4, the area of the tin-silver alloy 910 of FIG. 3 is larger than the area of the tin-silver alloy 210 of FIG. 4, and FIG. 3 also shows copper 3 tin (Cu ₃ Sn) 920. A large area of tin-silver alloy 910 and copper 3 tin 920 will greatly weaken the strength of the micro-contact. In FIG. 4, there is no generation of Cu ₃ Sn (Cu ₃ Sn), and the area of the tin-silver alloy 210 is also small, so that the mechanical reliability and thermal cycle reliability of the welding system can be improved.

Step S108: setting the package substrate on the solder so that the solder is interposed between the semiconductor substrate and the package substrate. In this step, the package substrate 160 includes a contact pad 170 that abuts the solder 150 and is electrically connected to the solder 150.

The package structure 100 as shown in FIG. 2d can be obtained through the above steps S100 to S108. The package structure 100 includes a semiconductor substrate 110, a pad layer 120, an under bump metal layer 140, and a solder 150. The pad layer 120 is located on the semiconductor substrate 110. The under bump metal layer 140 is located on the pad layer 120 and electrically connected to the pad layer 120. The under bump metal layer 140 comprises the following components: 3.5-30% by weight of zinc, and a balance of copper. Preferably, the under bump metal layer 140 has a zinc content of 3.5 to 15% by weight. Alternatively, the under bump metal layer 140 has a zinc content of 3.5 to 5 wt%. The solder 150 is positioned on the under bump metal layer 140.

Preferably, the package structure 100 further includes a package substrate 160 disposed on the solder 150 such that the solder 150 is interposed between the semiconductor substrate 110 and the package substrate 160. The package substrate 160 includes a contact pad 170 that abuts the solder 150 and is electrically connected to the solder 150.

The invention utilizes the addition of zinc element in the underlying metal layer of the bump, can inhibit the formation of the tin-copper alloy and the void, and form a copper-zinc-tin alloy. The copper zinc tin alloy is formed in the interface of a tin-copper alloy (Cu ₆ Sn ₅ ). The formation of the copper zinc-tin alloy can block the interdiffusion of copper and tin, thereby slowing the reaction of tin and copper in the interface. The copper-tin-zinc alloy is more stable than the copper-tin alloy, so as to reduce the formation of copper 3 tin alloy (Cu ₃ Sn) and at the same time reduce the generation of kirkendall pores in the substrate due to the thermodynamics between copper and zinc. Stable, inhibiting copper from diffusing outward from the substrate to form a metal, and improving the mechanical reliability of the joint.

If the solder contains silver metal components, zinc will be incorporated into the solder to greatly reduce the subcooling interval during the hot reflow process, while the lower supercooling interval can effectively suppress the large-sized tin-silver alloy in the solder. The growth of (Ag ₃ Sn) will increase the mechanical reliability of the welding system and the reliability of the thermal cycle.

The package structure and the manufacturing method thereof of the invention can be used for three-dimensional packaging, in particular, can be applied to micro-contacts of three-dimensional packages, and newly generated in the process when the diameter of the solder balls used is less than 100 micrometers. In the intermetallic compound, copper 3 tin (Cu ₃ Sn) and a large amount of tin-silver compound are not produced, which improves the mechanical reliability and thermal cycle reliability of the welding system in the three-dimensional package.

In summary, the present invention is merely described as an embodiment or an embodiment of the technical means for solving the problem, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made to the scope of the patent application of the present invention, or the scope of the patent application of the present invention, are covered by the scope of the invention.

S100~S108‧‧‧Steps

Claims (11)

A package structure comprising: a semiconductor substrate; a pad layer on the semiconductor substrate; a bump under metal layer on the pad layer, and electrically connecting the pad layer, the under bump metal layer The composition includes the following components: 3.5 to 30 wt% of zinc, and a balance of copper; and a solder on the underlying metal layer of the bump. The package structure according to claim 1, wherein the underlying metal layer has a zinc content of 3.5 to 15% by weight. The package structure according to claim 1, wherein the underlying metal layer has a zinc content of 3.5 to 5 wt%. The package structure according to claim 1, further comprising a package substrate disposed on the solder such that the solder is interposed between the semiconductor substrate and the package substrate. The package structure of claim 4, wherein the package substrate comprises a contact pad that abuts the solder and electrically connects the solder. A manufacturing method of a package structure, comprising the steps of: providing a semiconductor substrate; forming a pad layer on the semiconductor substrate; Forming a sub-bump metal layer on the pad layer, the under bump metal layer comprises: 3.5 to 30 wt% zinc, and a balance of copper; and forming a solder on the under bump metal layer. The method for manufacturing a package structure according to claim 6, wherein the under bump metal layer has a zinc content of 3.5 to 15% by weight. The method for manufacturing a package structure according to claim 6, wherein the under bump metal layer has a zinc content of 3.5 to 5 wt%. The method of fabricating a package structure according to claim 6, wherein the under bump metal layer is formed by a sputtering process. The method for manufacturing a package structure according to claim 6, further comprising the steps of: providing a package substrate on the solder such that the solder is interposed between the semiconductor substrate and the package substrate. The method of manufacturing a package structure according to claim 10, wherein the package substrate comprises a contact pad that abuts the solder and electrically connects the solder.