TWI556447B - 半導體裝置及其製作方法 - Google Patents

半導體裝置及其製作方法 Download PDF

Info

Publication number
TWI556447B
TWI556447B TW103145766A TW103145766A TWI556447B TW I556447 B TWI556447 B TW I556447B TW 103145766 A TW103145766 A TW 103145766A TW 103145766 A TW103145766 A TW 103145766A TW I556447 B TWI556447 B TW I556447B
Authority
TW
Taiwan
Prior art keywords
layer
dielectric layer
interface
forming
gate
Prior art date
Application number
TW103145766A
Other languages
English (en)
Other versions
TW201537752A (zh
Inventor
陳聖文
林鈺庭
張哲豪
游偉明
王廷君
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201537752A publication Critical patent/TW201537752A/zh
Application granted granted Critical
Publication of TWI556447B publication Critical patent/TWI556447B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane

Description

半導體裝置及其製作方法
本發明係有關於一種半導體裝置及其製作方法，特別係有關於一種以障蔽層作為介電層的半導體裝置。
半導體裝置被用於各式各樣的電子應用中，例如：個人電腦、手機、數位相機和其他電子設備。典型地製作半導體裝置是藉由連續地沉積一些絕緣層或介電層、導電層和半導體層在一半導體基板上，和用微影製程圖案化這些各式各項的材料層以形成電路元件。
電晶體為一些經常形成在半導體裝置上的電路元件，許多的電晶體可能形成在半導體裝置上，根據電路設計需要，電容器、電感器、電阻器、二極體、導線或其他元件也可能形成在半導體裝置上。場效電晶體(field effect transistor,FET)是一種電晶體的形式。
一般來說，電晶體包括在源區和汲區之間的閘極堆疊，源區和汲區可能包括基板的摻雜區，源區和汲區可能為了特定應用而表現適合的摻雜分佈，閘極堆疊位於通道區之上，可能包括在基板中插入閘極和通道區之間的閘介電 質。
在一實施例中，提供一種形成半導體裝置的方法，此方法包括形成一界面層和形成一介電層在此界面層之上，形成一導電層在此介電層之上，以及在此導電層之上進行一處理以增加此導電層的一阻氧能力。在一實施例中，此處理為一氮化處理。
在另一實施例中，提供一種形成半導體裝置的方法，此方法包括提供一基板和形成一閘介電層在此基板之上，形成一障蔽層在此閘介電層之上以及沿著此障蔽層和此閘介電層之間的一界面，在此障蔽層中增加一氮濃度。
在又一實施例中，提供一種半導體裝置包括一基板具有一閘介電層在此基板之上，一導電層在此閘介電層之上以及一閘極在此導電層之上，相較於遠離此閘介電層和此導電層之間的一界面的一第一位置，此導電層在沿著此閘介電層和此導電層之間的此界面上具有一更高的相對氮濃度。
102‧‧‧基板
104‧‧‧虛擬閘極堆疊
104a‧‧‧虛擬閘介電質
104b‧‧‧虛擬閘極
106‧‧‧微摻雜源/汲極區
108‧‧‧閘極間隙壁
110‧‧‧高摻雜源/極區
112‧‧‧矽化區
214‧‧‧層間介電層
320‧‧‧開口
420‧‧‧介面層
422‧‧‧閘介電層
524‧‧‧導電層
626‧‧‧閘極
1010‧‧‧閘極堆疊
1202-1210‧‧‧步驟
從下列詳盡的描述搭配附圖一起閱讀時，可以更了解本案發明的方面，應該注意的是，根據在工業中的標準慣例，各種特徵並不會依實際的尺寸來繪製，事實上，為了更清楚地進行討論，各種特徵的尺寸可能被任意的增大或 縮小。
第1-6圖係根據一些實施例說明一種形成半導體裝置的方法的各種中間階段。
第7-11圖係根據一些實施例說明另一種形成半導體裝置的方法的各種中間階段。
第12圖係根據一些實施例說明形成半導體裝置的處理步驟的流程圖。
為了實施各種實施例的不同特徵，下述的發明內容提供許多不同的實施例或範例，為了簡化本案發明，以下描述組成和擺放的特定範例，當然，這些少數的範例並非用以限制本案，舉例來說，在描述中，形成一第一特徵『在』一第二特徵之『上』，這段描述可能包括第一特徵和第二特徵形成直接接觸的實施例，可能也包括在第一和第二特徵之間形成額外的特徵使得第一和第二特徵沒有直接接觸。此外，在各種實施例中，本案發明可能使用重複的參考數字和/或字母，重複的目的是為了簡化和清楚說明，並非意指討論的各種的實施例和/或配置之間有關聯。
此外，有關空間的詞彙，如『在……之下』、『在下方』、『在……下方、』『下部的』、『在……上面』或『上部的』，用來方便描述文中在附圖中所示的一元件或一特徵與另一元件或一特徵之關係。有關空間的詞彙除了圖中描繪的位向，用來包含使用中的裝置中的不同位向或操 作。例如，如果一附圖中的裝置被翻轉，元件將會被描述為位於其它元件或特徵之『下』側，或是被定向為位於其他元件或特徵之『上』側，因此，例示性的詞彙『下』可以包含『下』和『上』兩種方向，設備可能被以別的方式翻轉(旋轉90度或是其他位向)且空間上相對的描述符號可能據此解釋。
提供以障蔽層作為介電層和一種製造方法以減少或預防氧化物在連續的處理步驟期間重新長出，此處所討論的說明實施例在為了平面電晶體而形成高介電係數閘介電質的內容之中，實施例不但討論後閘極(gate-last)方法也討論先閘極(gate-first)方法，本案發明的特徵可能被運用在其他內容中，舉例來說，在連續的處理步驟期間重新長出氧化物可能是一個問題，可能被運用在包括其他其他電晶體、電容器或相似物中。
第1-6圖係根據一些實施例說明一種形成閘極的實施例。首先參考第1圖，表示基板102具有形成在其上的虛擬閘極堆疊104，舉例來說，基板102可能包括塊狀矽、有摻雜或沒有摻雜的、或半導體在絕緣層上(semiconductor-on-insulator,SOI)基板的主動層，一般來說，SOI基板包括半導體材料層形成在絕緣層之上，半導體材料例如：矽，舉例來說，絕緣層可能為埋藏氧化物(buried oxide,BOX)層或矽氧化層，在基板之上提供絕緣層，基板典型地會使用矽或玻璃基板，也可能使用其他的基板，例如多層的或梯度的基板。
以下討論更多細節，虛擬閘極堆疊104為一種犧牲結構，用以排列和形成鄰近虛擬閘極堆疊104的源/汲區，且將會在連續的處理步驟中被取代，確切而言，虛擬閘極電極104可能以任何合適的材料或處理形成。在一些實施例中，當其他裝置在晶片(如其它電晶體)上形成時，虛擬閘極堆疊104也會同時形成。在一些實施例中，可能希望從虛擬閘介電質104a和虛擬閘極104b形成虛擬閘極堆疊104，可能用這些層為其他裝置形成具功能性的閘極堆疊。
以植入摻雜物形成微摻雜源/汲極(lightly-doped source/drain,LDD)區106，摻雜物例如：n型摻雜物或p型摻雜物，用虛擬閘極堆疊104作為光罩，藉此以虛擬閘極堆疊104的邊緣排列LDD區106，可能也形成環狀和/或袋狀區域(未畫出)。
第1圖進一步說明沿著虛擬閘極堆疊104的側壁形成閘極間隙壁108。在一些實施例中，閘極間隙壁108由沈積一或多層介電材質形成，除了鄰近虛擬閘極堆疊104的介電材料外，以非等向性蝕刻移除其它介電材質。舉例來說，在一些實施例中，從氮化矽層形成閘極間隙壁108，如第1圖所說明，以非等向性溼蝕刻或乾蝕刻移除氮化矽層的水平部分以圖案化氮化矽層，形成閘極間隙壁108。在一些實施例中，由多層形成閘極間隙壁108。舉例來說，在一些實施例中，閘極間隙壁108包括氧化矽層和上覆的氮化矽層。
由植入摻雜物形成高摻雜源/極區110，摻雜物 例如：n型摻雜物或p型摻雜物，用虛擬閘極堆疊104和閘極間隙壁108當做光罩，藉此以閘極間隙壁108的邊緣排列高摻雜源/極區110。
第1圖也說明矽化區112的形成，矽化區112可能由全面覆蓋沈積一層金屬薄層形成，金屬薄層像是：鎳、鉑、鈷和其組合，接著加熱基板，加熱使基板(例如：矽)與金屬接觸處和金屬反應，在反應之後，在基板和金屬之間形成金屬矽化層，沒有反應的金屬會被選擇性移除。
僅為了說明而提供上述的結構，其他的實施例也可能利用其他結構或特徵，舉例來說，一些實施例可能加上埋藏的壓力源(stressor)、以壓力源填滿的在凹處的源/汲區、突起的源/汲區、不同材料、不同閘極結構和材料、環形佈植、不同的源/汲區的摻雜分佈和相似物。
參考第2圖，根據一些實施例形成第一層間介電(inter-layer dielectric,ILD)層214，舉例來說，第一層間介電層214以低介電係數介電材質形成，像是：含碳材料、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)、氟化矽酸玻璃(fluorinated silicate glass,FSG)、SiOxCy、旋塗玻璃(Spin-On-Glass)、旋塗聚合物(Spin-On-Polymers)、矽碳材料(silicon carbon material)、其化合物、其成分、其組合或相似物，第一層間介電層214以任何合適的方法形成，像是：旋轉塗佈(spinning)、化學氣相沉積(chemical vapor deposition, CVD)和電漿增強化學氣相沉積(plasma-enhanced CVD,PECVD)，第一ILD層214可能包括複數的介電層。
移除在虛擬閘極堆疊104之上第一ILD層214，露出虛擬閘極堆疊104，用化學機械研磨(chemical mechanical polishing,CMP)處理平坦化第一ILD層214的上表面，與第2圖說明的虛擬閘極堆疊104的上表面齊高。
第3圖係根據一些實施例說明虛擬閘極堆疊104的選擇性移除(見第2圖)，因此形成開口320。在一些實施例中，虛擬閘極堆疊104為多晶矽材料，虛擬閘極堆疊104可能被乾蝕刻或濕蝕刻選擇性蝕刻，在使用乾蝕刻的情況下，處理氣體可能包括CF4、CHF3、NF3、SF6、Br2、HBr、Cl2或其組合，可能隨意地使用稀釋氣體，像是：氮氣、氧氣或氬氣，在使用濕蝕刻的情況下，化學物可能包括H4OH：H2O2：H2O(APM)、NH2OH、KOH、HNO3：NH4F：H2O和/或其相似物。
在一些實施例中，虛擬閘極堆疊104包括氧化矽虛擬閘極介電質104a，氧化矽可能使用稀釋的氫氟酸的濕蝕刻流程移除，如果ILD層214和虛擬閘極介電質104a使用相似的材料，在移除虛擬閘極介電質104a其間，可能使用光罩保護ILD層214。
第4圖係根據一些實施例說明在開口320中，介面層420沿著基板表面形成，介面層420幫助緩衝基板102和連續形成的高介電係數介電層。在一些實施例中，介面層420為化學氧化矽，可能由化學反應產生，舉例來說，化學氧化物可能以去離子水加上臭氧(DIO3)、NH4OH+H2O2+H2O (APM)或其他方法形成，其他的實施例可能利用不同的材料或是處理形成介面層420。在一實施例中，介面層420可能具有約10Å至約30Å的厚度。
在介面層420之上形成閘介電層422。在一實施例中，閘介電層422包括一或更多高介電係數介電層(例如：具有大於3.9的介電係數)，舉例來說，一或更多閘介電層可能包括一或更多層的金屬氧化物或是矽酸鉿、矽酸鋁、矽酸鋯、其組合和其形成的多層，其他適合的材料包括La、Mg、Ba、Ti、Pb、Zr、以這些元素形成的金屬化物、金屬合金氧化物和其組合，示範的材料包括MgOx、BaTixOy、BaSrxTiyOz、PbTixOy、PbZrxTiyOz和相似物，形成的方法包括分子束沉積(molecular-beam deposition,MBD)、原子層沉積(atomic layer deposition,ALD)、物理氣相沉積(physical vapor deposition,PVD)和類似的方法。在一實施例中，閘介電層422可能具有約10Å至約50Å的厚度。
第5圖係根據一些實施例說明在閘介電層422之上形成導電層524，以下將討論更多細節，處理導電層524以提高其作為障蔽層的能力，以減少或預防進一步在下層中的氧化或氧化物重新生成，下層像是下層閘介電層422，發現在連續的處理步驟中可能發生氧化物重新生成，連續的處理步驟像是由於氧氣穿過高介電係數介電層的退火，以下將討論更多細節，將處理導電層524，沿著導電層524和閘介電層422之間的介面增加導電層524中的相對氮濃度。
在一些實施例中，導電層524可由鈦或鉭或是 含有鈦、鉭的材料形成，例如：TiN、TaC、TaN、TaAlN、TaSiN和其組合，這些含有金屬的材料可能有如下形式：氮化金屬、碳化金屬或導電金屬氧化物，舉例來說，在一些實施例中，導電層524由TiN形成，具有約10Å至約100Å的厚度，導電層524的形成方法包括ALD、PVD、有機金屬化學氣相沉積(metal-organic chemical vapor deposition,MOCVD)和相似的方法。
之後，進行處理以增加在連續處理步驟中導電層524阻擋氧氣穿過的能力，在一些實施例中，處理為在退火處理後的去耦合電漿氮化(decoupled plasma nitridation,DPN)處理，可能以含氮處理氣體(nitrogen-containing process gas)進行DPN，含氮處理氣體像是：N2,NH3或相似物，舉例來說，可能在約800℃至約1,000℃的溫度下和約1毫秒至約50秒的時間下進行退火。
如以上處理的結果，導電層524可能為梯度層。舉例來說，在一實施例中，導電層524為TixNy層，相較於遠離導電層524和閘介電層422之間的界面的某位置的TiN層，靠近導電層524和閘介電層422之間的介面的TiN層具有更高的相對氮濃度。在一些實施例中，在TiN層和閘介電層422之間的界面，具有約1.0至約1.2的y：x的比例，且在遠離TiN層和閘介電層422之間的界面的某位置，具有約0.85至約0.98的y：x的比例，在連續的流程處理步驟中，更高的比例提供更有效的的抵抗氧氣穿過的保護。
現在參考第6圖係根據一些實施例表示在導電層524之上形成閘極626，為了說明，第6圖說明閘極626包括單層。在一些實施例中，閘極626包括一或更多的金屬層或其他導電層，舉例來說，在一些實施例中，閘極626可能包括一或更多層由以下材質組成：鈦、鈷、鎢、鎢合金、鋁、鋁合金、銅、銅合金和/或其相似物，其中各種層可能為相似或不同的材料，形成閘極626的方法包括ALD、PVD、CVD、MOCVD和相似的方法。
以上的敘述為一般性的描述，提供一些對於實施例的理解和來龍去脈，其他實施例可能包括其他層和/或其他步驟，舉例來說，在一些實施例中，可能包括功金屬函數層，一般來說，可能調整閘極的功函數以適應矽的能帶(band-edge)，N型金屬氧化物半導體(NMOS)裝置可調整功函數接近導帶，P型金屬氧化物半導體(PMOS)裝置可調整功函數接近價帶。
如其他範例，在一些實施例中，可能形成矽上蓋(Si-cap)，可能在過程中進行上蓋後退火(post-capping anneal,PCA)處理以幫助減少氧氣穿透的問題。一般來說，可能形成非晶矽上蓋層以下層限制氧氣穿透的問題。在一些實施例中，在進行以上處理後，在導電層524之上形成非晶矽上蓋層，PCA處理包括退火以增強矽上蓋層防止氧氣穿過的能力。
此處揭露的這些實施例在閘介電質上提供更好的控制。舉例來說，在連續的處理步驟中，使用沒有氮化處 理的介面層和/或高介電係數介電層的裝置可能會歷經氧化物重新生成的問題，連續的處理步驟例如：退火，可能允許氧氣穿過上覆層和在介面層和/或高介電係數介電層中導致氧化物重新生成。
藉由在高介電係數介電層之上形成導電層(例如：TiN層)和進行處理，形成障蔽層以減少或是預防氧氣從介面層和/或高介電係數介電層穿過，沿著介電的氮濃度越高可以越有效的減少預防氧化物重新生成的問題。
之後，可進行一些額外的步驟以完成製程。舉例來說，可能形成額外的ILD層和接觸，可能形成金屬化層以使各種裝置互連形成電路、可能形成外部接觸和可能進行其他後端製程(back-end of line,BEOL)。
為了說明，以上討論的實施例說明使用後閘極方法，為了說明，第7-11圖說明使用先閘極方法的實施例，在接下來的討論中，類似的數字指稱類似的元件，因此類似的元件可能用以上所數述的相同的處理或是材料形成，將不會進一步討論，可能使用其它材料或是處理。
首先參考第7圖，表示基板102具有在其上形成的界面層420，和在界面層420之上形成閘介電層422，在第7圖中說明的實施例，介面層420和閘介電層422為在基板102的表面之上形成的一些層，在連續的處理步驟期間，界面層420和閘介電層422會被圖案化。
第8圖係根據一些實施例說明在閘介電層422之上，導電層524的形成，可能如上述討論處理導電層524 以沿著導電層524和閘介電層422之間的界面增加導電層524的氮濃度。
之後，如第9圖的說明，形成閘極層626，說明閘極層626為單層。在一些實施例中，閘極層626可能包括多層，例如：一些金屬層、多晶矽層和相似物，和可能包括功函數層。
第10圖說明界面層420、閘介電層422、導電層524的圖案化和以閘極層626形成閘極堆疊1010，如第10圖所示，可能以下列方式圖案化這些層，舉例來說，使用光刻技術形成圖案化的光罩(未示出)，和一或更多蝕刻處理，例如溼蝕刻或是乾蝕刻處理以圖案化界面層420、閘介電層422、導電層524和閘介電層626以形成閘極堆疊1010。
之後，可能如第11圖所說明，可能形成LDD區106、閘極間隙壁108、高摻雜源/極區110、矽化區112。第11圖進一步說明一或更多上覆的ILD層214。
之後，可進行一些額外的處理以完成製程。舉例來說，可能形成一些接觸延伸通過ILD層214，可能形成金屬化層以使各種裝置互連形成電路、可能形成外部接觸和可能進行其他後端製程。
第12圖係根據一些實施例說明描述進行製作半導體裝置的步驟的流程圖。從步驟1202開始，其中提供基板。在一些實施例中，基板具有一層在其上形成的ILD層，和形成虛擬閘極堆疊延伸通過ILD層，參考第1圖和第2圖，和以上的討論相似，移除虛擬閘極堆疊，由此在ILD層 中形成開口，參考第3圖，和以上的討論相似。
之後，在步驟1204中，在基板上形成界面層，和在界面層上形成高介電係數介電層，參考第4圖和/或第7圖和以上的討論相似，在步驟1206中，在高介電係數介電層之上形成導電層，導電層例如TiN層，在步驟1208中，進行一處理，參考第5圖和/或第8圖，和以上的討論相似，此處理係減少或預防氧氣穿過導電層，因此以介電層和/或高介電係數介電層減少或預防氧化物重新生成的問題。之後，在步驟1210中，在導電層之上形成閘極，參考第6圖和/或第9圖，和以上的討論相似。
在一實施例中，提供一種形成半導體裝置的方法，此方法包括形成一界面層和形成一介電層在此界面層之上，形成一導電層在此介電層之上，以及在此導電層之上執行一處理以增加此導電層的一阻氧能力。在一實施例中，此處理為一氮化處理。
在另一實施例中，提供一種形成半導體裝置的方法，此方法包括提供一基板和形成一閘介電層在此基板之上，形成一障蔽層在此閘介電層之上以及沿著此障蔽層和此閘介電層之間的一界面，在此障蔽層中增加一氮濃度。
在又一實施例中，提供一種半導體裝置包括一基板具有一閘介電層在此基板之上，一導電層在此閘介電層之上以及一閘極在此導電層之上，相較於遠離此閘介電層和此導電層之間的一界面的一第一位置，此導電層在沿著此閘介電層和此導電層之間的此界面上具有一更高的相對氮濃 度。
前述概要了幾個實施例的特徵，使得該領域之習知技藝者更加瞭解本案發明的方面，為了實行與本文所介紹的實施例一樣的目的和達到相同的優點，該領域之習知技藝者應該瞭解他們可以利用本案發明作為基礎用以設計或修飾其他處理和結構，該領域之習知技藝者也應該瞭解相等的建造並不會背離本案發明的精神和範圍，且他們可以在不背離本案發明的精神和範圍進行各種改變、替代和交替。
102‧‧‧基板
106‧‧‧微摻雜源/汲極區
108‧‧‧閘極間隙壁
110‧‧‧高摻雜源/極區
112‧‧‧矽化區
214‧‧‧層間介電層
420‧‧‧介面層
422‧‧‧閘介電層
524‧‧‧導電層

Claims (10)

  1. 一種形成一半導體裝置之方法，包括：形成一界面層；形成一介電層在該界面層之上；形成一導電層在該介電層之上，該導電層包含一氮化金屬，該導電層與該介電層之間具有一界面；以及處理該導電層，使該導電層內靠近該界面處的一第一氮濃度高於遠離該界面處的一第二氮濃度。
  2. 如請求項1所述之方法，其中該處理為一氮化處理。
  3. 如請求項1所述之方法，其中該處理包括沿著該導電層和該介電層之間的一界面增加該導電層的一氮濃度。
  4. 如請求項1所述之方法，其中形成該導電層包括形成一TiN層。
  5. 如請求項4所述之方法，其中該處理係沿著該導電層和該介電層之間的一界面形成一TixNy層，y：x的比例為約1.0至約1.2。
  6. 一種形成一半導體裝置之方法，包括：提供一基板； 形成一閘介電層在該基板之上；形成一障蔽層在該閘介電層之上；以及沿著該障蔽層和該閘介電層之間的一界面，在該障蔽層中增加一氮濃度，使該障蔽層內靠近該界面處的一第一氮濃度高於遠離該界面處的一第二氮濃度。
  7. 如請求項6所述之方法，至少一部分的該增加係藉由一去耦合電漿氮化(decoupled plasma nitridation,DPN)處理進行。
  8. 如請求項6所述之方法，其中該形成該障蔽層包括形成一TixNy層，在增加該氮濃度後，y：x為約1.0至約1.2。
  9. 如請求項6所述之方法，在形成該閘介電層之前，進一步包括：形成一虛擬閘極堆疊；形成共面的一介電層、該介電層的一上表面和該虛擬閘極堆疊的一上表面；以及移除該虛擬閘極堆疊。
  10. 一種半導體裝置，包括：一基板；一閘介電層在該基板之上；一導電層在該閘介電層之上；以及 一閘極在該導電層之上，相較於遠離該閘介電層和該導電層之間的一界面的一第一位置，該導電層在沿著該閘介電層和該導電層之間的該界面上具有一更高的相對氮濃度。
TW103145766A 2014-03-31 2014-12-26 半導體裝置及其製作方法 TWI556447B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/231,190 US9508548B2 (en) 2014-03-31 2014-03-31 Method for forming barrier layer for dielectric layers in semiconductor devices

Publications (2)

Publication Number Publication Date
TW201537752A TW201537752A (zh) 2015-10-01
TWI556447B true TWI556447B (zh) 2016-11-01

Family

ID=54191519

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103145766A TWI556447B (zh) 2014-03-31 2014-12-26 半導體裝置及其製作方法

Country Status (2)

Country Link
US (2) US9508548B2 (zh)
TW (1) TWI556447B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9508548B2 (en) 2014-03-31 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming barrier layer for dielectric layers in semiconductor devices
US9722038B2 (en) * 2015-09-11 2017-08-01 International Business Machines Corporation Metal cap protection layer for gate and contact metallization
US10008386B2 (en) 2016-09-12 2018-06-26 International Business Machines Corporation Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device
US11329136B2 (en) 2018-06-01 2022-05-10 International Business Machines Corporation Enabling anneal for reliability improvement and multi-Vt with interfacial layer regrowth suppression

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100120245A1 (en) * 2008-11-07 2010-05-13 Agus Sofian Tjandra Plasma and thermal anneal treatment to improve oxidation resistance of metal-containing films
US20110230042A1 (en) * 2010-03-16 2011-09-22 Taiwan Semiconductor Menufacturing Company, Ltd. Method for improving thermal stability of metal gate

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566205B1 (en) * 2002-01-11 2003-05-20 Taiwan Semiconductor Manufacturing Company Method to neutralize fixed charges in high K dielectric
US7256498B2 (en) * 2004-03-23 2007-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Resistance-reduced semiconductor device and methods for fabricating the same
WO2006071363A2 (en) * 2004-11-08 2006-07-06 Brewer Science Inc. Device for coating the outer edge of a substrate during microelectronics manufacturing
US7564108B2 (en) * 2004-12-20 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Nitrogen treatment to improve high-k gate dielectrics
CN103855006A (zh) * 2012-11-30 2014-06-11 中国科学院微电子研究所 半导体器件的制造方法
US8877625B1 (en) * 2013-05-14 2014-11-04 Globalfoundries Inc. Methods of forming semiconductor devices with different insulation thickness on the same semiconductor substrate and the resulting devices
US9105720B2 (en) * 2013-09-11 2015-08-11 United Microelectronics Corp. Semiconductor device having metal gate and manufacturing method thereof
US9508548B2 (en) 2014-03-31 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming barrier layer for dielectric layers in semiconductor devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100120245A1 (en) * 2008-11-07 2010-05-13 Agus Sofian Tjandra Plasma and thermal anneal treatment to improve oxidation resistance of metal-containing films
US20110230042A1 (en) * 2010-03-16 2011-09-22 Taiwan Semiconductor Menufacturing Company, Ltd. Method for improving thermal stability of metal gate

Also Published As

Publication number Publication date
US10453933B2 (en) 2019-10-22
TW201537752A (zh) 2015-10-01
US20170047420A1 (en) 2017-02-16
US20150279954A1 (en) 2015-10-01
US9508548B2 (en) 2016-11-29

Similar Documents

Publication Publication Date Title
US10978350B2 (en) Structure and method for metal gates with roughened barrier layer
US20210280473A1 (en) Methods of Cutting Metal Gates and Structures Formed Thereof
CN111987096B (zh) 半导体器件的栅极结构及其形成方法
US20220130730A1 (en) Semiconductor Device and Method
US9543399B2 (en) Device having sloped gate profile and method of manufacture
TWI556447B (zh) 半導體裝置及其製作方法
US20180337248A1 (en) High-K Dielectric and Method of Manufacture
TWI804594B (zh) 半導體結構及其形成方法
CN105990405B (zh) 半导体结构及其制造方法
US9543203B1 (en) Method of fabricating a semiconductor structure with a self-aligned contact
US9349726B2 (en) Semiconductor device fabrication method and structure
US8598033B1 (en) Method for forming a salicide layer
JP2008103613A (ja) 半導体装置及びその製造方法
CN220510045U (zh) 半导体装置
US20220336584A1 (en) Nanosheet field-effect transistor device and method of forming
TWI625856B (zh) 半導體裝置結構及其製造方法
TW202414835A (zh) 半導體裝置、其製造方法及在金屬閘極結構的上方形成連續的金屬蓋的方法
CN114649266A (zh) 半导体器件中的栅极接触结构和栅极过孔结构