TWI553751B - Method for cleaning molding flash of semiconductor package - Google Patents

Method for cleaning molding flash of semiconductor package Download PDF

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TWI553751B
TWI553751B TW104115616A TW104115616A TWI553751B TW I553751 B TWI553751 B TW I553751B TW 104115616 A TW104115616 A TW 104115616A TW 104115616 A TW104115616 A TW 104115616A TW I553751 B TWI553751 B TW I553751B
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pin
wafer
wafer holder
package
image
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TW104115616A
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TW201640591A (en
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蔡宜興
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蔡宜興
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封裝晶片之除膠方法 Decapsulation method for packaged wafer

本發明係關於一種封裝晶片之除膠方法,特別是關於一種用於四方平面引腳封裝晶片之除膠方法。 BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of removing a packaged wafer, and more particularly to a method for removing a package for a tetragonal planar lead package wafer.

在現有的技術中,QFN(quad flat no-lead)的晶片封裝製程首先係於一基板(導線架條)上製作多個導線架單元,其各包含一晶片承座及多排引腳;接著,將一半導體晶片經由黏晶(die attach)步驟固定在晶片承座之上表面上,晶片及各引腳之間係透過焊線(wire bond)或者預先成型之電連接元件(如覆晶凸塊)以形成電性連接;再於該基板之下表面上貼附一層阻隔膜;接著,以一對上、下模具夾持該基板,利用塑料注模將呈熔融狀態之封裝膠體原料注入至該模具之模穴中,以包覆位於該基板上表面側的晶片、焊線及引腳,待其冷卻成形後即形成半導體封裝構造的基本封裝輪廓;最後,卸除該阻隔膜以完成該晶片封裝製程之封膠(molding)程序;後續,並可進行切割,以成為多個QFN封裝體。 In the prior art, a QFN (quad flat no-lead) chip packaging process is first performed on a substrate (a lead frame strip) to form a plurality of lead frame units, each of which includes a wafer holder and a plurality of rows of pins; A semiconductor wafer is fixed on the upper surface of the wafer holder via a die attach step, and a wire bond or a pre-formed electrical connection component (such as a flip chip) is interposed between the wafer and each of the leads. Blocking) to form an electrical connection; attaching a barrier film on the lower surface of the substrate; then, holding the substrate with a pair of upper and lower molds, and injecting the molten colloidal material into the molten state by plastic injection molding The mold cavity of the mold covers the wafer, the bonding wire and the pin on the upper surface side of the substrate, and forms a basic package outline of the semiconductor package structure after being cooled and formed; finally, the barrier film is removed to complete the The molding process of the wafer packaging process; subsequent, and can be cut to become a plurality of QFN packages.

然而,在現有封裝膠體成形的過程中,容易發生溢膠(molding flash)缺陷,亦即部份流動的膠體意外進入阻隔膜與晶片承座(或引腳)下表面之間,因此在封膠程序後產生不當覆蓋該晶片承座或引腳下表面 之多餘殘膠毛邊,致使晶片承座或引腳無法完整暴露其下表面,進而產生散熱或電性接觸不良的情形,間接造成該晶片封裝後之良率下滑。 However, in the process of forming the existing package colloid, it is easy to cause a melting flash defect, that is, a part of the flowing colloid accidentally enters between the barrier film and the lower surface of the wafer holder (or the lead), so Improper coverage of the wafer holder or pin lower surface after the program Excessive residual rubber burrs, such that the wafer holder or pins can not completely expose the lower surface, resulting in heat dissipation or poor electrical contact, indirectly causing the yield of the wafer after packaging to decline.

鑑於上述的缺點,申請人係設計發明申請案第201513236號的一種封裝晶片之除膠方法,藉由一運算單元對一基板之影像執行影像分析運算並與樣板比對,以偵測基板之晶片承座及引腳部因溢膠而被殘膠覆蓋的部分,接著利用一雷射產生器之雷射軌跡來燒蝕去除殘膠,以避免晶片之引腳部發生電性接觸不良的情形。 In view of the above-mentioned shortcomings, the applicant is in the method of removing the glue of the packaged wafer of the application of the invention No. 201513236, by performing an image analysis operation on the image of a substrate by an arithmetic unit and comparing with the template to detect the wafer of the substrate. The portion of the socket and the lead portion that is covered by the residual glue due to the overflow of the glue, and then the laser trace of a laser generator is used to ablate and remove the residual glue to avoid the electrical contact failure of the lead portion of the wafer.

然而,由於在執行影像分析運算時,晶片承座及引腳部與樣版同步進行比對將較容易因晶片承座及引腳部在配置時所產生的位置誤差而影響比對的結果精準度,因而無法精準辨識被殘膠覆蓋的部分;再者,每個導線架單元係由多個衝壓或蝕刻穿孔所定義而成,該導線架與樣板比對時也容易因導線孔的形狀較小及排列密集而無法有效辨識被殘膠覆蓋的部分。 However, when the image analysis operation is performed, the wafer holder and the lead portion are synchronously compared with the pattern, which is more likely to be affected by the position error caused by the wafer holder and the lead portion during the configuration. Degree, thus it is impossible to accurately identify the part covered by the residual glue; further, each lead frame unit is defined by a plurality of stamping or etching perforations, and the lead frame is also easier to be compared with the shape of the lead hole due to the shape of the lead hole. Small and densely arranged to effectively identify the part covered by the residual glue.

故,有必要提供一種改良之封裝晶片之除膠方法,以解決習用技術所存在的問題。 Therefore, it is necessary to provide an improved method of removing the packaged wafer to solve the problems of the conventional technology.

本發明之主要目的在於提供一種封裝晶片之除膠方法,藉由二階段分別對封裝區塊內之晶片承座及引腳部之引腳進行位置定位及除膠比對,可有效提高除膠的精確性。 The main purpose of the present invention is to provide a method for removing a packaged wafer, which can effectively improve the removal of glue by separately positioning and removing the glue pins of the wafer holder and the lead portion in the package block in two stages. The accuracy.

為達上述之目的,本發明提供一種封裝晶片之除膠方法,包含一拍攝步驟、一晶片承座定位步驟、一晶片承座殘膠偵測步驟、一引腳部定位步驟、一引腳部殘膠偵測步驟及一除膠步驟;該拍攝步驟係利用一 顯微攝影裝置拍攝而取得一晶片封裝後之導線架基板之一基板影像,其中該基板影像包含彼此相鄰排列的多個封裝區塊,每一封裝區塊具有一晶片承座、多排引腳部及一膠體部,該等引腳部分別圍繞在該晶片承座外,且每排引腳部具有多個引腳,該膠體部填滿在該等引腳部及該晶片承座的上表面及兩者之間;該晶片承座定位步驟係利用一運算單元載入該基板影像,並執行影像分析定位該等封裝區塊內之晶片承座的位置;該晶片承座殘膠偵測步驟係利用該運算單元將該等封裝區塊之晶片承座與一晶片承座樣本影像進行比對,以偵測覆蓋在該等封裝區塊之晶片承座上的殘膠;該引腳部定位步驟係利用該運算單元執行影像分析定位該等封裝區塊內之引腳部的位置;該引腳部殘膠偵測步驟係利用該運算單元將每排引腳部的引腳與至少一引腳樣本影像進行比對,以偵測覆蓋在該等引腳部之引腳上的殘膠;該除膠步驟係利用一雷射產生器去除該等封裝區塊之晶片承座以及該等引腳部之引腳上的殘膠。 In order to achieve the above object, the present invention provides a method for removing a packaged wafer, comprising a photographing step, a wafer holder positioning step, a wafer holder residue detecting step, a pin portion positioning step, and a lead portion. Residue detection step and a de-glue step; the shooting step utilizes a The photomicrograph device captures a substrate image of a lead frame substrate after the chip is packaged, wherein the substrate image comprises a plurality of package blocks arranged adjacent to each other, each package block having a wafer holder and a plurality of rows of leads a leg portion and a gel portion, the pin portions respectively surrounding the wafer holder, and each of the lead portions has a plurality of pins, and the glue portion fills the pin portions and the wafer holder The upper surface and the two; the wafer bearing positioning step uses an arithmetic unit to load the substrate image, and performs image analysis to locate the position of the wafer holder in the package block; the wafer bearing residual glue detection The measuring step uses the computing unit to compare the wafer holders of the package blocks with a wafer holder sample image to detect residual glue covering the wafer holders of the package blocks; The positioning step is performed by the computing unit to perform image analysis to locate the position of the pin portion in the package block; the pin portion residual glue detecting step uses the operation unit to pin each pin of each row with at least One pin sample image ratio To detect residual glue covering the pins of the pin portions; the de-glue step uses a laser generator to remove the wafer holders of the package blocks and the pins of the pin portions Residual glue.

在本發明之一實施例中,在該晶片承座定位步驟中,該運算單元執行影像分析係將該基板影像的多個定位部與一定位部樣本影像進行比對,以定位該等封裝區塊內之晶片承座的位置。 In an embodiment of the present invention, the computing unit performs image analysis by comparing the plurality of positioning portions of the substrate image with a positioning portion sample image to locate the packaging regions. The location of the wafer holder within the block.

在本發明之一實施例中,在該晶片承座殘膠偵測步驟中,該等封裝區塊之晶片承座與該晶片承座樣本影像係利用本身的像素值進行比對,以偵測覆蓋在該等封裝區塊之晶片承座上的殘膠。 In an embodiment of the present invention, in the process of detecting the residual adhesive of the wafer, the wafer holder of the package block and the sample image of the wafer holder are compared by using pixel values of the wafer holder to detect Residual glue covering the wafer holders of the package blocks.

在本發明之一實施例中,在該引腳部定位步驟中,係利用該運算單元執行影像分析定位該等封裝區塊之晶片承座的四個邊長的位置,進而運算出該等封裝區塊之引腳部的位置。 In an embodiment of the present invention, in the pin portion positioning step, the operation unit performs image analysis to locate the positions of the four side lengths of the wafer holders of the package blocks, and then calculates the packages. The position of the pin portion of the block.

在本發明之一實施例中,在該引腳部定位步驟中,該等封裝區塊之晶片承座的四個邊長的位置定位之後,再依照該等邊長分別推算該晶片承座外圍的四個矩形區域,每一矩形區域劃分成多個區段,每一排引腳部的多個引腳分別對位於相應的區段中,進而運算出該等封裝區塊內之引腳部之引腳的位置。 In an embodiment of the present invention, in the pin portion positioning step, after the positions of the four side lengths of the wafer holders of the package blocks are positioned, the wafer holder periphery is separately estimated according to the side lengths. Four rectangular regions, each rectangular region is divided into a plurality of segments, and a plurality of pins of each row of pin portions are respectively located in corresponding segments, thereby calculating a pin portion in the package blocks The position of the pin.

在本發明之一實施例中,在該除膠步驟中,該雷射產生器係依據對位於相應引腳位置之區段的一中心,進行雷射燒蝕而去除覆蓋在該引腳上的殘膠。 In an embodiment of the present invention, in the step of removing the glue, the laser generator performs laser ablation according to a center of the section at the corresponding pin position to remove the cover on the pin. Residue.

在本發明之一實施例中,在該引腳部殘膠偵測步驟中,該等封裝區塊之引腳部的引腳與該引腳樣本影像係利用本身的像素值進行比對,以偵測覆蓋在該等引腳部之引腳上的殘膠。 In an embodiment of the present invention, in the step of detecting the residual portion of the lead portion, the pin of the pin portion of the package block is compared with the sample image of the pin by using the pixel value of the pin. Detecting residual glue covering the pins of the pins.

在本發明之一實施例中,在該引腳部殘膠偵測步驟中,該等封裝區塊之四排引腳部的引腳分別對應於不同方位的四種引腳樣本影像而進行像素值進行比對。 In an embodiment of the present invention, in the step of detecting the residual portion of the lead portion, the pins of the four rows of the pin portions of the package blocks respectively correspond to the image of the four pin samples in different orientations for pixel The values are compared.

在本發明之一實施例中,在該拍攝步驟後,更包含一自動調光步驟,利用偵測該基板影像的色階,以調整該顯微攝影裝置之一光源的強度。 In an embodiment of the invention, after the photographing step, an automatic dimming step is further included to detect the intensity of the light source of the photomicrography device by detecting the color gradation of the substrate image.

在本發明之一實施例中,在該拍攝步驟之前,更包含一預存步驟,將該晶片承座樣本影像及引腳樣本影像儲存在該運算單元中。 In an embodiment of the present invention, before the photographing step, a pre-stored step is further included, and the wafer holder sample image and the pin sample image are stored in the operation unit.

如上所述,本發明藉由所獲得的基板影像以二階段分別對該等封裝區塊內之晶片承座及引腳部之引腳進行位置定位,可有效提高其位置定位的精確性;同時,利用該晶片承座樣本影像及引腳樣本影像分別與 晶片承座及引腳進行像素值比對,也能夠有效辨識被殘膠覆蓋的部分,進而提高對該封裝晶片進行除膠的效率。 As described above, the present invention can position the pins of the wafer holder and the lead portion of the package block in two stages by using the obtained substrate image, thereby effectively improving the accuracy of positional positioning; Using the wafer holder sample image and the pin sample image respectively Pixel value comparison between the wafer holder and the pin can also effectively identify the portion covered by the residual glue, thereby improving the efficiency of removing the packaged wafer.

S201‧‧‧預存步驟 S201‧‧‧ Pre-existing steps

S202‧‧‧拍攝步驟 S202‧‧‧Photographing steps

S203‧‧‧自動調光步驟 S203‧‧‧Automatic dimming step

S204‧‧‧晶片承座定位步驟 S204‧‧‧ wafer holder positioning step

S205‧‧‧晶片承座殘膠偵測步驟 S205‧‧‧ wafer holder residue detection step

S206‧‧‧引腳部定位步驟 S206‧‧‧Pin section positioning steps

S207‧‧‧引腳部殘膠偵測步驟 S207‧‧‧Pin section residual glue detection step

S208‧‧‧除膠步驟 S208‧‧‧Degumming step

100‧‧‧基板影像 100‧‧‧Substrate image

1‧‧‧封裝區塊 1‧‧‧Package block

11‧‧‧晶片承座 11‧‧‧ wafer holder

12‧‧‧引腳部 12‧‧‧Lead Department

121‧‧‧引腳 121‧‧‧ pin

13‧‧‧膠體部 13‧‧‧Colloid

14‧‧‧定位部 14‧‧‧ Positioning Department

15‧‧‧矩形區域 15‧‧‧Rectangular area

151‧‧‧區段 Section 151‧‧‧

21‧‧‧定位部樣本影像 21‧‧‧ Positioning sample image

22‧‧‧晶片承座樣本影像 22‧‧‧ wafer holder sample image

23‧‧‧引腳樣本影像 23‧‧‧ Pin sample image

第1圖是根據本發明一較佳實施例之封裝晶片之除膠方法的流程圖;第2圖是根據本發明一較佳實施例之封裝晶片之除膠方法之基板影像的示意圖;第3圖是根據本發明一較佳實施例之封裝晶片之除膠方法之定位部樣本影像的示意圖;第4圖是根據本發明一較佳實施例之封裝晶片之除膠方法之晶片承座樣本影像的示意圖;第5圖是根據本發明一較佳實施例之封裝晶片之除膠方法將每一矩形區域劃分成多個區段的示意圖;及第6圖是根據本發明一較佳實施例之封裝晶片之除膠方法之引腳樣本影像的示意圖。 1 is a flow chart of a method for removing a packaged wafer according to a preferred embodiment of the present invention; and FIG. 2 is a schematic view of a substrate image of a method for removing a packaged wafer according to a preferred embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 4 is a schematic view showing a sample image of a positioning portion of a method for removing a packaged wafer according to a preferred embodiment of the present invention; FIG. 4 is a view showing a sample of a wafer holder for a method for removing a packaged wafer according to a preferred embodiment of the present invention. 5 is a schematic diagram of dividing a rectangular region into a plurality of segments by a method of removing a packaged wafer according to a preferred embodiment of the present invention; and FIG. 6 is a view of a preferred embodiment of the present invention. Schematic diagram of the pin sample image of the decapsulation method of the packaged wafer.

為了讓本發明之上述及其他目的、特徵、優點能更明顯易懂,下文將特舉本發明較佳實施例,並配合所附圖式,作詳細說明如下。再者,本發明所提到的方向用語,例如上、下、頂、底、前、後、左、右、內、外、側面、周圍、中央、水平、橫向、垂直、縱向、軸向、徑向、最上層或最下層等,僅是參考附加圖式的方向。因此,使用的方向用語是用以說明及理解本發明,而非用以限制本發明。 The above and other objects, features and advantages of the present invention will become more <RTIgt; Furthermore, the directional terms mentioned in the present invention, such as upper, lower, top, bottom, front, rear, left, right, inner, outer, side, surrounding, central, horizontal, horizontal, vertical, longitudinal, axial, Radial, uppermost or lowermost, etc., only refer to the direction of the additional schema. Therefore, the directional terminology used is for the purpose of illustration and understanding of the invention.

請參照第1圖所示,本發明一較佳實施例之封裝晶片之除膠方法,係針對已知四方平面無引腳封裝(quad flat no-lead package,QFN package)製程所使用的基板進行除膠,其中該基板(導線架條)具有多個晶片承座及引腳部,多個半導體晶片係設置在相應的晶片承座上,且晶片承座及引腳部的上表面及兩者之間包覆一膠體,以達到絕緣的效果。該封裝晶片之除膠方法包含一預存步驟S201、一拍攝步驟S202、一自動調光步驟S203、一晶片承座定位步驟S204、一晶片承座殘膠偵測步驟S205、一引腳部定位步驟S206、一引腳部殘膠偵測步驟S207及一除膠步驟S208,本發明將於下文詳細說明各元件的細部構造、組裝關係及其運作原理。 Referring to FIG. 1 , a method for removing a packaged wafer according to a preferred embodiment of the present invention is performed on a substrate used in a known quad flat no-lead package (QFN package) process. The substrate (the lead frame strip) has a plurality of wafer holders and lead portions, and the plurality of semiconductor wafers are disposed on the corresponding wafer holders, and the upper surfaces of the wafer holders and the lead portions and both A colloid is coated between them to achieve an insulating effect. The method for removing the packaged wafer includes a pre-storing step S201, a photographing step S202, an automatic dimming step S203, a wafer holder positioning step S204, a wafer holder residue detecting step S205, and a pin portion positioning step. S206, a lead portion residual glue detecting step S207 and a glue removing step S208, the detailed structure, assembly relationship and operation principle of each element will be described in detail below.

請參照第1圖所示,在該預存步驟S201中,先將一定位部樣本影像21(見第3圖)、一晶片承座樣本影像22(見第4圖)、多個引腳樣本影像23(見第6圖)及儲存在一運算單元(未繪示)中,其中該定位部樣本影像、晶片承座樣本影像22及該等引腳樣本影像23係經由軟體繪製之模板影像。 Referring to FIG. 1 , in the pre-storing step S201, a positioning portion sample image 21 (see FIG. 3 ), a wafer holder sample image 22 (see FIG. 4 ), and a plurality of pin sample images are first introduced. 23 (see FIG. 6) and stored in an arithmetic unit (not shown), wherein the positioning portion sample image, the wafer holder sample image 22, and the pin sample images 23 are template images drawn by software.

請參照第1、2圖所示,在該拍攝步驟S202中,係利用一顯微攝影裝置(未繪示)拍攝而取得一半導體晶片經封裝後之導線架基板之下表面的一基板影像100,其中該基板影像100(即導線架基板之下表面)包含彼此相鄰排列的多個封裝區塊1,每一封裝區塊1具有一晶片承座11、多排引腳部12及一膠體部13,每一引腳部12圍繞在該晶片承座11外,且每排引腳部12具有多個引腳121,該膠體部13填滿在該等引腳部12及該晶片承座11的上表面及兩者之間。 Referring to FIGS. 1 and 2, in the photographing step S202, a substrate image 100 of a lower surface of the packaged lead frame substrate of the semiconductor wafer is obtained by using a microphotography device (not shown). The substrate image 100 (ie, the lower surface of the lead frame substrate) includes a plurality of package blocks 1 arranged adjacent to each other, each package block 1 having a wafer holder 11, a plurality of rows of pins 12, and a colloid Each of the lead portions 12 surrounds the wafer holder 11 and each of the lead portions 12 has a plurality of pins 121. The glue portion 13 fills the lead portions 12 and the wafer holder. The upper surface of 11 and between the two.

請參照第1、2圖所示,在該自動調光步驟S203中,利用偵測該基板影像100的色階,以調整該顯微攝影裝置之一光源的強度,並且再 對該導線架基板進行拍攝,以取得能夠符合色階的一預設值之基板影像100。 Referring to FIGS. 1 and 2, in the automatic dimming step S203, the color gradation of the substrate image 100 is detected to adjust the intensity of a light source of the photomicrography device, and then The lead frame substrate is photographed to obtain a substrate image 100 of a preset value that can conform to the color gradation.

請參照第1、2、3圖所示,在該晶片承座定位步驟S204中,係利用該運算單元載入該基板影像100,並執行影像分析定位該等封裝區塊1內之晶片承座11的位置;在本實施例中,該運算單元執行影像分析係將該基板影像100的多個定位部14與一定位部樣本影像21進行比對,藉由運算該等定位部14及晶片承座11的相對位置,而定位該等封裝區塊1內之晶片承座11的位置。 Referring to the first, second, and third figures, in the wafer carrier positioning step S204, the substrate image 100 is loaded by the computing unit, and image analysis is performed to locate the wafer holders in the package blocks 1. In the embodiment, the computing unit performs the image analysis system to compare the plurality of positioning portions 14 of the substrate image 100 with a positioning portion sample image 21, by calculating the positioning portion 14 and the wafer bearing The relative positions of the seats 11 position the positions of the wafer holders 11 within the package blocks 1.

請參照第1、2、4圖所示,在該晶片承座殘膠偵測步驟S205中,係利用該運算單元將該等封裝區塊1之晶片承座11與該晶片承座樣本影像22進行比對,以偵測覆蓋在該等封裝區塊1之晶片承座11的下表面上的殘膠;在本實施例中,該等封裝區塊1之晶片承座11與該晶片承座樣本影像22係利用本身的像素值進行比對,以偵測覆蓋在該等封裝區塊1之晶片承座11的下表面上的殘膠;例如,其中一晶片承座11的像素值與該晶片承座樣本影像22的像素值的差距大於一預設值,則表示該晶片承座11的下表面具有覆蓋許多殘膠。 Referring to FIGS. 1, 2, and 4, in the wafer carrier residue detecting step S205, the wafer holder 11 of the package block 1 and the wafer holder sample image 22 are used by the arithmetic unit. Aligning to detect residual glue covering the lower surface of the wafer holder 11 of the package block 1; in this embodiment, the wafer holder 11 of the package block 1 and the wafer holder The sample images 22 are aligned using their own pixel values to detect residual glue covering the lower surface of the wafer holder 11 of the package block 1; for example, the pixel value of one of the wafer holders 11 The difference in pixel values of the wafer holder sample image 22 is greater than a predetermined value, indicating that the lower surface of the wafer holder 11 has a plurality of residual glue.

請參照第1、2、5圖所示,在該引腳部定位步驟S206中,係利用該運算單元執行影像分析定位該等封裝區塊1內之引腳部12的位置;在本實施例中,係利用該運算單元執行影像分析定位該等封裝區塊1之晶片承座11的四個邊長的位置,再依照該等邊長分別推算該晶片承座11外圍的四個矩形區域15(第5圖僅繪示其一),其中每一矩形區域15劃分成多個區段 151,而每一排引腳部12的多個引腳121分別對位於相應的區段151中,進而運算出該等封裝區塊1內之引腳部12之引腳121的位置。 Referring to the first, second, and fifth figures, in the pin portion positioning step S206, the image unit is used to perform image analysis to locate the position of the lead portion 12 in the package block 1. In this embodiment, The operation unit performs image analysis to locate the positions of the four sides of the wafer holder 11 of the package block 1, and then calculates the four rectangular regions 15 around the wafer holder 11 according to the sides. (Fig. 5 shows only one of them), in which each rectangular area 15 is divided into a plurality of sections 151, and the plurality of pins 121 of each row of the pin portions 12 are respectively located in the corresponding segments 151, thereby calculating the positions of the pins 121 of the pin portions 12 in the package blocks 1.

請參照第1、2、6圖所示,在該引腳部殘膠偵測步驟S207中,係利用該運算單元將每排引腳部12的引腳121與至少一引腳樣本影像23進行比對,以偵測覆蓋在該等引腳部12之引腳121的下表面上的殘膠;在本實施例中,每一封裝區塊1之四排引腳部12的引腳121分別對應於不同方位的四種引腳樣本影像23(見第6圖)進行比對;例如,每一封裝區塊1之上排引腳部12的引腳121與第6圖上方的引腳樣本影像23進行比對;另外,該等封裝區塊1之引腳部12的引腳121與該引腳樣本影像23係利用本身的像素值進行比對,以偵測覆蓋在該等引腳部12之引腳121的下表面上的殘膠。 Referring to the first, second, and sixth figures, in the lead portion residual glue detecting step S207, the arithmetic unit is used to perform the pin 121 of each row of the pin portion 12 and the at least one pin sample image 23. Aligning to detect the residual glue covering the lower surface of the pin 121 of the pin portion 12; in this embodiment, the pins 121 of the four rows of the pin portions 12 of each package block 1 are respectively The four pin sample images 23 (see FIG. 6) corresponding to different orientations are compared; for example, the pin 121 of the upper pin portion 12 and the pin sample above the sixth figure of each package block 1 The image 23 is compared; in addition, the pin 121 of the pin portion 12 of the package block 1 and the pin sample image 23 are compared by their own pixel values to detect coverage on the pin portions. Residual glue on the lower surface of pin 121 of 12.

請參照第1、2圖所示,在該除膠步驟S208中,係利用一雷射產生器(未繪示)去除該等封裝區塊1之晶片承座11以及該等引腳部12之引腳121的下表面上的殘膠;在本實施例中,該雷射產生器係採用亞格雷射,且該雷射產生器所產生之雷射光束的功率及波長分別為16~24瓦特及851~1277奈米;該雷射產生器依據該晶片承座11的對邊運算獲得的一中心進行雷射燒蝕而去除覆蓋在該晶片承座11的下表面上的殘膠,以及依據對位於相應引腳121位置之區段151(見第5圖)的一中心,進行雷射燒蝕而去除覆蓋在該引腳121的下表面上的殘膠。 Referring to FIGS. 1 and 2, in the de-glue step S208, the wafer holder 11 of the package block 1 and the lead portions 12 are removed by a laser generator (not shown). Residual glue on the lower surface of the pin 121; in this embodiment, the laser generator uses a sub-Gray shot, and the laser beam generated by the laser generator has a power and a wavelength of 16 to 24 watts, respectively. And 851~1277 nm; the laser generator performs laser ablation according to a center obtained by the opposite side operation of the wafer holder 11 to remove the residual glue covering the lower surface of the wafer holder 11, and At a center of the section 151 (see FIG. 5) at the position of the corresponding pin 121, laser ablation is performed to remove the residual glue covering the lower surface of the lead 121.

依據上述的結構,首先,利用該顯微攝影裝置拍攝該導線架基板而獲得該基板影像100,再對該等封裝區塊1內之晶片承座11的位置進行定位,並且與該晶片承座樣本影像22進行比對,以偵測覆蓋在該等封裝區塊1之晶片承座11的下表面上的殘膠;接著,利用上述晶片承座11的位置 運算並定位該等封裝區塊1內之引腳部12之引腳121的位置,再與該引腳樣本影像23進行比對,以偵測覆蓋在該等引腳部12之引腳121的下表面上的殘膠;最後,利用該雷射產生器去除覆蓋在該晶片承座11及引腳121的下表面上的殘膠。 According to the above structure, first, the lead frame substrate is photographed by the photomicrography device to obtain the substrate image 100, and the position of the wafer holder 11 in the package block 1 is positioned, and the wafer holder is positioned. The sample images 22 are aligned to detect residual glue covering the lower surface of the wafer holder 11 of the package block 1; then, the position of the wafer holder 11 is utilized. The position of the pin 121 of the pin portion 12 in the package block 1 is calculated and located, and then compared with the pin sample image 23 to detect the pin 121 covering the pin portion 12. Residual glue on the lower surface; finally, the residual glue covering the lower surface of the wafer holder 11 and the lead 121 is removed by the laser generator.

藉由上述的設計,本發明藉由所獲得的基板影像100以二階段分別對該等封裝區塊1內之晶片承座11及引腳部12之引腳121進行位置定位,可有效提高其位置定位的精確性;同時,利用該晶片承座樣本影像22及引腳樣本影像23分別與晶片承座11及引腳121進行像素值比對,也能夠有效辨識被殘膠覆蓋的部分,進而提高對該封裝晶片進行除膠的效率。 With the above design, the present invention can effectively position the substrate holders 11 and the pins 121 of the lead portions 12 in the package blocks 1 in two stages by the obtained substrate image 100. The accuracy of the positional positioning; at the same time, the pixel bearing sample image 22 and the pin sample image 23 are respectively compared with the wafer holder 11 and the pin 121 for pixel value comparison, and the portion covered by the residual glue can be effectively recognized, and further Improve the efficiency of de-glueing the packaged wafer.

雖然本發明已以較佳實施例揭露,然其並非用以限制本發明,任何熟習此項技藝之人士,在不脫離本發明之精神和範圍內,當可作各種更動與修飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 The present invention has been disclosed in its preferred embodiments, and is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

S201‧‧‧預存步驟 S201‧‧‧ Pre-existing steps

S202‧‧‧拍攝步驟 S202‧‧‧Photographing steps

S203‧‧‧自動調光步驟 S203‧‧‧Automatic dimming step

S204‧‧‧晶片承座定位步驟 S204‧‧‧ wafer holder positioning step

S205‧‧‧晶片承座殘膠偵測步驟 S205‧‧‧ wafer holder residue detection step

S206‧‧‧引腳部定位步驟 S206‧‧‧Pin section positioning steps

S207‧‧‧引腳部殘膠偵測步驟 S207‧‧‧Pin section residual glue detection step

S208‧‧‧除膠步驟 S208‧‧‧Degumming step

Claims (10)

一種封裝晶片之除膠方法,包含:一拍攝步驟,利用一顯微攝影裝置拍攝而取得一晶片封裝後之導線架基板之一基板影像,其中該基板影像包含彼此相鄰排列的多個封裝區塊,每一封裝區塊具有:一晶片承座;多排引腳部,分別圍繞在該晶片承座外,且每排引腳部具有多個引腳;及一膠體部,填滿在該等引腳部及該晶片承座的上表面及兩者之間;一晶片承座定位步驟,利用一運算單元載入該基板影像,並執行影像分析定位該等封裝區塊內之晶片承座的位置;一晶片承座殘膠偵測步驟,利用該運算單元將該等封裝區塊之晶片承座與一晶片承座樣本影像進行比對,以偵測覆蓋在該等封裝區塊之晶片承座上的殘膠;一引腳部定位步驟,利用該運算單元執行影像分析定位該等封裝區塊內之引腳部的位置;一引腳部殘膠偵測步驟,利用該運算單元將每排引腳部的引腳與至少一引腳樣本影像進行比對,以偵測覆蓋在該等引腳部之引腳上的殘膠;及一除膠步驟,利用一雷射產生器去除該等封裝區塊之晶片承座以及該等引腳部之引腳上的殘膠。 A method for removing a packaged wafer, comprising: a photographing step of obtaining a substrate image of a lead frame substrate after a chip package by using a microphotography device, wherein the substrate image comprises a plurality of package regions arranged adjacent to each other Block, each package block has: a wafer holder; a plurality of rows of lead portions respectively surrounding the wafer holder, and each row of lead portions has a plurality of pins; and a colloid portion filled with the a lead portion and an upper surface of the wafer holder and between the two; a wafer holder positioning step of loading the substrate image by an arithmetic unit and performing image analysis to locate the wafer holder in the package block a wafer bearing residue detection step, wherein the wafer holder of the package block is compared with a wafer holder sample image by the operation unit to detect a wafer covering the package block Residual glue on the socket; a pin positioning step, the image unit is used to perform image analysis to locate the position of the pin portion in the package block; and a pin portion residual glue detecting step is performed by using the operation unit Each row of pins The pins are compared with at least one pin sample image to detect the residual glue covering the pins of the pin portions; and a de-glue step, using a laser generator to remove the package blocks The wafer holder and the residual glue on the pins of the pins. 如申請專利範圍第1項所述之封裝晶片之除膠方法,其中在該晶片承座定位步驟中,該運算單元執行影像分析係將該基板 影像的多個定位部與一定位部樣本影像進行比對,以定位該等封裝區塊內之晶片承座的位置。 The method for removing a packaged wafer according to claim 1, wherein in the wafer holder positioning step, the operation unit performs image analysis on the substrate The plurality of positioning portions of the image are compared with a positioning portion sample image to locate the position of the wafer holder in the packaging block. 如申請專利範圍第1項所述之封裝晶片之除膠方法,其中在該晶片承座殘膠偵測步驟中,該等封裝區塊之晶片承座與該晶片承座樣本影像係利用本身的像素值進行比對,以偵測覆蓋在該等封裝區塊之晶片承座上的殘膠。 The method for removing a packaged wafer according to the first aspect of the invention, wherein in the wafer carrier residue detecting step, the wafer holder of the package block and the wafer holder sample image utilize the same The pixel values are compared to detect residual glue covering the wafer holders of the package blocks. 如申請專利範圍第1項所述之封裝晶片之除膠方法,其中在該引腳部定位步驟中,係利用該運算單元執行影像分析定位該等封裝區塊之晶片承座的四個邊長的位置,進而運算出該等封裝區塊之引腳部的位置。 The method for removing a packaged wafer according to claim 1, wherein in the step of positioning the lead portion, the image unit is used to perform image analysis to locate four sides of the wafer holder of the package block. The position, and thus the position of the pin portion of the package block. 如申請專利範圍第4項所述之封裝晶片之除膠方法,其中在該引腳部定位步驟中,該等封裝區塊之晶片承座的四個邊長的位置定位之後,再依照該等邊長分別推算該晶片承座外圍的四個矩形區域,每一矩形區域劃分成多個區段,每一排引腳部的多個引腳分別對位於相應的區段中,進而運算出該等封裝區塊內之引腳部之引腳的位置。 The method for removing a packaged wafer according to claim 4, wherein in the pin portion positioning step, the positions of the four side lengths of the wafer holders of the package blocks are positioned, and then according to the The side lengths respectively calculate four rectangular regions on the periphery of the wafer holder, each rectangular region is divided into a plurality of segments, and the plurality of pins of each row of pin portions are respectively located in the corresponding segments, thereby calculating the The position of the pin of the pin portion in the package block. 如申請專利範圍第5項所述之封裝晶片之除膠方法,其中在該除膠步驟中,該雷射產生器係依據對位於相應引腳位置之區段的一中心,進行雷射燒蝕而去除覆蓋在該引腳上的殘膠。 The method of removing a packaged wafer according to claim 5, wherein in the step of removing the glue, the laser generator performs laser ablation according to a center of a section at a corresponding pin position. The residual glue covering the pin is removed. 如申請專利範圍第1項所述之封裝晶片之除膠方法,其中在該引腳部殘膠偵測步驟中,該等封裝區塊之引腳部的引腳與該 引腳樣本影像係利用本身的像素值進行比對,以偵測覆蓋在該等引腳部之引腳上的殘膠。 The method for removing a packaged wafer according to claim 1, wherein in the step of detecting the residual portion of the lead portion, the pin of the package portion of the package block is The pin sample image is compared using its own pixel values to detect the residual glue covering the pins of the pins. 如申請專利範圍第7項所述之封裝晶片之除膠方法,其中在該引腳部殘膠偵測步驟中,該等封裝區塊之四排引腳部的引腳分別對應於不同方位的四種引腳樣本影像而進行像素值進行比對。 The method for removing a packaged wafer according to claim 7, wherein in the step of detecting the residual portion of the lead portion, the pins of the four rows of the lead portions of the package block respectively correspond to different orientations. Four pin sample images are compared for pixel values. 如申請專利範圍第1項所述之封裝晶片之除膠方法,其中在該拍攝步驟後,更包含一自動調光步驟,利用偵測該基板影像的色階,以調整該顯微攝影裝置之一光源的強度。 The method for removing a packaged wafer according to claim 1, wherein after the photographing step, an automatic dimming step is further included, and the color gradation of the substrate image is detected to adjust the photomicrography device. The intensity of a light source. 如申請專利範圍第1項所述之封裝晶片之除膠方法,其中在該拍攝步驟之前,更包含一預存步驟,將該晶片承座樣本影像及引腳樣本影像儲存在該運算單元中。 The method for removing a packaged wafer according to claim 1, wherein before the photographing step, a pre-stored step is further included, and the wafer holder sample image and the pin sample image are stored in the operation unit.
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