TWI552210B - Metal-gate cmos device and fabrication method thereof - Google Patents

Description

Metal gate CMOS device and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a dual work-function metal-gate complementary metal oxide semiconductor (CMOS) transistor device and a method of fabricating the same.

As semiconductor components continue to shrink, work function metals have gradually replaced conventional polysilicon as control electrodes for matching high-k dielectric layers. At present, the manufacturing method of the double work function metal gate can be roughly divided into a gate-first process and a gate-last process, wherein the back gate process is also referred to as a "replacement metal gate". (Replacement Metal-Gate) or "RMG" process can avoid high-heat budget process such as source/bungee ultra-shallow junction activation tempering and metal telluride, and has a wide material selection, so it gradually replaces the front gate Extreme process.

The conventional back gate process first forms a polysilicon dummy gate or a replacement gate, and then sequentially completes a plurality of MOS transistor fabrication steps, for example, forming a first sidewall, LDD ion implantation after the first sidewall, buried epitaxial process of the drain/source, a second sidewall process of the tantalum nitride/yttria composite, ion implantation of the drain/source, etc., Then, the polysilicon dummy gate is removed to form a gate trench, and finally, different metals are filled in the gate trench according to electrical requirements.

Since the double work function metal gate needs to be matched with the NMOS component on the one hand, and the PMOS component on the other hand, the integration technology and process control of the related component are more complicated, and the thickness and composition control requirements of each material are also more complicated. Strict. In this rigorous process environment, how to integrate the PMOS/NMOS device process while fabricating the dual-function metal gate while achieving cost reduction and competing products is an important issue today.

Accordingly, the present invention provides a dual work function metal gate CMOS device and a fabrication method thereof, which integrates a buried SiGe/SiC process, which simplifies the complexity of the dual work function metal gate CMOS process and further reduces manufacturing costs.

According to a preferred embodiment of the present invention, the present invention provides a method for fabricating a dual work function metal gate CMOS device, comprising: providing a substrate including a first region and a second region; respectively in the first region And the second region forms a first dummy gate structure and a second dummy gate structure; respectively, the substrate on both sides of the first dummy gate structure and the second dummy gate structure Forming a first lightly doped drain and a second lightly doped drain in the substrate; forming a first sidewall on the first dummy gate structure and the second dummy gate structure respectively And a second sidewall; forming a first buried epitaxial layer in the substrate on both sides of the first dummy gate structure; forming a layer in the first region; and forming the cap layer, A second buried epitaxial layer is formed in the substrate on both sides of the second dummy gate structure.

After forming the second buried epitaxial layer, a first contact hole etch stop layer is continuously deposited on the substrate to cover the first region and the second region; and the first contact hole is etched on the stop layer Forming a first dielectric layer; performing a chemical mechanical polishing process to polish a portion of the thickness of the first dielectric layer and the first contact hole etch stop layer until the first dummy gate structure is exposed and The second dummy gate structure; the first dummy gate structure and the second dummy gate structure are removed to form a first gate trench and a second gate trench respectively; and the first gate A first gate dielectric layer and a first metal gate are formed in the drain trench, and a second gate dielectric layer and a second metal gate are formed in the second gate trench.

After forming the first metal gate and the second metal gate, continuing to deposit a second dielectric layer on the substrate; etching the first and second dielectric layers in the first region, the first Contacting the hole etch stop layer and the cap layer to form a first contact hole, etching the first and second dielectric layers in the second region and the first contact hole etch stop layer to form a second contact hole; Forming a deuterated metal layer at the bottom of the first and second contact holes; and filling the metal layer with the first and second contact holes to form a first contact plug and a second contact plug.

According to another preferred embodiment of the present invention, after the first metal gate and the second metal gate are formed, the first dielectric layer, the first contact hole etch stop layer and the sealing layer are continuously removed; Depositing a second contact hole etch stop layer having stress; forming a third dielectric layer on the second contact hole etch stop layer; etching the first portion in the first region The third dielectric layer and the second contact hole etch stop layer form a first contact hole, and the third dielectric layer and the second contact hole etch stop layer in the second region are etched to form a second contact hole Forming a deuterated metal layer at the bottom of the first and second contact holes; and filling the metal layer with the first and second contact holes to form a first contact plug and a second contact plug.

In another aspect, the present invention provides a metal gate CMOS device including: a substrate including a PMOS region and an NMOS region; a PMOS transistor disposed on the substrate in the PMOS region; and an NMOS transistor; Provided on the substrate in the NMOS region; a layer covering only the PMOS transistor in the PMOS region; and a contact hole etch stop layer covering the cap layer in the PMOS region and the NMOS region The NMOS transistor. The PMOS transistor includes a first metal gate and a first gate dielectric layer. The first gate dielectric layer comprises a metal oxide. The metal oxide comprises hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), aluminum oxide (aluminum oxide, Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO3), tantalum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ) Zirconium silicon oxide (ZrSiO ₄ ) or hafnium zirconium oxide (HfZrO ₂ ). The PMOS transistor further includes a buried SiGe epitaxial layer located in a drain/source region of the PMOS transistor. The cap layer directly contacts the buried SiGe epitaxial layer. The first metal gate comprises titanium nitride (TiN), aluminum nitride (AlN), tantalum nitride (TaN), aluminum (aluminum, Al) or a work function metal.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims. However, the following preferred embodiments and drawings are for illustrative purposes only and are not intended to limit the invention.

Please refer to FIG. 1 to FIG. 14 , which are schematic diagrams showing a method for fabricating a dual work function metal gate CMOS device according to a preferred embodiment of the present invention. First, as shown in FIG. 1, a substrate 10 is provided. For example, the substrate 10 may be a germanium substrate, a germanium-containing substrate, a blanket insulating (SOI) substrate, or an epitaxial substrate. A plurality of shallow trench isolations (STIs) 12 are formed in the substrate 10 to electrically isolate at least one PMOS region 101 and an NMOS region 102. Next, a dummy gate structure 21 and a dummy gate structure 22 are formed in the PMOS region 101 and the NMOS region 102 of the substrate 10, wherein the dummy gate structure 21 may include a gate germanium oxide dielectric layer. 21a, a polysilicon layer 21b, a cap layer 21c and a sidewall oxide layer 21d, and the dummy gate structure 22 may include a gate oxide dielectric layer 22a, a polysilicon layer 22b, a cap layer 22c, and a sidewall oxidation. Layer 22d. The cap layers 21c and 22c may be tantalum nitride. Next, after the dummy gate structures 21 and 22 are formed, the PMOS region 101 is covered with the patterned photoresist layer 30, and the opening 30a of the patterned photoresist layer 30 exposes the NMOS region 102, and then an ion implantation is performed. The process 130 forms a lightly doped drain (LDD) 220 in the substrate 10 on both sides of the dummy gate structure 22.

As shown in FIG. 2, after the ion implantation process 130, the patterned photoresist layer 30 is removed, and the NMOS region 102 is covered with another patterned photoresist layer 40, and the opening 40a of the photoresist layer 40 is patterned. Then, the PMOS region 101 is exposed, and then an ion implantation process 140 is performed to form a lightly doped gate (LDD) 210 in the substrate 10 on both sides of the dummy gate structure 21, and then the patterned photoresist layer 40 is removed. . Of course, those skilled in the art should be able to understand that the LDD ion implantation process in Figure 1 is interchangeable with the LDD ion implantation process in Figure 2.

As shown in FIG. 3, a sidewall sub-material layer 50 is deposited on the surface of the substrate 10 to cover the PMOS region 101 and the NMOS region 102. In accordance with a preferred embodiment of the present invention, the sidewall sub-material layer 50 may be a carbon doped tantalum nitride layer having a higher dielectric constant than tantalum nitride which is not doped with carbon. As shown in FIG. 4, the sidewall sub-material layer 50 is then etched by an anisotropic dry etching process such that sidewalls 51 and 52 are formed on the sidewalls of the dummy gate structures 21 and 22, respectively. It can be seen from this that one of the technical features of the present invention is that after forming the LDD, the gate sidewalls are formed.

Next, as shown in FIG. 5, a sacrificial tantalum nitride layer 54 is additionally deposited on the surface of the substrate 10 to cover the PMOS region 101 and the NMOS region 102. In accordance with a preferred embodiment of the present invention, the sacrificial tantalum nitride layer 54 can be an undoped tantalum nitride layer having a significant etch selectivity to the sidewall spacer material layer 50 described above. In other words, the etch rate of the sacrificial tantalum nitride layer 54 is significantly higher than the etch selectivity ratio of the sidewall sub-material layer 50.

As shown in FIG. 6, the NMOS region 102 is then covered with a patterned photoresist layer 60, and the opening 60a of the patterned photoresist layer 60 exposes the PMOS region 101. Next, an etching process is performed to automatically align the sigma-shaped grooves 71 on both sides of the dummy gate structure 21 in the PMOS region 101, and then the patterned photoresist layer 60 is removed. As shown in FIG. 7, a SiGe epitaxial process of the PMOS region 101 is then performed to form a buried SiGe epitaxial layer 81 in the recess 71. According to a preferred embodiment of the present invention, the aforementioned SiGe epitaxial process is in-situ P ⁺ doped to form a P ⁺ buried SiGe epitaxial layer 81, so that the subsequent PMOS drain/source can be omitted. Extreme ion implantation step and corresponding mask.

As shown in FIG. 8, an etching process is then performed to selectively remove the sacrificial tantalum nitride layer 54 remaining in the NMOS region 102. In other embodiments, this etching step can also be omitted. Then, a deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), is performed to deposit a SiN seal layer 56 on the surface of the substrate 10, the thickness of which is about Between 50 angstroms and 200 angstroms.

As shown in FIG. 9, the PMOS region 101 is then covered with a patterned photoresist layer 80, and the opening 80a of the patterned photoresist layer 80 exposes the NMOS region 102. Next, an etching process is performed to automatically align the sigma-shaped recesses 72 on both sides of the dummy gate structure 22 in the NMOS region 102, and then the patterned photoresist layer 80 is removed. As shown in FIG. 10, the SiC epitaxial process of the NMOS region 102 is then performed to form the buried SiC epitaxial layer 82 in the recess 72. According to a preferred embodiment of the present invention, the aforementioned SiC epitaxial process line for the synchronization N ⁺ doped (in-situ), an N ⁺ buried SiC epitaxial layer 82 may be omitted so that the subsequent drain of NMOS source / sources Extreme ion implantation step and corresponding mask. In addition, those skilled in the art should be able to understand that the buried SiGe epitaxial process in the PMOS region of FIGS. 6-7 can be interchanged with the buried SiC epitaxial process sequence of the NMOS region in FIGS. 9-10.

As shown in FIG. 11, a contact hole etch stop layer (CESL) 90, for example, a tantalum nitride layer, may be deposited over the surface of the substrate 10, which may have a thickness between 100 angstroms and 150 angstroms. In accordance with a preferred embodiment of the present invention, the contact hole etch stop layer 90 may be free of stress. Then, a dielectric layer 91, such as a germanium oxide layer or a low dielectric constant material layer, is deposited over the contact hole etch stop layer 90.

As shown in FIG. 12, a chemical mechanical polishing (CMP) process is performed to polish away a portion of the thickness of the dielectric layer 91, a portion of the thickness of the contact hole etch stop layer 90, and the cap layer of the dummy gate structure 21. 21c and the cap layer 22c of the dummy gate structure 22, such that the polysilicon layer 21b of the dummy gate structure 21 and the polysilicon layer 22b of the dummy gate structure 22 are exposed. Then, the dummy gate structure 21 (including the polysilicon layer 21b and the gate oxide dielectric layer 21a) and the dummy gate structure 22 (including the polysilicon layer 22b and the gate oxide dielectric layer 22a) are etched. Completely removed, the gate trench 321 and the gate trench 322 are formed, respectively exposing the channel region 121 of the PMOS transistor and the channel region 122 of the NMOS transistor.

As shown in FIG. 13, a high-k gate dielectric layer 421a and a metal gate 421b are formed in the gate trench 321 to form a high dielectric constant gate in the gate trench 322. Dielectric layer 422a and metal gate 422b. The high dielectric constant gate dielectric layers 421a and 422a may be selected from the group consisting of tantalum nitride (SiN), bismuth oxynitride (SiON), and metal oxides, wherein the metal oxide contains yttrium oxide ( Hafnium oxide, HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al ₂ O ₃ ), antimony oxide _{lanthanum oxide, La 2 O 3)} , lanthanum aluminate (lanthanum aluminum oxide, LaAlO3), tantalum oxide _{(tantalum oxide, Ta 2 O 5} ), zirconium oxide (zirconium oxide, ZrO _2), zirconium silicate oxide compound (zirconium silicon Oxide, ZrSiO ₄ ), or hafnium zirconium oxide (HfZrO ₂ ). The metal gates 421b and 422b may comprise titanium nitride, aluminum nitride, tantalum nitride, aluminum or a work function metal, and may be a single layer or a composite layer structure. The high dielectric constant gate dielectric layers 421a and 422a may be formed by chemical vapor deposition or atomic layer deposition, and the metal gates 421b and 422b may be formed by deposition, evaporation or sputtering, and finally removed by chemical mechanical polishing. The metal layer outside the gate trench 321 and the gate trench 322 is removed.

As shown in FIG. 14, after completing the high dielectric constant gate dielectric and high-k/metal gate process, a dielectric layer 92 is then deposited on the substrate 10, and then, The contact hole and contact plug process includes a dielectric layer 92, 91 in the dry etched PMOS region 101, a contact hole etch stop layer 90, and a tantalum nitride sealing layer 56, forming a contact hole 92a, exposing a portion of the PMOS transistor. The drain/source, the dielectric layers 92, 91 and the contact hole etch stop layer 90 in the NMOS region 102 are dry etched to form a contact hole 92b exposing the drain/source of the portion of the NMOS transistor. Then, a deuterated metal process is performed to form a deuterated metal layer 171 at the bottoms of the contact holes 92a and 92b, respectively. 172, for example, nickel telluride (NiSi) or NiPt. Finally, metal contact layers such as titanium (Ti), titanium nitride (TiN), and tungsten (W) are formed in the contact holes 92a and 92b, and the contact plugs 192a and 192b are formed. As can be seen from Fig. 14, one of the structural features of the present invention is that the PMOS region 101 is covered by the tantalum nitride sealing layer 56 and the contact hole etch stop layer 90, and the NMOS region 102 is only covered by the contact hole etch stop layer 90. That is, the tantalum nitride sealing layer 56 covers only the PMOS region 101.

15 to FIG. 16 are schematic diagrams showing a method of fabricating a dual work function metal gate CMOS device according to another preferred embodiment of the present invention, wherein FIG. 15 is a continuation of FIG. As shown in FIG. 15, after the metal gate process in FIG. 13 is completed, the dielectric layer 91, the contact hole etch stop layer 90, and the tantalum nitride sealing layer 56 are removed, and then another contact hole is etched to stop. Layer 93 and another dielectric layer 94, wherein the contact hole etch stop layer 93 has stress, such as tensile stress or compressive stress, to increase device performance.

Next, as shown in FIG. 16, the contact hole and contact plug process are performed, including dry etching the dielectric layer 94 in the PMOS region 101 and the contact hole etch stop layer 93 to form a contact hole 94a to expose the PMOS transistor. Part of the drain/source, the dielectric layer 94 in the NMOS region 102 and the contact hole etch stop layer 93 are dry etched to form a contact hole 94b exposing the drain/source of the portion of the NMOS transistor. Next, a deuterated metal process is performed to form deuterated metal layers 271 and 272, for example, nickel telluride, at the bottoms of the contact holes 94a and 94b, respectively. Finally, a metal adhesion layer, for example, tungsten, titanium, or titanium nitride, is formed in the contact holes 94a and 94b to form contact plugs 194a and 194b.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Base

12‧‧‧Shallow trench insulation

21‧‧‧Virtual gate structure

21a‧‧‧Gate Electrode Layer

21b‧‧‧Polysilicon layer

21c‧‧‧ cover

21d‧‧‧ sidewall oxide layer

22‧‧‧Virtual gate structure

22a‧‧‧ Gate Electrodeoxygen Dielectric Layer

22b‧‧‧Polysilicon layer

22c‧‧‧ cover

22d‧‧‧ sidewall oxide layer

30‧‧‧ patterned photoresist layer

30a‧‧‧ openings

40‧‧‧ patterned photoresist layer

40a‧‧‧ openings

50‧‧‧ Sidewall material layer

51‧‧‧ Sidewall

52‧‧‧ Sidewall

54‧‧‧ Sacrificial layer of tantalum nitride

56‧‧‧ nitride layer

60‧‧‧ patterned photoresist layer

60a‧‧‧ openings

71‧‧‧ Groove

72‧‧‧ Groove

80‧‧‧ patterned photoresist layer

80a‧‧‧ openings

81‧‧‧ Buried SiGe epitaxial layer

82‧‧‧Buided SiC epitaxial layer

90‧‧‧Contact hole etch stop layer

91‧‧‧ dielectric layer

92‧‧‧ dielectric layer

92a‧‧‧Contact hole

92b‧‧‧Contact hole

93‧‧‧Contact hole etch stop layer

94‧‧‧Dielectric layer

94a‧‧‧Contact hole

94b‧‧‧Contact hole

101‧‧‧ PMOS area

102‧‧‧NMOS area

121‧‧‧Channel area

122‧‧‧Channel area

130‧‧‧Ion implantation process

140‧‧‧Ion implantation process

171‧‧‧Chemical metal layer

172‧‧‧Deuterated metal layer

192a‧‧‧Contact plug

192b‧‧‧Contact plug

194a‧‧‧Contact plug

194b‧‧‧Contact plug

210‧‧‧Lightly doped bungee

220‧‧‧Lightly doped bungee

271‧‧‧Deuterated metal layer

272‧‧‧Deuterated metal layer

321‧‧‧The gate ditches

322‧‧‧The gate ditches

421a‧‧‧gate dielectric layer

421b‧‧‧Metal gate

422a‧‧‧gate dielectric layer

422b‧‧‧Metal gate

1 to 14 are schematic views showing a method of fabricating a dual work function metal gate CMOS device according to a preferred embodiment of the present invention.

15 to 16 are schematic views showing a method of fabricating a dual work function metal gate CMOS device according to another preferred embodiment of the present invention.

10‧‧‧Base

12‧‧‧Shallow trench insulation

51‧‧‧ Sidewall

52‧‧‧ Sidewall

56‧‧‧ nitride layer

81‧‧‧ Buried SiGe epitaxial layer

82‧‧‧Buided SiC epitaxial layer

90‧‧‧Contact hole etch stop layer

91‧‧‧ dielectric layer

92‧‧‧ dielectric layer

92a‧‧‧Contact hole

92b‧‧‧Contact hole

101‧‧‧ PMOS area

102‧‧‧NMOS area

171‧‧‧Chemical metal layer

172‧‧‧Deuterated metal layer

192a‧‧‧Contact plug

192b‧‧‧Contact plug

210‧‧‧Lightly doped bungee

220‧‧‧Lightly doped bungee

421a‧‧‧gate dielectric layer

421b‧‧‧Metal gate

422a‧‧‧gate dielectric layer

422b‧‧‧Metal gate

Claims (7)

A metal gate CMOS device includes: a substrate including a first conductivity type MOS region and a second conductivity type MOS region, wherein the first conductivity type MOS region is a PMOS region, and the second conductivity type MOS region is An NMOS region; a first conductivity type MOS transistor disposed on the substrate in the first conductivity type MOS region; and a second conductivity type MOS transistor disposed on the substrate in the second conductivity type MOS region a layer covering only the first conductive type MOS transistor in the first conductive type MOS region; and a contact hole etch stop layer covering the sealing layer in the first conductive type MOS region and the first layer The second conductivity type MOS transistor in the second conductivity type MOS region, wherein the contact hole etch stop layer has no stress. The metal gate CMOS device of claim 1, wherein the first conductivity type MOS transistor comprises a buried SiGe epitaxial layer, and a drain/source of the first conductivity type MOS transistor Polar area. The metal gate CMOS device of claim 2, wherein the cap layer directly contacts the buried SiGe epitaxial layer. The first gate of the metal gate CMOS component as described in claim 1 The electrical MOS transistor comprises a first metal gate and a first gate dielectric, wherein the first metal gate comprises titanium nitride, aluminum nitride, tantalum nitride, aluminum or a work function metal. The metal gate CMOS device of claim 1, wherein the second conductivity type MOS transistor comprises a buried SiC epitaxial layer, and a drain/source of the second conductivity type MOS transistor Polar area. The metal gate CMOS device of claim 1, wherein the second conductivity type MOS transistor comprises a second metal gate and a second gate dielectric layer, wherein the second metal gate comprises Titanium nitride, aluminum nitride, tantalum nitride, aluminum or work function metal. The metal gate CMOS device of claim 1, wherein the sealing layer is a tantalum nitride sealing layer.