201239959 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體元件及其製作方法，尤指一種雙功 函數(dual work-fUnction)金屬閘極(metal-gate)互補式金氧半導體 (CMOS)電晶體元件及其製作方法。 【先前技術】 隨著半導體元件持續地微縮，功函數金屬已逐漸取代傳統多晶 石夕作為匹配高介電常數介電層的控綱極^目前，雙功函數金屬間 極之製作方法可概分為前閘極(gate_first)製程與後閘極(职把七贫)製 程，其中，後_製程又被稱做「置換金屬閘極(Replace_t Metal-Gate)」或「RMG」製程’可以避免源極/沒極超淺接面活化回 火以及金屬魏物等高熱預算製程，且具有較寬的材料選擇，故漸 漸地取代前閘極製程。 習知的後閘極製程係先形成一多晶石夕虛置閘極(dummy㈣或 置換閘極(replacementgate)，然後依序完成多道的M〇s電晶體製作 步驟’例如’形成第-側壁子、第一側壁子後的LDD離子佈植、沒 極/源極的埋入磊晶製程、氮化矽/氧化矽複合第二側壁子製程、汲極 /源極的離子佈植等等，接著’再將多㈣虛置閘極移除而形成1 極溝渠(gatetrench)，最後依電性需求於閘極溝渠内填入不同的金 201239959 由於雙功函數金屬閘極一方面需要與NM〇S元件搭配，另一方 面則需與PMOS元件搭配，因此使得相關元件的整合技術以及製程 控制更形複雜’且各材料的厚度與成分控制要求亦更形嚴苛。在這 個嚴苛的製程環境下，如何在製作雙功函數金屬閘極時又同時整合 PMOS/NMOS元件的製程，而同時賴降低成本與完成具有競爭力 產品的作法即為現今重要課題。 【發明内容】 據此’本發明提供一種雙功函數金屬閘極CMOS元件及製作方 法整a 了埋入式SiGe/SiC製程’其能夠簡化雙功函數金屬閘極 CMOS製程的複雜度，並進―步降低製造成本。 根據本發明之一較佳實施例，本發明提供一種雙功函數金 極CMOS元件的製作方法，包含有：提供一基底包含有一第4 域及第—d域；分別在該第—區域及該第二輯形成—第一虛^ 閘極結構及-第二虛置閘極結構；分別於該第—虛置閘極結構 的該基底中及該第二虛置閘極結構_的該基底中形成—第一輕換 雜沒極及-第二婦雜汲極；分別於該第—虛置閘極結構上及⑽ -虛置閘極結構上形成—第一侧壁子及一第二側壁子；於該第 置閘極結構_的該基底中形成—第—埋人蠢晶層；於該第一區ς 封層；及形成該封層之後，於該第二虛置閘極結構兩側㈣ 基底中形成一第二埋入磊晶層。 ζ 6 201239959 在形成該第二埋入蟲晶層之後，繼續於該基底上全面沈積 -接觸洞侧停止層，覆蓋住該第—區域及該第二區域；於 接觸洞侧停止層上形成—第—介電層；進行—化學機械研磨製 私’研磨掉冑份厚度的該第一介電層及該第一接觸洞触刻停止 層’直到曝露出該第—虛置_結構及該第二虛置閘極結構；去除 該第-虛置_結構及該第二虛置閘極結構，分卿成—第一間極 溝渠及一第二閘極溝渠；及於該第—閘極溝渠内形成-第-閘極介 電層及-第-金屬閘極，並於該第二閘極溝渠内形成—第二問極介 在械4第金屬閘極及該第二金屬閘極之後，繼續於該基底 上沈積-第二介電層；_該第—區域内的該第―、第二介電層、- j第、接觸顺顺止層及該封層，形成—第—接細，蚀刻該第 一區域内的4第-、第二介電層及該第—接觸洞侧停止層，形成 -第二接觸洞；於該第―、第二接觸洞的底部形成—㈣金屬層， 及於該第、第—接觸洞填人金屬層’俾形成—第—接觸插塞及一 第二接觸插塞。 根據本I明之另一較佳實施例，在形成該第一金屬間極及該第 二金屬閘極之後，繼續去除該第—介電層、該第-接觸職刻停止 層以及該封層；沈積—具有應力的第二接觸洞_停止層；於該第 一接觸舰胁止層形成―第三介電層；侧該第—區域内的該第 201239959 三介電層及該第二接觸洞侧停止層，形成一第―接細，姓刻該 第二區域内的該第三介電層及該第二接觸洞蚀刻停止層，形成一第 二接觸洞；於該第第二接觸洞的底部形成—魏金屬層；及於 該第一、第二接觸洞填入金屬層，俾形成一第一接觸插塞及一第二 接觸插塞。 另一方面，本發明提供一種金屬閘極CM〇s元件，包含有：一 基底，包含有一 PMOS區域及一 NMOS區域；一 PMOS電晶體， δ史於s亥PMOS區域内的該基底上；一 nmos電晶體，設於該NM〇s 區域内的該基底上；一封層，僅覆蓋住該PM〇s區域内的該1>]^1〇8 電晶體，及一接觸洞蚀刻停止層，覆蓋住該該pM〇s區域内的封層 及該NMOS區域内的該NM0S電晶體。其中該pM〇s電晶體包含 有一第一金屬閘極以及一第一閘極介電層。該第一閘極介電層包含 金屬氧化物。該金屬氧化物包含有氧化給(hafnium oxjde，Hf〇2)、石夕 酸铪氧化合物(hafnium silicon oxide，HfSi04)、矽酸铪氮氧化合物 (hafnium silicon oxynitride，HfSiON)、氧化鋁(aluminum oxide， AI2O3)、氧化爛(lanthanum oxide，La2〇3)、紹酸爛(lanthanum aluminum oxide，LaA103 )、氧化組(tantalum oxide，Ta2〇5)、氧化錯(zirconium oxide, Zr〇2)、石夕酸锆氧化合物(zirconium silicon oxide，ZrSi〇4)、或鍅 酸铪(hafnium zirconium oxide，HfZr〇2)。該 PMOS 電晶體另包含有一 埋入式SiGe磊晶層，位於該PMOS電晶體的一汲極/源極區域。該 封層直接接觸該埋入式SiGe磊晶層。該第一金屬閘極包含有氮化鈦 (titanium nitride，TiN)、氮化鋁（aluminum nitride，A1N)、氮化組 8 201239959 (tantalum nitride, TaN)、紹（aluminum，A1)或功函數金屬。 為讓本發明之上述目的、特徵及優點缺_賴，下文特舉 較佳實施方式，並配合所賴式，作詳細說明如下。然而如下之較 佳實施方式無式僅供參考與朗用，並_來對本發明加以限制 者。 【實施方式】 請參閱第1 ®至第14圖，其桃據本㈣較佳實施例所繪示之 雙功函數金屬閘極CMOS元件製作方法之示意圖。首先，如第】圖 所示’提供-基底1G ’例如，基底料以切基底、切基底、 石夕覆絕緣基絲Μ基料。基底⑴_成有複數個淺溝絕 緣_ 12，電性隔離出至少—p则區域⑽以及—nm〇s區域 102。接下來，分別於基底10的PM〇s區域1〇1及麵⑽區域ι〇2 内形成-虛置閘極結構21以及—虛置閘極結構22，其中虛置問極 結構21可包含有一閘極魏介電層2U、一多晶破層训、一蓋層 21c以及-側壁氧化層21d，而虛置閘極結構22可包含有一問極石夕 氧介電層瓜、-多晶销细、—蓋層瓜以及一側壁氧化層咖。 蓋層21c及22c可以是氮化石夕。接著，在形成虛置間極結構η及 22之後，如_化光阻層3()蓋住p则區域⑼，圖案化光阻 層30的開口 3〇a則曝露出繼〇s區域1〇2，再進行一離子佈植製201239959 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a dual work-fUnction metal-gate complementary metal oxide Semiconductor (CMOS) transistor elements and methods of making same. [Prior Art] As semiconductor components continue to shrink, work function metals have gradually replaced traditional polycrystals as a master of matching high-k dielectric layers. Currently, a two-worker function inter-metal fabrication method can be used. It is divided into a front gate (gate_first) process and a rear gate (a seven-poor) process. The post-process is also called "Replacement Metal Gate (Replace_t Metal-Gate)" or "RMG" process. Source / immersion ultra-shallow junction activation tempering and metal heat and other high-heat budget process, and a wider material selection, so gradually replace the front gate process. The conventional post-gate process first forms a polycrystalline silicon dummy gate (dummy) or a replacement gate (replacement gate), and then sequentially completes multi-channel M〇s transistor fabrication steps 'eg, forming a first sidewall The LDD ion implantation after the first sidewall, the buried epitaxial process of the immersion/source, the second sidewall process of the tantalum nitride/yttria composite, the ion implantation of the drain/source, etc. Then, the multi-fourth dummy gate is removed to form a 1st gate trench. Finally, different gold is filled in the gate trench according to electrical requirements. 201239959 Due to the dual work function metal gate, it needs to be NM〇 on the one hand. S components are matched, on the other hand, they need to be matched with PMOS components, which makes the integration technology and process control of related components more complicated. The thickness and composition control requirements of each material are also more stringent. In this harsh process environment Next, how to integrate the PMOS/NMOS device process while fabricating the bi-worker metal gate, while at the same time reducing the cost and completing the competitive product is an important issue today. [Invention] According to the present invention mention A dual work function metal gate CMOS device and a fabrication method thereof, a buried SiGe/SiC process, which can simplify the complexity of the dual work function metal gate CMOS process and further reduce the manufacturing cost. In a preferred embodiment, the present invention provides a method for fabricating a dual work function gold-polar CMOS device, comprising: providing a substrate including a fourth domain and a -d-domain; respectively forming the first region and the second portion - a first dummy gate structure and a second dummy gate structure; respectively formed in the substrate of the first dummy gate structure and the substrate of the second dummy gate structure_-first light a second sidewall and a second sidewall; respectively, formed on the first dummy gate structure and the (10)-virtual gate structure; Forming a first-layer buried layer in the substrate of the gate structure _; forming a sealing layer in the first region; and forming the sealing layer, forming a substrate on both sides (4) of the second dummy gate structure a second buried epitaxial layer. ζ 6 201239959 After forming the second buried worm layer Continuing to deposit on the substrate, a contact hole side stop layer covering the first region and the second region; forming a first-dielectric layer on the contact hole side stop layer; performing - chemical mechanical polishing to make a private 'grinding Removing the first dielectric layer of the thickness and the first contact hole etch stop layer ' until the first dummy-structure and the second dummy gate structure are exposed; removing the first-dummy_structure And the second dummy gate structure, which is divided into a first pole trench and a second gate trench; and a first-gate dielectric layer and a -metal in the first gate trench a gate electrode formed in the second gate trench - a second interrogating electrode is deposited on the substrate after the second metal gate and the second metal gate; and the second dielectric layer is deposited on the substrate; - the first, second dielectric layer, -j first, contact smoothing layer and the sealing layer in the region, forming a -th-thin, etching 4th - and second dielectrics in the first region a layer and the first contact hole side stop layer, forming a second contact hole; forming a (four) metal layer at the bottom of the first and second contact holes, In the first, second - the contact hole metal layer that Person 'serve to form - of - contact plug and a second contact plug. According to another preferred embodiment of the present invention, after forming the first intermetal and the second metal gate, the first dielectric layer, the first contact stop layer, and the sealing layer are continuously removed; Depositing a second contact hole with a stress_stop layer; forming a "third dielectric layer" in the first contact ship barrier layer; the second dielectric layer of the 201239959 and the second contact hole in the first region The side stop layer forms a first contact, and the third dielectric layer and the second contact hole etch stop layer in the second region are formed to form a second contact hole; and the second contact hole is formed in the second contact hole Forming a germanium metal layer at the bottom; and filling the metal layer with the first and second contact holes to form a first contact plug and a second contact plug. In another aspect, the present invention provides a metal gate CM device comprising: a substrate including a PMOS region and an NMOS region; a PMOS transistor, δ on the substrate in the PMOS region; An nmos transistor disposed on the substrate in the NM〇s region; a layer covering only the 1>]^1〇8 transistor in the PM〇s region, and a contact hole etch stop layer, Covering the capping layer in the pM〇s region and the NMOS transistor in the NMOS region. The pM〇s transistor includes a first metal gate and a first gate dielectric layer. The first gate dielectric layer comprises a metal oxide. The metal oxide comprises hafnium oxjde (Hf〇2), hafnium silicon oxide (HfSi04), hafnium silicon oxynitride (HfSiON), and aluminum oxide (aluminum oxide). , AI2O3), lanthanum oxide (La2〇3), lanthanum aluminum oxide (LaA103), oxidation group (tantalum oxide, Ta2〇5), zirconium oxide (Zr〇2), Shi Xi Zirconium silicon oxide (ZrSi〇4) or hafnium zirconium oxide (HfZr〇2). The PMOS transistor further includes a buried SiGe epitaxial layer located in a drain/source region of the PMOS transistor. The cap layer directly contacts the buried SiGe epitaxial layer. The first metal gate comprises titanium nitride (TiN), aluminum nitride (A1N), nitride group 8 201239959 (tantalum nitride, TaN), aluminum (A1) or work function metal . In order to omise the above-mentioned objects, features and advantages of the present invention, the preferred embodiments are described below in conjunction with the preferred embodiments. However, the following preferred embodiments are for reference and use only, and are intended to limit the invention. [Embodiment] Please refer to Figures 1 to 14 for a schematic diagram of a method for fabricating a dual work function metal gate CMOS device according to the preferred embodiment of the present invention. First, as shown in the figure, 'providing-substrate 1G' is used, for example, to cut the substrate, cut the substrate, and to insulate the base material. The substrate (1)_ has a plurality of shallow trenches _12, electrically isolating at least -p then the region (10) and the -nm〇s region 102. Next, a dummy gate structure 21 and a dummy gate structure 22 are formed in the PM〇s region 1〇1 and the surface (10) region ι2 of the substrate 10, wherein the dummy gate structure 21 may include The gate dielectric layer 2U, a polycrystalline layer, a cap layer 21c and a sidewall oxide layer 21d, and the dummy gate structure 22 may comprise a porphyrin dielectric layer melon, a polycrystalline pin Fine, capped melon and a side oxide layer. The cap layers 21c and 22c may be nitrided. Next, after the dummy inter-pole structures η and 22 are formed, if the photoresist layer 3 () covers the p-region (9), the opening 3〇a of the patterned photoresist layer 30 is exposed to the subsequent region 〇1. 2, then carry out an ion implantation
程130,於虛置間極結構22兩側之基細内形成一輕摻雜 220。 J 201239959 {(第2圖所不’接著，在離子佈植製程⑽之後，去除圖案化 光阻層30 ’再以另一圖案化光阻層4〇蓋住丽〇s區域脱，圖案 化光阻層40的開σ 4Ga則曝露出pM〇s區域⑼，然後進行一離子 梯植製程14G，於虛置閘極結構21 _之基底1() _成一輕換雜 沒極(LDD)21()，隨後，去除圓案化光阻層⑽。當然，熟習該項技 藝者應能轉第1圖中的LDD離子佈植製健第2圖巾的⑽離 子佈植製程順序上係可以互換的。 如第3圖所示，於基底1()的表面上全面沈積—侧壁子材料層 5〇 ’覆蓋住PMOS區域101以及顧⑽區域1〇2。根據本發明之曰較 佳實施例，舰子材㈣5〇可以是碳摻雜化料，其介電常數較 不掺雜碳缝鮮要高。如第4圖_，歸，以神向性餘刻 製程儀刻触子材料層5G，如此相在虛置酿結構21及的側 壁上形成健子51及52。由此可知，本發賴鱗徵之—係在形 成LDD之後，始形成閘極側壁子。 乂 接著，如第5圖所示，於基底1〇的表面上另外全面沈積一犧牲 II化石夕層54 ’覆蓋住PMOS區域101以及NM〇s區域1〇2。根 本發明之雜實侧，齡氮切層M可以是切錢化艮 與前述之侧壁子材料層50具有明顯的蝕刻選擇比。 、 ci之’犧牲氮 化矽層54的蝕刻速率明顯高於侧壁子材料層5〇的蝕刻選擇比 201239959 如第6圖所示，接著以一圖案化光阻層6〇蓋住刪〇 搬’而圖案化光阻層60的開口 6〇a則曝露出pM〇s區域ι〇卜接 下來’進行-钱刻製程，於PM〇s區域1〇1内的虛置間極結構21 71， ’、，且θ 60 °如第7圖所示，接著進行PMOS區域ι01的SiGe 蟲晶製程’於凹槽71内形成埋入式啦以晶層81。根據本發明之 較佳實糊，前紅獅^製㈣同步㈣晰行p+捧雜，形 11^式獅蟲晶層81，故可省略後續PM〇S的沒極/源極的離 子佈植步财相對應的料。 雕 …如第8 _示’接著進行—侧製程，選擇性的去轉NMOS 區域102内剩餘的犧牲氮化石夕層％。在其它實施例中，此敍刻步驟 亦可以省略。然後，進行—沈積製程，例如，化學氣相沈積(CVD) 或原子層顿ALD)，於基底丨Q的表面上再全面沈積—氮化石夕封層 (SiN seal layer)% ’其厚度約介於5()埃至2⑻埃之間。 圖所示，接著以一圖案化光阻層80蓋住PMOS區域 1⑴’而圖案化光阻層80的開口 80a則曝露出NM0S區域1〇2。接 下來’進行i刻製程，於NM〇s區域1〇2内的虛置問極結構D 、兩側自動對準形成西格瑪形⑻興★_)的凹槽72，然後去除圖 案^匕光阻層8G。如第1G圖所示，接著進行NM〇s區域⑴2的沉 蟲曰曰製知’於凹槽72内形成埋入式SiC蟲晶層82。根據本發明之 實包例則述之沉蟲晶製程係同步(in-situ)進行N+掺雜，形The process 130 forms a light doping 220 in the base of both sides of the dummy interpole structure 22. J 201239959 {(No. 2 of the second figure) Next, after the ion implantation process (10), the patterned photoresist layer 30' is removed, and another patterned photoresist layer 4 is used to cover the area of the 〇s s, and the patterned light is removed. The opening σ 4Ga of the resist layer 40 exposes the pM 〇s region (9), and then an ion ladder process 14G is performed on the substrate 1 () of the dummy gate structure 21 _ into a light-changing impurity (LDD) 21 ( Then, the rounded photoresist layer (10) is removed. Of course, those skilled in the art should be able to switch the LDD ion implanted 2nd towel in Figure 1 (10). The ion implantation process is interchangeable. As shown in FIG. 3, the sidewall material layer 5'' is entirely deposited on the surface of the substrate 1() to cover the PMOS region 101 and the (10) region 1〇2. According to a preferred embodiment of the present invention, The ship's material (4) 5〇 can be a carbon doped material, and its dielectric constant is higher than that of the undoped carbon seam. As shown in Fig. 4, returning, the engraved material layer 5G is engraved with a divine process. In this way, the sons 51 and 52 are formed on the sidewalls of the dummy stalk structure 21 and the stalks. Thus, it can be seen that the squaring is formed after the formation of the LDD. Then, as shown in FIG. 5, a sacrificial II fossil layer 54' is additionally deposited on the surface of the substrate 1 覆盖 to cover the PMOS region 101 and the NM 〇 s region 1 〇 2. The solid side of the fundamental invention, The aged nitrogen cut layer M may have a significant etching selectivity ratio with the sidewall material layer 50. The etching rate of the sacrificial tantalum nitride layer 54 is significantly higher than that of the sidewall material layer 5〇. The etching selectivity is as shown in Fig. 6 of 201239959, and then the patterned photoresist layer 6 is covered by the photoresist layer 6 and the opening 6〇a of the patterned photoresist layer 60 is exposed to the pM〇s region. Next, the 'improvement-money engraving process, the dummy interpole structure 21 71, ', and θ 60 ° in the PM〇s region 1〇1 is as shown in Fig. 7, followed by the SiGe insect crystal of the PMOS region ι01 The process 'forms a buried layer 81 in the groove 71. According to the preferred solid paste of the present invention, the front red lion is made (4) synchronously (four) clarified p+, and the 11 stylus layer 81 is shaped. Therefore, the material corresponding to the ion-implantation step of the PM/S of the subsequent PM〇S can be omitted. The carving is as follows: The remaining sacrificial nitride layer % in the NMOS region 102 is removed. In other embodiments, the characterization step can also be omitted. Then, a deposition process, such as chemical vapor deposition (CVD) or atomic layer, is performed. ALD), deposited on the surface of the substrate 丨Q—SiN seal layer%' thickness between about 5 () angstroms and 2 (8) angstroms. As shown, the PMOS region 1(1)' is then covered with a patterned photoresist layer 80 and the opening 80a of the patterned photoresist layer 80 exposes the NMOS region 1〇2. Next, 'I process, the dummy structure D in the NM〇s area 1〇2, the two sides are automatically aligned to form the groove 72 of the sigma shape, and then the pattern is removed. Layer 8G. As shown in Fig. 1G, the buried SiC worm layer 82 is formed in the recess 72 by performing the immersion of the NM 〇 s region (1) 2 . According to the actual package example of the present invention, the in-situ process is performed in-situ for N+ doping.
11 S 201239959 成N埋入式SiC蠢晶層82，故可省略後續NM0S的汲極/源極的離 子佈植步驟及相對應的光罩。此外，熟習該項技藝者應能理解第6〜7 圖中PMOS區域的埋入式SiGe磊晶製程與第9~1〇圖中NM〇s區 域的埋入式SiC磊晶製程順序上係可以互換的。 如第11圖所示，接著在基底1〇的表面上全面沈積一接觸洞蝕 刻停止層(CESL)90，例如，氮化石夕層，其厚度可以介於1〇〇埃至15〇 埃之間。根縣發明讀佳實關，接觸洞侧停止層9G可以不具 有應力。然後，在接觸洞侧停止層9〇上沈積一介電層91，例如， 矽氧層或者低介電常數材料層。 如第12圖所示，進行一化學機械研磨(CMp)製程，研磨掉一部 份厚度的介電層91、-部份厚度的接__停止層9()、虛置間極 結構21的蓋層21c以及虛置閘極結構22的蓋層瓜，如此即曝露 出虛置閘極結構21的多晶韻21b以及虛置閘極結構22的多晶石夕 層22b。然後，利祕刻方式，將虛置閘極結構2ι(包括多晶石夕層 21b以及閘極魏介電層21a)及虛置閘極結構22(包括多晶碎層孤 以及閘極魏介電層22a)完全去除，俾形成閘極溝渠％丨及開極溝 渠322 β別曝露出PM〇s電晶體的通道區域⑵以及丽〇s電晶 體的通道區域122。 如第I3圖所不，接下來於閘極溝渠奶内形成高介電常數 (highk)閘極)丨電層421a及金屬閘極42化，於閉極溝渠内形成 12 201239959 高介電常數閘極介電層422a及金屬閘極422b。其中，高介電常數 閘極介電層421a及422a可選自氮化矽(siN)、氮氧化矽(SiON)以及 金屬氧化物所組成之一群組，其中金屬氧化物則包含氧化铪 (hafnium oxide，Hf02)、矽酸铪氧化合物(hafhiuin siHC0n oxide， HfSi〇4)、石夕酸給氮氧化合物(hafnium silicon oxynitride, HfSiON)、氧 化鋁(alumimmi oxide，Al2〇3)、氧化鑭(lanthanum 〇xide，La2〇3)、鋁酸 鑭（lamhamrni aluminum oxide，LaA103 )、氧化鈕(tantalum oxide，11 S 201239959 The N-embedded SiC stray layer 82 is formed, so the step of implanting the drain/source of the subsequent NM0S and the corresponding mask can be omitted. In addition, those skilled in the art should be able to understand that the buried SiGe epitaxial process in the PMOS region of Figures 6 to 7 and the buried SiC epitaxial process sequence in the NM〇s region of the ninth to the first enthalpy can be used. Interchangeable. As shown in FIG. 11, a contact hole etch stop layer (CESL) 90 is then deposited on the surface of the substrate 1 ,, for example, a nitride layer, which may have a thickness between 1 〇〇 and 15 Å. . The root county invented the Jiashiguan, and the contact hole side stop layer 9G may have no stress. Then, a dielectric layer 91, for example, a tantalum layer or a low dielectric constant material layer, is deposited on the contact hole side stop layer 9A. As shown in Fig. 12, a chemical mechanical polishing (CMp) process is performed to polish away a portion of the thickness of the dielectric layer 91, a portion of the thickness of the __stop layer 9 (), and the dummy interpole structure 21 The cap layer 21c and the cap layer of the dummy gate structure 22 expose the polycrystal 21b of the dummy gate structure 21 and the polycrystalline layer 22b of the dummy gate structure 22. Then, in a secret way, the dummy gate structure 2ι (including the polycrystalline layer 21b and the gate Wei dielectric layer 21a) and the dummy gate structure 22 (including the polycrystalline layer layer and the gate Weisuke The electrical layer 22a) is completely removed, and the gate trenches % 丨 and the open trenches 322 β expose the channel region (2) of the PM 〇s transistor and the channel region 122 of the 〇 电 transistor. As shown in Figure I3, a high dielectric constant (highk) gate is formed in the gate drain milk. The tantalum layer 421a and the metal gate 42 are formed, and 12 201239959 high dielectric constant gate is formed in the closed drain trench. The electrode dielectric layer 422a and the metal gate 422b. The high dielectric constant gate dielectric layers 421a and 422a may be selected from the group consisting of tantalum nitride (siN), bismuth oxynitride (SiON), and metal oxides, wherein the metal oxide contains yttrium oxide ( Hafnium oxide, Hf02), hafhiuin siHC0n oxide (HfSi〇4), hafnium silicon oxynitride (HfSiON), alumina (alumimmi oxide, Al2〇3), cerium oxide ( Lanthanum 〇xide, La2〇3), lamhamrni aluminum oxide (LaA103), oxidation button (tantalum oxide,
Ta205)、氧化锆(zirconium oxide，Zr〇2)、矽酸錯氧化合物(zirc〇nium silicon oxide, ZrSi04)、或錯酸給(hafnium zirc〇nium 〇xide，HiZr〇2) 等。金屬閘極421b及422b可以包含有i化鈦、氮化I呂、氮化组、 銘或功函數金屬’可以是單層或複合層結構。高介電常數閘極介電 層421a及422a可以利用化學氣相沈積或原子層沈積形成，金屬問 極421b及422b可以利用沈積、蒸鑛或濺錢等方式形成最後再以 化學機械研磨去除掉閘極溝渠321及閘極溝渠322外的金屬層。 如第Μ圖所示’在完成高介電常數閘極介電層暨金屬閘極 (high-k/metal gate)製程之後，接著於基底1〇上再沈積一介電層92 接下來，進行接觸洞及接雕塞製程，包括乾勤! pM〇s區域1〇 内的介電層92、9卜接觸洞_停止層9()及氮切封層％，獅 接觸洞92a’曝露出PMOS電晶體的部分的汲極/源極，乾侧腦 區域1〇2 _介電層92、91及接觸洞細亭止層9〇，形成接· 娜’曝露出NM〇s電晶體的部分的祕/源極。繼之，進行石夕⑽ 屬製程’分別於接觸洞92a及92b的底部形成石夕化金屬層Μ及 201239959 172，例如，矽化鎳(NiSi)或NiPb最後，於接觸洞92a及9处填入 金屬附著層’例如，鈦（Ti)、氮化鈦（TiN)、鶴㈤，俾形成接觸插 塞192a及192b。從第14圖可看出本發明結構上的特徵之一在於 PMOS區域101係被氮化石夕封層56以及接觸洞钮刻停止層奶蓋 住，而NMOS區域102只被接觸洞蝕刻停止層9〇蓋住。 第15圖至帛16圖為依據本發明另一較佳實施例所输示之雙功 函數金屬閘極CMOS元件製作方法之示意圖，針，帛15圖係接 續第13圖。如第15圖所示，在完成第13圖中的金屬_製程之後， 接著將介 9卜接觸洞_停止層9()以及封層兄去除， 然後沈積另-接觸洞侧停止層93以及另-介電層94，其中，接 觸洞侧停止層93係具有應力，例如，伸麵力或壓鶴力，以增 加元件效能。 曰 接下來’如帛16圖所示’進行接觸洞及接觸插塞製程，包括乾 飯刻PMOS區域1〇1 _介電層％及接觸洞触刻停止層93，形成 接觸洞94a’曝露出PM0S電晶體的部分的雜/源極，乾侧nm〇s 區域102 β的介電層94及接觸洞钱刻停止層93,形成接觸洞9物， 曝露出NMOS料體_分的_/雜。繼之，進行魏金屬製 程’分別於接觸洞9如及州的底部形成石夕化金屬層271及272， 例如’石夕化錦。最後，於接觸洞94a及94b填入金屬附著層，例如， 鎢、鈦' 氮化鈦，俾形成接觸插塞194a及194b。 201239959 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第14圖為依據本發日驗佳實關所繪示之雙功函數金屬閘 極CMOS元件製作方法之示意圖。 第I5圖至第Ιό圖為依據本發明另—較佳實施例所繪示之雙功函數 金屬閘極CMOS元件製作方法之示奄圖。 【主要元件符號說明】 10基底 12淺溝絕緣 21虛置閘極結構 21a閘極矽氧介電層 21b多晶妙層 21c蓋層 2Id側壁氧化層 22虛置閘極結構 22a閘極石夕氧介電層 22b多晶碎層 22c蓋層 22d侧壁氧化層 30圖案化光卩且層 15 201239959 30a 開口 40圖案化光阻層 40a 開口 50側壁子材料層 51側壁子 52側壁子 54犧牲氮化矽層 56氮化矽封層 60圖案化光阻層 60a 開口 71凹槽 72凹槽 80圖案化光阻層 80a 開口 81埋入式SiGe磊晶層 82埋入式SiC磊晶層 90接觸洞蝕刻停止層 91介電層 92介電層 92a接觸洞 92b接觸洞 93接觸洞蝕刻停止層 94介電層 201239959 94a接觸洞 94b接觸洞 101 PMOS 區域 102NMOS 區域 121通道區域 122通道區域 130離子佈植製程 140離子佈植製程 171矽化金屬層 172矽化金屬層 192a接觸插塞 192b接觸插塞 194a接觸插塞 194b接觸插塞 210輕摻雜汲極 220輕掺雜汲極 271矽化金屬層 272矽化金屬層 321閘極溝渠 322閘極溝渠 421a閘極介電層 421b金屬閘極 422a閘極介電層 201239959 422b金屬閘極 18Ta205), zirconium oxide (Zr〇2), zirc〇nium silicon oxide (ZrSi04), or misacid (hafnium zirc〇nium 〇xide, HiZr〇2). The metal gates 421b and 422b may comprise a titanium nitride, a nitrided nitride, a nitrided group, or a work function metal 'which may be a single layer or a composite layer structure. The high dielectric constant gate dielectric layers 421a and 422a may be formed by chemical vapor deposition or atomic layer deposition, and the metal electrodes 421b and 422b may be formed by deposition, steaming or splashing, and finally removed by chemical mechanical polishing. a metal layer outside the gate trench 321 and the gate trench 322. As shown in the figure below, after completing the high dielectric constant gate dielectric and high-k/metal gate process, a dielectric layer 92 is deposited on the substrate 1 next. Contact hole and picking process, including dry work! The dielectric layer 92, 9 in the pM〇s area, the contact hole_stop layer 9() and the nitrogen sealing layer%, the lion contact hole 92a' exposes the PMOS Part of the transistor's drain/source, dry side brain region 1〇2 _ dielectric layer 92, 91 and contact hole fine pavilion stop layer 9〇, forming a part of the NM〇s transistor exposed Secret / source. Subsequently, the Shi Xi (10) genus process is performed to form a shihua metal layer 2012 and 201239959 172 at the bottom of the contact holes 92a and 92b, respectively, for example, nickel hydride (NiSi) or NiPb, and finally filled in the contact holes 92a and 9 The metal adhesion layer 'for example, titanium (Ti), titanium nitride (TiN), crane (five), and tantalum form contact plugs 192a and 192b. As can be seen from Fig. 14, one of the structural features of the present invention is that the PMOS region 101 is covered by the nitride nitride layer 56 and the contact hole stop layer, while the NMOS region 102 is only contacted by the hole etch stop layer 9 Cover it. 15 to 16 are schematic views showing a method of fabricating a bi-function metal gate CMOS device according to another preferred embodiment of the present invention, and the pin, Fig. 15 diagram is continued from Fig. 13. As shown in Fig. 15, after completing the metal_process in Fig. 13, the contact hole_stop layer 9() and the seal layer are removed, and then the other contact hole side stop layer 93 and the other are deposited. a dielectric layer 94 in which the contact hole side stop layer 93 has a stress, for example, an extension force or a crushing force, to increase the element performance.曰 Next, as shown in Fig. 16, the contact hole and contact plug process are performed, including the PMOS region 1〇1 _ dielectric layer % and the contact hole etch stop layer 93, and the contact hole 94a' is exposed to expose the PM0S. The impurity/source of the portion of the transistor, the dielectric layer 94 of the dry side nm〇s region 102β, and the contact hole stop layer 93 form a contact hole 9 to expose the NMOS material body__. Subsequently, the Wei metal process is performed to form the stone-like metal layers 271 and 272 at the bottom of the contact hole 9 and the state, for example, 'Shi Xi Hua Jin. Finally, a metal adhesion layer, for example, tungsten or titanium titanium nitride, is formed in the contact holes 94a and 94b to form contact plugs 194a and 194b. 201239959 The above is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. [Simple description of the drawings] Fig. 1 to Fig. 14 are schematic diagrams showing the manufacturing method of the dual work function metal gate CMOS device according to the present day. FIG. 15 is a schematic diagram showing a method for fabricating a dual work function metal gate CMOS device according to another preferred embodiment of the present invention. [Main component symbol description] 10 base 12 shallow trench insulation 21 dummy gate structure 21a gate pole tantalum dielectric layer 21b polycrystalline layer 21c cap layer 2Id sidewall oxide layer 22 dummy gate structure 22a gate magnetite oxygen Dielectric layer 22b polycrystalline layer 22c cap layer 22d sidewall oxide layer 30 patterned aperture and layer 15 201239959 30a opening 40 patterned photoresist layer 40a opening 50 sidewall sub-material layer 51 sidewall sub-52 sidewall 54 54 sacrificial nitride矽 layer 56 tantalum nitride capping layer 60 patterned photoresist layer 60a opening 71 recess 72 recess 80 patterned photoresist layer 80a opening 81 buried SiGe epitaxial layer 82 buried SiC epitaxial layer 90 contact hole etching Stop layer 91 dielectric layer 92 dielectric layer 92a contact hole 92b contact hole 93 contact hole etch stop layer 94 dielectric layer 201239959 94a contact hole 94b contact hole 101 PMOS region 102 NMOS region 121 channel region 122 channel region 130 ion implantation process 140 Ion implantation process 171 deuterated metal layer 172 deuterated metal layer 192a contact plug 192b contact plug 194a contact plug 194b contact plug 210 lightly doped bungee 220 lightly doped bungee 271 deuterated metal layer 272 deuterated metal layer 321 gate Pole gate 322 Trench gate dielectric 421a 421b 422a metal gate gate dielectric metal gate 18 201239959 422b