TWI545437B - Rram, and methods of storing and retrieving information for rram - Google Patents

Description

Resistive random access memory and method for storing and extracting information of resistive random access memory

The present invention relates to RRAM and methods of storing and capturing information from RRAM.

A type of memory system integrated circuit that is used in systems for storing data. Typically memory is fabricated into one or more arrays of individual memory cells. A memory bit is the smallest unit of information that is retained in a memory array. Each memory cell can correspond to a single memory bit having one of two different selectable states. In a binary system, the states can be treated as a "0" or a "1".

Resistive Random Access Memory (RRAM) is a type of memory that is focused on existing and future data storage needs. RRAM utilizes two or more stable state programmable materials that differ from each other in resistivity. Examples of memory cells that can be utilized in RRAM are phase change memory (PCM) cells, programmable metallization cells (PMC), conductive bridged random access memory (CBRAM) cells, and nanobridge memory. A unit, an electrolyte memory unit, a binary oxide unit, and a multilayer oxide unit (for example, a unit utilizing a polyvalent oxide). These memory unit types are not mutually exclusive. For example, CBRAM and PMC are overlapping classification groups.

An example of a prior art RRAM cell 10 is shown in FIG. 1 for transitioning between two memory states. One of these memory states is a high resistance state (HRS) and others. A low resistance state (LRS). The memory cell includes a programmable material 16 between a pair of electrodes 12 and 14. The programmable material can be a single homogeneous composition (as shown) or can include two or more discrete layers.

Electrode 12 is coupled to circuit 18 and electrode 14 is coupled to circuit 22. Circuits 18 and 22 can include sense lines and/or access lines coupled to the electrodes and are configured to provide an appropriate electric field across the memory unit during read/write operations. In some embodiments, the memory unit referred to can be one of a plurality of memory cells of a memory array, and circuits 18 and 22 can be used to uniquely address the memory cells of the array. One of the circuit configuration parts of each. In some embodiments, a "select" device (not shown) is provided adjacent memory unit 10 to reduce to and/or undesired current from the memory cell during use of the memory cell in a memory array. Give way. The example selection device includes a diode, a transistor, a bidirectional limit switch, and the like.

The application of the electric field EF(+) across the memory cell 10 forms a current conducting transition structure 20 that extends through the material 16. The transition structure 20 provides a low resistance current conduction path through one of the cells 10; and thus the structure 20 is formed to transition the cell to the LRS configuration.

The application of the electric field EF(-) degrades the structure 20 and returns the unit 10 to the HRS configuration. The electric field EF(-) has a polarity opposite to the electric field EF(+).

Depending on the nature of the memory cell and the nature of the programmable material and the chemical and physical aspects involved in forming the transition structure, the transition structure 20 can have many configurations. For example, the transition structure can be an ion particle filament that conducts current (the ion particle can be a superion cluster, an individual ion, etc.). As another example, the transition structure can include a region of altered phase, altered vacancy concentration, altered ion concentration (eg, altered oxygen ion concentration), etc.; Part of the filament.

The memory unit 10 can be programmed by providing an appropriate voltage across the memory unit to transition from the HRS configuration to the LRS configuration (or vice versa). By limiting the voltage across the memory cell to determine the resistance through one of the memory cells while limiting the voltage to It does not cause one of the stylized bits of the memory unit to read the memory unit.

Due to variations in the operational characteristics of the cells across an RRAM array, difficulties may be encountered during operation of the memory cells of the RRAM array. It is desirable to develop methods and structures that address these difficulties.

10‧‧‧RRAM unit

12‧‧‧ electrodes

14‧‧‧Electrode

16‧‧‧Programmable materials

18‧‧‧ Circuitry

20‧‧‧Transitional structure

22‧‧‧ Circuitry

30‧‧‧ Chart

32‧‧‧ Curve

34‧‧‧ Curve

35‧‧‧Area

40‧‧‧Chart

42‧‧‧ Curve

44‧‧‧ Curve

46‧‧‧Sensing window

50‧‧‧ memory array

52‧‧‧ memory unit

52a‧‧‧ memory unit

52b‧‧‧ memory unit

54‧‧‧Selection device

56‧‧‧Single memory bit

60‧‧‧Example embodiment memory array

62‧‧‧ Field Effect Crystal

Bl0‧‧‧ bit line

Bl1‧‧‧ bit line

Bl2‧‧‧ bit line

Bl3‧‧‧ bit line

Bl4‧‧‧ bit line

HRS‧‧‧high resistance state

LRS‧‧‧Low resistance state

Src‧‧‧ source line

Wl0‧‧‧ word line

Wl1‧‧‧ word line

Wl2‧‧‧ word line

Wl3‧‧‧ word line

Figure 1 illustrates two interchangeable memory states of a prior art memory cell.

2 graphically illustrates two groups of memory cells, wherein one of the groups is in a high resistance state and the other of the groups is in a low resistance state.

Figure 3 is a diagram showing two groups of memory cells and two groups of memory cells containing pairs of memory cells.

4 is a diagrammatic circuit diagram of one of the example embodiments of a stylized operation of an example embodiment RRAM array.

5 is a diagrammatic circuit diagram of one of the example embodiments of the read operation of the RRAM array of the example embodiment of FIG. 4.

6 is a diagrammatic circuit diagram of one of the example embodiments of a stylized operation of an example embodiment RRAM array.

7 is a diagrammatic circuit diagram of one of the example embodiments of the read operation of the RRAM array of the example embodiment of FIG. 6.

The prior art memory unit 10 of FIG. 1 illustrates two memory states (HRS and LRS) that can be selectively programmed into the memory unit and that are ideally readily distinguishable from one another during a read operation. However, an RRAM array can have one large group of cells in the HRS configuration and another large group of cells in the LRS configuration, and there can be substantial changes in the HRS and LRS characteristics of the cells across the respective groups. FIG. 2 is a diagram showing various memory cells of an example embodiment RRAM. In particular, Figure 2 includes depicting through individual memory cells. The nature of the current (as measured in arbitrary units au and as shown on a logarithmic scale on the x-axis of graph 30) is a graph 30 of the number of memory cells in the group (as depicted by SIGMA) having this property. . Two groups of memory cells are shown on the chart, one of which should be in the memory unit of the LRS configuration and shown by curve 32; and a second group should be in the memory unit of the HRS configuration, and Shown by curve 34.

The memory cell group that should be in the HRS configuration has a high resistance (i.e., a relatively low current for the x-axis scale of chart 30). Conversely, the memory cell group that should be in the LRS configuration covers a wide range of resistivity. Most of the memory cells along curve 32 have a low resistivity (i.e., a relatively high current for the x-axis scale of chart 30). However, some of the memory cells along curve 32 have a high resistivity, to the extent that a small number of memory cells that are present in the LRS configuration have one of the resistivity overlaps with the cells that should be in the HRS configuration. 35 (illustrated by the dotted line diagram).

The memory cells that should be in the LRS configuration can have high resistivity for any number of reasons. For example, such memory cells may never completely form one of the appropriate conductive transition structures associated with the LRS configuration (eg, similar to one of the structures 20 shown in FIG. 1). Alternatively, or in addition, this transition structure may have been degraded to reduce the conductivity through the cells. Regardless of the reason that there is a memory cell that should have too high resistivity in the LRS configuration, the high resistivity of the memory cells at these cells will indicate that the cell is in the HRS configuration during a read operation. Not in the expected LRS configuration.

The memory cells that should be in the LRS configuration but have a high resistivity (and therefore are within region 35) can be considered to correspond to one of the "tails" on the curve 32 representing the group of cells that should be in the LRS configuration. . In other words, the memory cells with the problematic high resistivity that should be in the LRS configuration are only a small fraction of the total cell group that should be in the LRS configuration.

In some embodiments, the memory in the "tail" of curve 32 is compensated One of the methods of high resistivity of a cell utilizes this relatively small portion of the problematic memory cell represented by the "tail". In particular, a memory bit is configured to include two or more memory cells. For example, in some applications, the memory bits can be configured to each include two memory cells coupled together. The output from the coupled memory cells is totaled during a read operation. Since the memory cell group that should be in the LRS configuration contains only a small fraction of the problematic high resistivity, most of the problematic high resistivity cells are combined with other cells having low resistivity rather than with each other. Combine. The memory cells may be arranged in parallel in the memory cells such that the current through one of the other memory cells is the total number of currents of the memory cells within the memory cell (ie, in the memory) One of the resistivities of the memory cells within the body position is combined in parallel). Thus, as long as one of the cells in the memory bit has a low resistivity, the total resistivity through the memory bit will be low.

One disadvantage of coupling multiple cells to individual memory bits is that the total storage density of the memory array will be reduced. For example, if each memory bit includes two memory cells, then the storage density of the memory array is reduced to the memory array if each memory bit includes only a single memory cell. One and a half storage density. More generally, if an RRAM array includes X memory cells and Y memory cells are incorporated into each memory bit, the RRAM will have no more than X/Y memory bits. Conversely, a single memory cell is included in each memory bit. A prior art RRAM array will include X memory bits.

Achieving this improved reliability by coupling multiple memory cells into a single memory bit can compensate for this disadvantage of reduced storage density in some applications. In some embodiments, the coupling of the memory cells within each memory bit can be viewed as improving the signal to noise ratio compared to using only a single memory cell in the memory bit.

3 shows a chart 40 having the same axis as chart 30 of FIG. 2, and graphically illustrates an improvement that can be achieved by coupling two memory cells into each memory bit. In the picture The two memory cell groups described with reference to FIG. 2 are shown in the graph of 3, one of which should be in the memory unit in the LRS configuration and shown by curve 32; and the other group should be in the HRS configuration. The memory unit is shown by curve 34. Two memory bit groups are also shown, wherein the individual memory bits contain a pair of memory cells and have a resistivity corresponding to the parallel combination of resistivity of the pair of memory cells. One of the groups of memory bits can be formed by pairing the memory cells from the curve 32. This group should be a memory bit group of low resistivity states and is shown by curve 42. The other of the groups of memory bits can be formed by pairing the memory cells from the curve 34. This group should be a memory bit group of a high resistivity state and is shown by curve 44.

All of the memory locations in the high resistivity group of curve 44 have high resistance, and curve 44 varies only modestly with respect to curve 34 corresponding to the individual memory cells.

All of the memory bitlines in the low resistivity group of curve 42 have a sufficiently low resistivity to distinguish from the memory bit of the high resistivity group of curve 44. In other words, the problematic overlap region 35 of FIG. 2 does not exist with respect to the memory bit groups of curves 42 and 44; and therefore, all of the low resistivity memory bits of curve 42 can be compared to curve 44. High resistivity memory bit distinction. One difference between the highest resistivity memory bit along curve 42 and the lowest resistivity memory bit along curve 44 can be considered to be suitable for determining high resistivity memory bits and low during a read operation. A sensing window 46 is one of the differences between the resistivity memory bits. Coupling a plurality of memory cells to a prior art memory bit in an individual memory bit that has resulted in a memory cell that is less than coupled lacks at least improves (ie, broadens) one of the sense windows.

The memory cells can be coupled by any suitable architecture to form the memory bits of FIG. 4 shows an example stylization operation using an architecture in which word lines are paired to produce memory bits including pairs of memory cells. This operation of Figure 4 is illustrated using a circuit diagram of a memory array 50. The memory array includes a plurality of bit lines (bl0 to bl4), source line (src), and word line (wl0 to wl4). The memory array includes memory cells 52, which are represented as resistors (only some of which are labeled), and include selection means 54 (only some of which are labeled). The selection means can be any suitable means; including, for example, field effect transistors, bipolar junction transistors, diodes, bidirectional limit switches, and the like. These selection devices are provided to alleviate the problematic leakage current. In some embodiments, if the leakage current is not a problem, the selection means can be omitted.

The two word lines wl1 and wl2 are paired together and, as illustrated by an asterisk (*) at each of the word lines, provide an electrical pulse along the two word lines. Similarly, an electrical pulse is provided along this bit line as illustrated by an asterisk (*) at bit line bl2. The electrical pulses along wl1, wl2, and bl2 cause both of the memory cells (shown as memory cells 52a and 52b) to be programmed into a particular state without stylizing the remaining memories Body unit. The memory cells 52a and 52b can be programmed into the same state as each other, and in particular, the resistivity of each of the memory cells 52a and 52b can be substantially changed simultaneously, so that the two memory cells It can be programmed substantially simultaneously into an HRS configuration, or two memory cells can be programmed into an LRS configuration at substantially the same time. The term "substantially simultaneously" encompasses operations in which coupled memory cells are exposed to stylized conditions and programs within operational limits and measurement limits or due to randomness of memory cells during stylized operations and Not exactly the same program. In some embodiments, the coupled memory cells of a memory bit can be completely separated from each other, and thus, the individually coupled memory cells can be programmed in a manner such that they are not simultaneously or even insubstantially The memory cells are also programmed relative to each other.

The memory cells 52a and 52b are paired together into a single memory bit 56. Other memory cells 52 can similarly be paired into memory bits. Thus, array 50 can be considered to be subdivided into a plurality of memory bits, where each memory bit includes two memory cells. Although the memory cells depicted include two memory cells, in other embodiments, the memory cells can be configured to include more than two memory cells.

Referring to FIG. 5, the memory cells 52a and 52b of the memory bit 56 are read by providing appropriate electrical pulses along w1, wl2, and bl2 (as illustrated by an asterisk (*) diagram), wherein the readings are performed. The pulse train has an appropriate duration and magnitude to determine the total current through one of the memory cells 52a and 52b without changing the stylized state of the memory bit 56. The total current (as shown) can be determined by causing current to flow through one of all of the coupled memory cells by completing the reading of the coupled memory cells. Alternatively, in some embodiments, the "coupled" memory cells can be read from each other (ie, the current passes through the individual memory cells along a path that does not extend through all of the total cells) and is later passed by The logic (and/or through other stylized circuits or operations) adds the currents together to produce the total current of the coupled memory cells. If the current is passed along one of the paths of all of the coupled memory cells extending through the one-bit element, the coupled memory cells of the bit can be considered to be read simultaneously with each other; and if the current is passed through the bit Each memory cell of the cell and later summing the currents with an additional operation, the coupled memory cells of the bit can be considered to be read in a non-simultaneous operation.

The illustrated configuration of memory array 50 has a plurality of memory cells 52, each of which is uniquely addressed by a combination of word lines and bit lines. In the illustrated embodiment, the memory cells of memory bit 56 are addressed by paired word lines wl1 and wl2 and a single bit line bl2. In other embodiments, similar memory bits can be addressed by pairs of bit lines and a single word line.

4 and 5 collectively illustrate the selection device 54. 6 and 7 each illustrate a stylized and read operation of an example embodiment memory array 60 including field effect transistors 62 (only some of which are labeled) of the selection devices. These pulses are shown on wl1 and wl2 for these stylized and read operations. For such stylized and read operations, the illustrated embodiment utilizes the same duration and magnitude of pulses as on W12 on wl1. In other embodiments, for the stylized operations, the read operations, or both of the stylized and read operations, the pulse utilized on wl1 may be different from the pulse utilized on wl2. Rush.

The memory arrays discussed above can be incorporated into an electronic system. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication data units, processor modules, and application specific modules, and can include multi-layer, multi-chip modules. The electronic systems can be any of a wide range of systems, such as clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

The particular orientation of the various embodiments in the figures is for illustrative purposes only and the embodiments may be rotated relative to those shown in some applications. The description and the accompanying claims are hereby incorporated by reference to the entire disclosure of the disclosure of the disclosure of It is rotated relative to this direction.

The cross-sectional views of the drawings show only features in the plane of the cross-sections, and to simplify the drawings, the material after the plane of the cross-sections is not shown.

Some embodiments include a method of storing and extracting data from an RRAM array of one of the X memory cells, wherein Y memory cells are coupled to each other in each memory bit such that the RRAM array has no more than X/ Y memory bits. The coupled memory cells of each memory bit are maintained in a mutual resistance state during reading and writing operations. The memory cells with coupled memory cells provide improved reliability compared to memory cells having only a single memory cell.

Some embodiments include a method of storing and capturing data from an RRAM array. The array is subdivided into a plurality of memory bits, wherein each memory bit includes at least two memory cells. A memory bit is programmed by substantially simultaneously changing the resistance state of all of the memory cells within the memory bit. The memory bit is read by determining the total current through all of the memory cells within the memory bit.

Some embodiments include an RRAM that includes a plurality of memory cells in which each of the memory cells is uniquely addressed by a single bit line/word line combination. The memory list The element includes a programmable material having a selectively interchangeable resistance state. The memory bit includes a plurality of memory cells coupled together. The coupled memory cells within each memory bit are in the same resistive state with each other.

50‧‧‧ memory array

52‧‧‧ memory unit

52a‧‧‧ memory unit

52b‧‧‧ memory unit

54‧‧‧Selection device

56‧‧‧Single memory bit

Bl0‧‧‧ bit line

Bl1‧‧‧ bit line

Bl2‧‧‧ bit line

Bl3‧‧‧ bit line

Bl4‧‧‧ bit line

Src‧‧‧ source line

Wl0‧‧‧ word line

Wl1‧‧‧ word line

Wl2‧‧‧ word line

Wl3‧‧‧ word line

Claims (29)

A method for storing and extracting data of a resistive random access memory (RRAM) array of X memory cells, comprising: forming individual memory bits, each of the individual memory bits having Y coupled memories a unit, where Y is an integer greater than or equal to 2 such that the RRAM array has no more than X/Y memory bits; during the read and write operations, the Y coupled memories of each memory bit The body cells are maintained in a mutual resistance state; the memory cells having Y coupled memory cells provide improved reliability compared to memory cells having only a single memory cell; the X memories The array of body units is subdivided into a plurality of memory bits, each memory bit having a number of coupled memory cells of the same number as Y, and a given memory bit comprising each of the Y coupled memory cells The given memory bit is configured to be separately programmed separately from independent memory bits associated with other groups of Y coupled memory cells; and separately programmed to be associated with the memory One other memory position of Yuan Yuan Yuan or more of the memory position. The method of claim 1, wherein the Y memory cells of one memory bit are simultaneously read. The method of claim 1, wherein the Y memory cells of one memory bit are substantially simultaneously programmed. The method of claim 1, wherein the Y memory cells of one memory bit are not programmed and/or read at the same time. The method of claim 1, wherein Y is two. The method of claim 5, wherein each memory unit is uniquely addressed by a combination of a word line and a bit line; and wherein the addressing is performed by a pair of word lines and individual bit lines The memory cells of the memory bit. The method of claim 5, wherein each memory cell is uniquely addressed by a combination of a word line and a bit line; and wherein the memory bit is addressed by the pair of bit lines and the individual word lines Memory unit. The method of claim 1, wherein the Y system is greater than two. The method of claim 1, wherein the resistive random access memory comprises phase change memory. The method of claim 1, wherein the resistive random access memory comprises a polyvalent metal oxide. The method of claim 1, wherein the resistive random access memory comprises a conductive bridge random access memory. The method of claim 1, wherein the resistive random access memory comprises a binary oxide. A method of storing and capturing data of a resistive random access memory (RRAM) array, the method comprising: subdividing the resistive random access memory array into a plurality of memory bits, each memory bit including a memory bit Having at least two coupled memory cells, each memory bit of the plurality of memory cells having an identical number of memory cells in the group, and associated with each of the plurality of memory bits Memory cell groups of memory bits, each set of memory cells being configured to be separately programmed separately with respect to other sets of memory cells in the array; by substantially simultaneously changing all of the memory bits The resistance state of the memory cell is programmed to a memory bit; and the memory bit is read by determining the total current through all of the memory cells within the memory bit. The method of claim 13, wherein the memory cells of the one memory cell are the same Read when. The method of claim 13, wherein the memory cells of a memory bit are not read at the same time. The method of claim 13, wherein each memory bit comprises two memory cells; wherein each memory cell is uniquely addressed by a combination of a word line and a bit line; and wherein the pair of words are The lines and individual bit lines address the memory cells of the memory bit. The method of claim 13, wherein each memory bit comprises two memory cells; wherein each memory cell is uniquely addressed by a combination of a word line and a bit line; and wherein the pair of bits is The memory lines of the memory bits are addressed by the meta-line and the individual word lines. The method of claim 13, wherein the resistive random access memory comprises phase change memory. The method of claim 13, wherein the resistive random access memory comprises a polyvalent metal oxide. The method of claim 13, wherein the resistive random access memory comprises a conductive bridge random access memory. The method of claim 13, wherein the resistive random access memory comprises a binary oxide. A resistive random access memory comprising: a plurality of memory cells including a programmable material; the programmable material having a selectively interchangeable resistance state; uniquely coupled by a bit line/word line combination Addressing each of the memory cells; and a memory bit comprising a plurality of memory cells coupled together; the coupled memory cells in each memory bit are a set of memory cells and are each other In the same resistance state, each group of memory cells is configured to be related to Other sets of memory cells included in other memory bits are separately programmed. The resistive random access memory of claim 22, wherein the memory bits comprise a pair of memory cells; and wherein the pair of memory cells are addressed by a pair of word lines and individual bit lines Memory unit. The resistive random access memory of claim 22, wherein the memory bits comprise a pair of memory cells; and wherein the pairs of memory cells are addressed by pairs of bit lines and individual word lines Memory unit. The resistive random access memory of claim 22, comprising more than two coupled memory cells in each memory bit. The resistive random access memory of claim 22, wherein the resistive random access memory comprises phase change memory. The resistive random access memory of claim 22, wherein the resistive random access memory comprises a polyvalent metal oxide. The resistive random access memory of claim 22, wherein the resistive random access memory comprises a conductive bridge random access memory. The resistive random access memory of claim 22, wherein the resistive random access memory comprises a binary oxide.