TWI544749B - Analog-digital converter controller and digital calibration method for the same - Google Patents

Description

Analog digital conversion controller and digital correction method

The invention relates to an analog digital conversion controller and a correction method, in particular to a small-area application field, such as a general-purpose approaching analog-like digital converter, a determinant analog-to-digital converter in an image sensor, and a raw Analog to digital converter in medical systems.

Referring to FIG. 1 , a schematic diagram of a conventional conversion circuit of a binary analog-to-digital converter is shown. As shown in FIG. 1, the conversion circuit converts the analog signal into a digital signal by connecting a plurality of capacitors in parallel with each other. However, to implement an N-bit analog-to-digital converter, the total number of capacitors required is 2 ^(N+1) . For miniaturized applications, reducing the amount of capacitors in order to reduce the area of the converter is a problem that needs to be solved.

Referring to FIG. 2, a schematic diagram of a conventional second-order digital-to-digital converter conversion circuit is shown. On the left is the MSB (most significant bit) array, which consists of n bits, and the right side is the LSB (Least Significant Bit) array, which consists of m bits, which are connected in series by Capacitor 115 forms a n+m bit digital analog converter. For a N-bit digital analog converter, the total number of capacitors required is an analog digital converter for N bits. The total number of capacitors is 2 ⁽ⁿ⁺⁾ +2 ⁽ⁿ⁺¹⁾ +1. One of the more capacitors is the series capacitor 138. At the same time, the first parasitic capacitance C _P1 generated between the series capacitor 138 and the ground and the second parasitic capacitance C _P2 generated across the series capacitor 138 cause nonlinearity of the output digital code, resulting in the DNL of the digital analog converter ( Differential nonlinearity) generation of values.

Refer to Figures 3, 4, and 5. 3 is a schematic diagram of a conventional three-stage analog-to-digital converter conversion circuit; FIG. 4 is a diagram showing an analog-to-digital conversion curve of the analog digital signal of FIG. 3; and FIG. 5 is a diagram showing the DNL of FIG. A map of values and digit codes. The middle of the third order is the MSB array and the two sides are the LSB array. The number of bits in each order is from the MSB array to the LSB array in the order of 3 (1C, 2C, 4C), 4 (1C, 2C, 4C, 8C), 3 ( 1C, 2C, 4C) bits (where C is the unit capacitance value). Under this architecture, the parasitic capacitance of the first series capacitor 2381 and the second series capacitor 2382 affect the DNL of the digital analog converter, but the closer to the MSB array, the greater the influence of the series capacitance, that is, the parasitic capacitance of the first series capacitor 2381. The capacitance will have a more serious effect than the parasitic capacitance of the second series capacitor 2382. Ideally, the capacitance of the first series capacitor 2381 should be 16C/15, but because of the parasitic capacitance of the first series capacitor 2381 in series or the first series capacitor 2381 The drift of the process itself (that is, the error caused by poor fabrication) will make it impossible to have a capacitance value of 16C/15 and cause the DNL of the digital analog converter to deteriorate. If we set the first series capacitor 2381 to 0.9C, the digital analog conversion curve is as shown in FIG. 4, and an uncorrected analog digital conversion signal 248 is compared with a standard linear signal 245 because the MSB array is 3 bits, so 2 ³ -1=7 breakpoints are generated, and these breakpoints are positive values of the upward offset, resulting in their DNL as shown in Figure 5, each of which is offset upwards in Figure 4 The shifted position has a corresponding DNL value in Figure 5, and 7 positions have a positive DNL value. As a result of the upward shift of the DNL value, the uncorrected analog digital conversion signal 248 has no overlapping portion at all, so the analog input voltage is 0.105~0.130 (volts) corresponding to 130 (digital code). That is, after the analog-to-digital converter is solved, one digit code represents a plurality of analog input voltage values, so the digital code cannot derivate the actual analog input voltage value, so the presentation partial interval cannot be resolved. Therefore, digital mode correction cannot be used and can only be adjusted by analog correction. It can be seen from the above description of the second-order and third-order digital analog converters that the total number of capacitors can be effectively reduced by continuously increasing the order of the conversion circuit, but corresponding parasitics are generated around each of the corresponding series capacitors that are correspondingly increased. The capacitor in turn generates a DNL value when analog digital signal is converted. Therefore, how to solve the DNL value generated by the series capacitor is a problem to be solved.

Referring to FIG. 6, a schematic diagram of a conventional conversion circuit of an analog digital converter having an analog correction circuit is shown. Each of the base capacitors Cc requires an additional variable capacitor Ccn to compensate for the DNL generated by the parasitic capacitance. Therefore, in addition to the original conversion circuit, a large number of variable capacitors Ccn are required, and these variable capacitors Ccn make the entire analog-to-digital converter design complicated and the area becomes large. Therefore, it is impossible to effectively improve the performance of the analog digital converter under a small area.

To solve the above problems of the prior art. One of the main objects of the present invention is to provide an analog digital conversion controller. The analog to digital conversion controller includes an analog to digital converter and a digital correction circuit.

The analog-to-digital converter includes a complex-order conversion circuit for receiving a type of analog signal to generate a digital signal. The digital correction circuit receives the digital signal and generates a final digital signal; wherein the digital signal corresponds to each of the conversion circuits having at least one differential nonlinearity (DNL) value, and each of the differential nonlinearities is negative value.

The digital correction circuit further includes: a correction code table and an adder.

The correction code table is used to store a complex correction code. And a segment for correcting the digital signal by extracting the corresponding correction codes in the correction code table.

The analog to digital converter includes at least one series capacitor connected in series between each two-stage conversion circuit. The series capacitors are used to adjust each of the differential nonlinear values to a negative value.

In order to solve the above problems, another object of the present invention is to provide a digital correction method. Inputting a first analog signal to an analog-to-digital converter to generate a first digital signal, the analog digital converter includes a complex-order conversion circuit, and each two-stage conversion circuit is connected in series with at least one series capacitor, the method includes: First, a complex correction code is stored in a digital correction circuit. Then, a second analog signal is input to the analog digital converter to generate a second digital signal, and the first analog signal is the same size as the second analog signal. Then, the second digital signal is input to the digital correction circuit. Then, the digital correction circuit combines the correction codes to correct the segment corresponding to the second digital signal. Finally, a final digital signal is generated, wherein the first digital signal and the second digital signal have a differential nonlinearity (DNL) value corresponding to at least one negative value of each of the conversion circuits.

The step of storing the correction codes includes storing the correction codes in a correction code table of the digital correction circuit. The step of combining the correction codes includes multiplying the correction codes by corresponding coefficients and adding them to correct the second digital signals.

In an embodiment of the invention, the method further includes comparing the first digital signal with a standard linear signal to obtain the correction codes.

In another embodiment of the invention, the method further includes adjusting a capacitance value of the at least one series capacitor between each two-stage conversion circuit such that each of the differential nonlinear values is a negative value.

Compared to the prior art, the present invention makes each of the values by adjusting the values of the series capacitors. The DNL values are all negative, so that subsequent corrections can be made by the digital correction method without the problem of the additional capacitance required by the conventional analog correction method.

138, 438‧‧‧ series capacitor

2381‧‧‧First series capacitor

2382‧‧‧Second series capacitor

245, 445‧‧‧ standard linear signals

248, 448‧‧‧Uncorrected analog digital conversion signal

400‧‧‧ analog digital conversion controller

410‧‧‧ analog signal

430‧‧‧ Analog Digital Converter

435‧‧‧Transition circuit

440‧‧‧first digit signal

470‧‧‧Digital Correction Circuit

475‧‧‧Correction code list

479‧‧‧Adder

490‧‧‧ final digital signal

601~603‧‧‧ difference

Code 1~3‧‧‧Correction code

(1)~(3)‧‧‧ equation

FIG. 1 is a schematic diagram showing a conversion circuit of a conventional binary analog-to-digital converter.

FIG. 2 is a schematic diagram showing a conversion circuit of a conventional second-order digital analog converter.

FIG. 3 is a schematic diagram showing a conversion circuit of a conventional third-order analog-to-digital converter.

Figure 4 is a graph showing the analog-to-digital conversion curve of the analog digital signal of Figure 3.

Figure 5 is a diagram showing the correspondence between the DNL value and the digit code in Figure 4.

FIG. 6 is a schematic diagram showing a conversion circuit of an analog analog converter with an analog correction circuit.

FIG. 7 is a schematic structural diagram of an analog digital conversion controller according to a first embodiment of the present invention.

Fig. 8 is a view showing the configuration of a digital analog converter of the first embodiment of the present invention.

Figure 9 is a diagram showing the digital correction circuit of the first embodiment of the present invention.

FIG. 10 is a graph showing a conversion curve of an analog digital signal according to the first embodiment of the present invention.

Figure 11 is a diagram showing the correspondence between the DNL value and the digit code in Figure 10.

Fig. 12 is a view showing a correction code table of the first embodiment of the present invention.

Figure 13 is a diagram showing the digital correction method of the present invention.

The following description of various embodiments is presented to illustrate the specific embodiments The directional terms mentioned in the present invention, such as "upper", "lower", "before", "after", "left", "right", "inside", "outside", "side", etc., are merely references. The direction of the schema. Therefore, the directional terminology used is for the purpose of illustration and understanding of the invention.

Refer to Figure 7 and Figure 8. FIG. 7 is a block diagram showing the structure of the analog-to-digital conversion controller 400 of the first embodiment of the present invention. An analog to digital conversion controller 400 includes an analog to digital converter 430 and a digital correction circuit 470. FIG. 8 is a block diagram showing the digital analog converter 430 in the analog-to-digital conversion controller 400 of the first embodiment of the present invention.

The analog to digital converter 430 includes a third order conversion circuit 435. A type of analog signal 410 (including the first analog signal and the second analog signal) is transmitted to the analog-to-digital converter 430, and a digital signal 440 (including the first digital signal and the second) generated after the third-order conversion circuit 435 is generated. The digital signal contains 2 ^(3.1) - 1 DNL values. A series capacitor 438 is disposed in the middle of each of the conversion circuits 435. The series capacitor 438 is sized to make each DNL value a negative value.

Referring to Figures 9 through 12, FIG. 9 is a schematic diagram of a digital bit correction circuit 470 of the first embodiment of the present invention. The digital bit correction circuit 470 includes a correction code table 475 and an adder 479. Figure 10 is a diagram showing the analogy of the first embodiment of the present invention. Digital signal conversion graph. Figure 11 is a diagram showing the correspondence between the DNL value and the digit code in Figure 10. Fig. 12 is a diagram showing a correction code table 475 of the first embodiment of the present invention. The adder 479 passes through the three sets of correction codes generated after the first digital signal 440 that has not been corrected and a standard linear signal 445 is calculated: a first correction code Code1, a second correction code Code2, and a third correction code Code3. Reference is also made to the correction code table of Fig. 12 and the analog digital conversion curve of Fig. 10. For example, when the signal is located at 128~255 (digit code), the first difference 601 between the standard linear signal 445 and the uncorrected first digital signal 440 is equal to the first correction code Code1; when the signal is located 256~383 (digit code), the second difference between the standard linear signal 445 and the uncorrected first digital signal 440 is equal to the first correction code Code1+the second correction code Code2; when the signal is located at 512~639 (Digital code), the standard linear signal 445 and the third difference 603 of the uncorrected first digital signal 440 are equal to 2* first correction code Code1 + second correction code Code2+ third correction code Code3. Please refer to the following equation: first difference = first correction code --- (1)

Second difference = first correction code + second correction code - (2)

Third difference = 2 * first correction code + second correction code + third correction code - (3)

The first difference 601, the second difference 602, and the third difference 603 are known, and the correction codes can be obtained by a simple operation. If an analog digital converter with more orders is used, the correction code can be obtained by correcting the coding table and the analog digital conversion curve.

Then inputting the second analog signal 410 to generate the second digital signal 440, and the digital correction circuit combines the correction codes to correct the corresponding segment of the second digital signal 440 to obtain a final digital signal (not shown). ).

In this embodiment, when the series capacitor 438 is set to 1.1 times the ideal series capacitance, the digital analog conversion curve will have 7 breakpoints as shown in FIG. 10, but these breakpoints are negative of the lower offset. value. Referring also to Fig. 11, each of the downward offset positions in Fig. 10 has a corresponding DNL value in Fig. 11, and seven positions have a negative DNL value. These negative DNLs result in an uncorrected analog digital conversion signal 448 having overlapping portions at each breakpoint, which results in an input analog voltage of 0.12 to 0.16 (volts), although corresponding to 128 (digit code). However, before the input analog voltage reaches 0.16 (volts), each input analog voltage corresponds to a single digital code. Therefore, when the input analog voltage reaches 0.16 (volts), it can be judged by simple logic that only the input analog voltage is 0.16 (volts) corresponds to 128 (digital code), and the input analog voltage is 0.12 to 0.16 (volts). Both correspond to 128 (digit code). Therefore, when all DNL values are negative, the case where multiple analog input voltages correspond to the same digital code can be resolved so that each analog voltage can correspond to a single digital code. Referring to FIG. 12, the section corresponding to the second digit signal is distinguished according to the digit code. In a preferred embodiment of the present invention, for example, the correction code required for the segment of the digital code 128 to 255 is the first correction code Code1; the correction code required for the segment of the digital code 384 to 511 is 2* A correction code Code1 + second correction code Code2; the correction code required for the segment of the digital code 768~895 is 3* first correction Encoding Code1+2* second correction code Code2+ third correction code Code3; referring to Fig. 13, the digital bit correction method of the present invention is illustrated. First, a first analog signal 410 to an analog-to-digital converter 430 is input in step S01 to generate a first digital signal 440. Then, in step S02, the first digital signal 440 is compared with a standard linear signal 445 to obtain at least one correction code. For example, when the analog to digital converter 430 is 3rd order, 3 correction codes are generated. In other words, the number of correction codes will be the same as the order of the analog to digital converter 430. The at least one correction code is stored in a digital bit correction circuit 470 in step S03. In detail, the correction code is stored in a correction code table 472 of the digital bit correction circuit 470. If the same signal as the first analog signal 410 has been processed, that is, the correction code table 472 already has a corresponding correction code, and after the step S01 is completed, the step S02 is omitted and the step S03 is executed. A second analog signal 410 is input to the analog-to-digital converter 430 in step S04 to generate a second digital signal 440. The first analog signal 410 and the second analog signal 410 are actually the same size signals. Therefore, the correction code generated by the first analog signal 410 can be used for the correction of the second analog signal 410. The first digital signal 440 and the second digital signal 440 both have at least one differential nonlinearity (DNL) value before being corrected. The present invention is characterized in that the value of each series capacitor connected in series between each order of the analog-to-digital converter 430 is adjusted so that each of the differential nonlinear values is negative so that all differential nonlinear values can pass through the digits. The way to correct. Then, the second digit signal 440 is input to the digit correction circuit 470 in step S05. Then combined correction correction correction in step S06 The second digit signal. For example, when the analog to digital converter 430 is 3rd order, 3 correction codes are generated. In detail, the correction code is added to the first signal by an adder of the digital correction circuit. Further referring to Fig. 12, it can be known that, for example, in the segment of the digital code 128~255, the required correction code is the first correction code Code1; in the segment of the digital code 640~767, the required correction code is 3* A correction code Code1 + second correction code Code2+ third correction code Code3. Finally, a final digital signal 490 is generated in step S07.

Therefore, in order to facilitate the design of the digital circuit in accordance with the process miniaturization, the present invention selects a digital manner to correct the linearity of the analog digital converter. Therefore, in order to ensure that the correction method proposed by the present invention can operate correctly, it requires each serial connection. The capacitance of capacitor 438 needs to be larger than its ideal value, so that the DNL value of the digital analog converter is negative. As for the parasitic capacitance of other series capacitors 438, although it also affects the linearity of the analog digital converter, in the third-order digital analog converter of this design, the maximum and minimum value of the standard shift generated by the process will make the DNL less than 0.5LSB. Therefore no correction is required, but the invention can also be applied to the correction of other series capacitors 438 if desired. This type of correction requires only an additional x (x < N) set of memory to memorize code1 to codex and a set of adders to correct the linearity of the progressive approximation analog converter. Therefore, the analog-to-digital conversion controller of the present invention can have both advantages of small area and high linearity compared with the prior art.

The above is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art will be able to do without departing from the principles of the present invention. Several modifications and retouchings are also possible, which should also be considered as protection of the present invention.

400‧‧‧ analog digital conversion controller

410‧‧‧ analog signal

430‧‧‧ Analog Digital Converter

435‧‧‧Transition circuit

440‧‧‧first digit signal

470‧‧‧Digital Correction Circuit

490‧‧‧ final digital signal

Claims (8)

An analog-to-digital conversion controller includes: an analog-to-digital converter comprising a complex-order conversion circuit for receiving a analog signal to generate a digital signal; and a digital correction circuit for receiving the digital signal, and Generating a final digital signal; wherein the digital signal corresponds to each of the conversion circuits having at least one differential nonlinearity (DNL) value, and each of the differential nonlinearities is a negative value, wherein the series capacitances are used to adjust each The differential nonlinear value is a negative value. The analog digital controller of claim 1, wherein the digital correction circuit comprises: a correction coding table for storing a complex correction code; and an adder for capturing the correction code table The corresponding correction codes correct the segments corresponding to the digital signals. The analog digital controller of claim 1, wherein the analog digital converter comprises at least one series capacitor connected in series between each two-stage conversion circuit. A digital bit correction method, particularly for use in a type of digital controller, comprising: inputting a first analog signal to an analog to digital converter to generate a first digital signal, the analog digital converter comprising a complex digital conversion circuit, And connecting at least one series capacitor between each two-stage conversion circuit, the method comprising: storing a complex correction code in a digital correction circuit; inputting a second analog signal to the analog digital converter to generate a second digital position Signal, the first analog signal is the same size as the second analog signal; Inputting the second digit signal to the digit correction circuit; combining the correction codes to correct the segment corresponding to the second digit signal by the digit correction circuit; and generating a final digit signal, wherein the first digit signal and the The second digital signal has a differential nonlinearity (DNL) value corresponding to at least one negative value for each of the conversion circuits. The method of claim 4, wherein the method further comprises comparing the first digital signal with a standard linear signal to obtain the correction codes. The method of claim 4, wherein the storing the correction codes comprises storing the correction codes in a correction code table of the digital correction circuit. The method of claim 4, wherein the step of combining the correction codes comprises multiplying the correction codes by respective coefficients and adding them to correct the second digital signal. The method of claim 4, wherein the method further comprises adjusting a capacitance value of the at least one series capacitor between each two-stage conversion circuit such that each of the differential nonlinear values is a negative value.