JP2013074401A - Pipeline type a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pipeline type A/D converter capable of removing restriction on a dither quantity due to an offset of a comparator.SOLUTION: A pipeline type A/D converter 100 which converts an analog signal into a digital signal includes a plurality of cascaded stages, and an error correction circuit 101 which generates a digital signal on the basis of sub digital signals output from the plurality of stages respectively. When outputting an N-bit sub digital signal, at least one of the plurality of stages is such that a stage gain of a transfer function is 2, a folding-back number is 2-4, 2-2, or 2, and the number of bits overlapping when error correction is made with an adjacent stage is 2.

Description

  The present invention relates to a pipeline type A / D converter.

FIG. 41 is a diagram illustrating a configuration of a general pipeline ADC.
In the pipeline ADC, a plurality of stages are connected in cascade.

  Between the stages, analog results calculated at each stage are transmitted. Each stage has a digital output and is connected to an error correction circuit (ECL). The output of the error correction circuit ECL is a digital output of the ADC.

  In general, all stages except the final stage, stage 8, have one system for analog input, one system for analog output, and one system for digital output. As shown in FIG. 41, the stage is composed of SADC (Sub Analog-to-Digital Converter) and MDAC (Multiplying Digital-to-Analog Converter).

  Although details of the stage will be described later, generally speaking, the input signal is roughly quantized by the SADC, and the result is digitally output. The analog amount corresponding to the output digital value is D / A converted by the DAC function by MDAC, subtracted from the input value, and then amplified to a constant magnification by the amplification function (in the example of FIG. 41, Twice).

  Since the final stage has no stage in the next stage, only the SADC is configured. Unlike the other stages, there are many cases where the quantization is slightly finer. In the case of FIG. 41, unlike the other stages, quantization is performed with 3 bits.

  Since the pipeline ADC is composed of a switched capacitor circuit and a plurality of stages can operate simultaneously, a plurality of conversion processes can proceed simultaneously. For this reason, it has the characteristics that the throughput is high and the conversion speed can be easily increased. Further, there is a feature that the resolution can be easily increased by increasing the resolution of the stage or increasing the number of stages. Pipeline ADCs having such features are used not only for image / video applications but also for communications, and their application range is wide.

  FIG. 42 is a diagram illustrating a transfer function of a 1.5-bit stage SADC. FIG. 43 shows a transfer function of a 1.5-bit stage MADC.

  The SADC has a determination point at ± Vref / 4 with respect to the input voltage Vin, and the output Do is expressed by the following equation.

Do = 0 (Vin <−Vref / 4)
Do = 1 (−Vref / 4 <Vin <Vref / 4)
Do = 2 (Vin> Vref / 4)
The MADC receives the output of the SADC and performs an operation represented by the following expression.

Vout = 2 × Vin− (Do−1) × Vref
Since the value of the SDC output Do changes with Vin = ± Vref / 4, the transfer function of the MADC has a broken line characteristic as shown in FIG.

  By the way, although it is known that an error occurs in the calculation in the MADC, this error adversely affects the conversion result of the ADC.

Causes of calculation errors in MADC include offset errors and gain errors.
An offset error occurs due to an offset potential of the amplifier, charge injection of a switch in the MADC, or clock feedthrough. As a phenomenon, the output of the MADC moves in parallel. In a normal pipeline ADC, an offset error once generated at an intermediate stage does not have a method of correcting in subsequent stages, so the result of A / D conversion is also shifted as it is.

  The gain error is caused by finite gain of the amplifier, lack of transient characteristics of the amplifier (settling error), and mismatch of two capacitors included in the MADC. When a gain error occurs, the output of the MADC expands and contracts in the vertical direction as in the transfer function of the MADC shown in FIG. 44, and the inclination of the transfer function and the amount of folding in the transfer function change. In the former, since the magnitude of the residual component (that is, the MADC output) changes, the slope of the A / D conversion result changes. In the latter case, as shown in FIG. 44, there is a discrepancy between the digital amount given in the stage and the analog amount subtracted by MADC, so that there is a step in the A / D conversion result as shown in FIG. To do. Unlike the former, these phenomena greatly affect linearity characteristics such as DNL (Differential Non-linearity Error) and INL (Integral Non-linearity Error) as shown in FIG.

  The dither is a very effective means for improving the degradation of linearity as shown in FIG. 46, in particular, the degradation of DNL (differential nonlinearity). The principle of pipeline dithering is to spread a code in which a step in the A / D conversion result occurs to a plurality of points by shifting the judgment point of the comparator on the time axis. In many systems using the ADC, data processing (noise reduction, low-pass filter processing, etc.) in which some averaging action occurs is often performed. When steps diffused at a plurality of points are input to such a system, the steps are averaged according to the frequency per time. That is, as shown in FIG. 47, one step is converted into a number of steps having a size of 1 / the number of diffusions. The linearity is also improved as shown in FIG.

  By the way, the greater the number of dither divisions, the smoother the INL and DNL. However, an increase in the number of divisions increases the hardware to be realized, so a trade-off is important.

  On the other hand, the amplitude is a parameter that does not affect the value of DNL but has a large influence on INL. When the dither amplitude is small, the divided step groups are concentrated near the original step position. Therefore, when viewed from a macro view, neither the ADC transfer function nor INL changes. On the other hand, if the amplitude is large, it is scattered over a wide range, so that it appears to be completely divided as shown in FIGS. If the resolution of the stage is an integer multiple of 1LSB, the larger the better, but the balance is ideally 1LSB considering the balance with other parameters such as the input range. However, in practice, the value is limited to a smaller value due to a dither implementation method or the like. Introducing a large amplitude dither is one of the important issues in increasing the dither effect.

  One method of realizing dither for pipeline ADC is a method called threshold dither. In this method, a mechanism for shifting the determination point of the SADC at the stage of the pipeline ADC is provided.

  As a method of shifting the determination point, it is common to add dither to the reference voltage of the SADC comparator.

  A feature of threshold dither is that a dither component is applied only to SADC and no dither is applied to MADC. Although the decision point is deviated by applying dither, the influence of dither does not appear in the A / D conversion result due to the redundancy effect of the stage.

FIG. 49 is a diagram illustrating a transfer function of MADC when threshold dither is applied.
Since the MADC changes the turning point, as shown in FIG. 49, the MADC moves in parallel to the left and right positions according to the added dither value. As a result, a stepped code in the A / D conversion result is diffused, and the linearity is improved. Of course, since no dither is applied to the MADC, the input range does not decrease.

JP 2010-21918 A

  However, the threshold dither has a problem that the amount of dither due to the offset of the comparator is limited.

  That is, since the applied dither is handled in the same way as the offset error of the SADC comparator, the sum of the dither amplitude and the offset error needs to fall within a desired value. Therefore, it is necessary to limit the amplitude of the dither to be applied or to reduce the offset error of the comparator. In the former method, the range in which the step is diffused is narrowed and the step is concentrated in a narrow range, so that the degree of improvement in INL (integral nonlinearity) is reduced. In the latter method, in order to reduce the offset error, it is necessary to increase the area of the element, leading to an increase in the area.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a pipeline type A / D converter that can eliminate the limitation of the dither amount due to the offset of the comparator.

In order to solve the above-described problem, an embodiment of the present invention is a pipelined A / D converter that converts an analog signal into a digital signal, and includes a plurality of stages connected in cascade and a plurality of stages. An error correction circuit that generates a digital signal based on the output sub-digital signal, and when at least one of the plurality of stages outputs an N-bit sub-digital signal, the stage gain of the transfer function is 2 ^N-2 , and the number of turns is 2 ^N -4, 2 ^N -2, or 2 ^N , and the number of bits that overlap when performing error correction with an adjacent stage is 2 bits.

  According to the pipeline type A / D converter of one embodiment of the present invention, the restriction on the dither amount due to the offset of the comparator can be eliminated.

It is a figure showing the structure of pipeline ADC. It is a figure showing the transfer function of SADC of a 1st embodiment. It is a figure showing the transfer function of MADC of 1st Embodiment. It is a figure showing the transfer function of 3 types of MDAC with a stage gain of 2. It is a figure showing the structure of SADC of this Embodiment. It is a figure showing the structure of MDAC of this Embodiment. FIG. 6 is a diagram illustrating a configuration of a reference voltage generation unit included in FIG. 5. It is a figure showing the structure of the random number generation source contained in FIG. It is a figure showing the truth table of the decoder contained in FIG. It is a figure which shows the difference by the difference in overlap, and the difference in the input range of the next stage. It is a figure which shows the redundancy seen from the bit of another overlap. It is a figure showing the transfer function of SADC of the modification 1 of 1st Embodiment. It is a figure showing the transfer function of MDAC of the modification 1 of 1st Embodiment. It is a figure showing the transfer function of SADC when a stage gain is 4. It is a figure showing the transfer function of MADC when a stage gain is 4. It is a figure showing the structure of SADC when a stage gain is 4. It is a figure showing the structure of MADC when a stage gain is 4. It is a figure showing the structure of a reference voltage generation part when a stage gain is 4. It is a figure showing the transfer function of SADC when the stage gain is 4 and both ends are folded. It is a figure showing the transfer function of MADC when a stage gain is 4 and both ends turn. It is a figure showing the structure of SADC when the stage gain is 4 and both ends are folded. It is a figure showing the structure of MADC when a stage gain is 4 and both ends turn. It is a figure showing another structure of MADC when a stage gain is 4 and both ends turn up. It is a figure showing the structure of the reference voltage production | generation part in case a stage gain is 4 and both ends turn. It is a figure showing the structure of differential type SADC when the stage gain is 4 and both ends are folded. It is a figure showing the structure of differential type MADC when the stage gain is 4 and both ends are folded. It is a figure showing another structure of a differential type MADC when the stage gain is 4 and both ends are folded. It is a figure showing the structure of pipeline ADC of 2nd Embodiment. It is a figure showing the specific structure of a dither generation part. It is a figure showing the structure of pipeline ADC of the modification 1 of 2nd Embodiment. It is a figure showing the specific structure of a dither generation part. It is a figure showing the structure of pipeline ADC of the modification 2 of 2nd Embodiment. It is a figure showing the structure of the reference voltage generation part of 3rd Embodiment. It is a figure showing the transfer curve of conventional MADC. It is a figure showing the input-output characteristic of the conventional pipeline ADC. It is a figure showing the image of the curve of INL when the conventional dither is applied. It is a figure showing the structure of the stage of 4th Embodiment. It is a figure showing the transfer curve of MADC of 4th Embodiment. It is a figure showing the input-output characteristic of pipeline ADC of 4th Embodiment. It is a figure showing the image of the curve of INL when the dither of 4th Embodiment is applied. It is a figure which shows the structure of a general pipeline ADC. It is a figure showing the transfer function of SADC of 1.5 bit stage. It is a figure showing the transfer function of MADC of 1.5 bit stage. It is a figure showing the transfer function of the conventional MADC. It is a figure showing the conventional A / D conversion result. It is a figure showing conventional DNL and INL. It is a figure showing an A / D conversion result. It is a figure showing DNL and INL. It is a figure showing the transfer function of MADC at the time of threshold dither application.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
In the present embodiment, the following points are improved with respect to the conventional threshold dither.

  (1) While maintaining the stage gain, increase the number of turns and decrease the output amplitude.

(2) Increase the number of overlap bits by increasing the number of turns.
This has the following effects.

(1) A dither having an amplitude of 1 LSB can be applied.
(2) There is no need to improve the accuracy of the comparator.

  (3) Since there is no change in the stage gain, there is no need to improve the characteristics of the MDAC amplifier.

FIG. 1 is a diagram illustrating the configuration of a pipeline ADC.
As shown in FIG. 1, the pipeline ADC 100 includes a plurality of stages and a digital error correction circuit 101.

Each stage includes a SubADC (SADC) 103 and an MDAC 104.
The digital error correction circuit 101 generates a digital signal based on the sub digital signal output from each of the plurality of stages.

  FIG. 2 is a diagram illustrating a transfer function of the SADC according to the first embodiment. FIG. 3 is a diagram illustrating a transfer function of the MADC according to the first embodiment.

  The SADC has determination points at ± Vref × 3/8 and ± Vref / 8 with respect to the input voltage Vin, and the output Do is expressed by the following equation.

Do = 0 (Vin <−Vref × 3/8)
Do = 1 (−Vref × 3/8 <Vin <−Vref × 8)
Do = 2 (−Vref / 8 <Vin <Vref / 8)
Do = 3 (Vref / 8 <Vin <Vref × 3/8)
Do = 4 (Vref × 3/8 <Vin)
Since the value of the output SDo of SADC changes between ± Vref × 3/8 and ± Vref / 8, the transfer function of the MADC has a broken line characteristic as shown in FIG.

  Due to the effects of (1) and (2), the redundancy has increased compared to FIGS. 42 and 43, so that even if the judgment point of the SADC comparator deviates to ± 3/8 × Vref, the A / D conversion result is affected. There is no.

  If the dither is given by 1LSB, that is, the amplitude corresponding to the folded and folded sections, INL can be improved most efficiently.

  In the case of FIG. 2 and FIG. 3, since 1LSB = Vref / 4, it is only necessary to provide a dither of ± Vref / 8. In the case of FIG. 2 and FIG. 3, even if the decision point is shifted by ± 3/8 × Vref, the A / D conversion result is not affected. This means that not only is it sufficient to provide a 1LSB dither, but the offset error of the SADC comparator can be tolerated to ± Vref / 4. Since the allowable offset error is the same value as in the case of FIGS. 42 and 43 before increasing the number of turns, there is no need to improve the accuracy of the comparator by increasing the number of turns. In order to increase the accuracy of the comparator, it is necessary to increase both the area and the current. Therefore, it is significant to avoid this.

Next, redundancy will be described in more detail.
FIG. 4 is a diagram showing transfer functions of three types of MDACs with a stage gain of 2. As shown in FIG.

  As shown in FIG. 4, in the classic 1-bit stage, 2Vref is folded at a position that is half the input width of 2Vref, that is, at Vin = 0. 1LSB corresponding to 0 before the return and 1LSB corresponding to 1 after the return are allocated exactly. Since the output of the stage exceeding ± Vref exceeds the input range of the subsequent stage and is not accepted, the stage output needs to fall within ± Vref. The output of 1-bit stage is exactly ± Vref when Vin = 0, and there is no redundancy.

  On the other hand, in a general 1.5-bit stage, the number of folds is increased to two so that the number of folds per time is half of that of the 1-bit stage. If the first turn is in the range of −Vref / 2 ≦ Vin ≦ 0 and the second turn is in the range of 0 ≦ Vin ≦ −Vref / 2, the output of the stage is within ± Vref. In other words, a general 1.5-bit stage has redundancy with a width of Vref / 2 for each turn.

  In the stage according to the present embodiment, the number of folds is increased to four so that the number of folds per turn is set to 1/4 Vref / 2 of the 1-bit stage.

  The first return is in the range of −3 / 8 × Vref ≦ Vin ≦ 0, the second return is in the range of −Vref / 4 ≦ Vin ≦ Vref / 8, and the third return is −Vref. If / 8 ≦ Vin ≦ Vref / 4 and the fourth turn is in the range of 0 ≦ Vin ≦ 3/8 × Vref, the output of the stage will be within ± Vref. In other words, in the present embodiment, the stage has redundancy with a width of 3/4 × Vref.

  Considering 1 LSB of a 1-bit stage as a reference, redundancy is 0 LSB for 1-bit MDAC, 0.5 LSB for 1.5-bit MDAC, and 0.75 LSB for the MDAC of this embodiment.

  These also correspond to the overlap of digital output. In the 1-bit stage, there is no overlap, but in the 1.5-bit stage, there is an overlap of 1 bit, which is an integer part 1 bit and a decimal part 1 bit. In the stage of the present embodiment, 2 bits overlap, and the integer part is 1 bit + the decimal part is 2 bits. It can be seen that the more overlap, the higher the correction capability.

FIG. 5 is a diagram showing the configuration of the SADC of the present embodiment.
The SADC 103 generates a sub-digital signal corresponding to the magnitude of the analog signal or the sub-analog signal output from the preceding stage, outputs the sub-digital signal to the error correction circuit, and outputs the analog signal or the sub-analog output from the preceding stage. A voltage selection signal corresponding to the magnitude of the signal is generated.

  As shown in FIG. 5, the SADC 103 includes a random number generation source 105, a reference voltage generation unit 106, comparators 110, 111, 112, 113, MDAC decoders 108, 109, and an encoder 114.

The random number generation source 105 gives a random number to the reference voltage generation unit 106.
The reference voltage generation unit 106 generates a plurality of reference voltages Vef1, Vref2, Vref3, and Vref4 based on the random number of the random number generation source 105. The magnitude of the reference voltage Vref4 is a voltage deviated from 3 / 8Vref by ± α. The magnitude of the reference voltage Vref3 is a voltage that is shifted from the 1/8 Vref by ± α. The magnitude of the reference voltage Vref2 is a voltage shifted by ± α from −1/8 Vref. The magnitude of the reference voltage Vref1 is a voltage deviated from −3 / 8Vref by ± α.

  The comparator 110 compares the input voltage Vin with the reference voltage Vref4 and outputs the comparison result to the MADC decoder 108. The comparator 111 compares the input voltage Vin with the reference voltage Vref3 and outputs the comparison result to the MADC decoder 108. The comparator 112 compares the magnitudes of the input voltage Vin and the reference voltage Vref2, and outputs the comparison result to the MADC decoder 109. The comparator 113 compares the input voltage Vin with the reference voltage Vref1 and outputs the comparison result to the MADC decoder 109.

  This input voltage Vin is the output voltage (sub analog signal) of the MDAC 104 of the previous stage when the SADC 103 is the SADC 103 of the stage 2 to the stage 8, and the pipeline when the SADC 103 is the SADC 103 of the stage 1 It is an analog input voltage (analog signal) input to the ADC 100.

  The encoder 114 outputs 4-bit digital data (sub-digital signal) corresponding to the comparison results of the comparators 110, 111, 112, and 113.

  The MADC decoders 108 and 109 generate voltage selection signals SW2a to SW2f according to the comparison result.

  The MADC decoder 108 activates one of the voltage selection signals SW2a, 2b, and 2c to “H” level and deactivates the rest to “L” level according to the comparison result of the comparators 110 and 110. To do.

  The MADC decoder 109 activates one of the voltage selection signals SW2d, 2e, and 2f to the “H” level and deactivates the rest to the “L” level according to the comparison result of the comparators 112 and 113. To do.

FIG. 6 is a diagram showing the configuration of the MDAC of the present embodiment.
The MADC 104 generates a sub-analog signal according to the input voltage Vin and the voltages (+ Vref, 0, −Vref) input according to the voltage selection signals SW2a to SW2f generated by the SADC 103, and enters the next stage. Output.

  As shown in FIG. 6, the MADC includes a plurality of switches 263 to 272, capacitors Ci <b> 1 and Ci <b> 2, and capacitors 261 and 262.

  The capacitor Ci1 is connected to the first input of the amplifier 115, is connected to the input voltage Vin via the switch 263, is connected to the first voltage (+ Vref) via the switch 267, and is connected via the switch 268. It is connected to the second voltage (0V), and is connected to the third voltage (−Vref) via the switch 269.

  The capacitor Ci2 is connected to the first input of the amplifier 115, is connected to the input voltage Vin via the switch 264, is connected to the first voltage (+ Vref) via the switch 270, and is connected via the switch 271. It is connected to the second voltage (0V), and is connected to the third voltage (−Vref) via the switch 272.

  The first input and the output of the amplifier 115 are connected to the capacitors 261 and 262 connected in parallel via the switch 265. The output of the amplifier 115 is connected to the input voltage Vin via the switches 265 and 273.

  The first input and the second input of the amplifier 115 are connected via a switch 266. The second input of amplifier 115 is connected to the power supply.

  Switches 267, 268, and 269 are controlled by voltage selection signals SW2a, SW2b, and SW2c, respectively.

  The switches 270, 271, and 272 are controlled by voltage selection signals SW2d, SW2e, and SW2f, respectively.

  The switches 263, 264, 266, 273 are controlled by a switch signal SW1. The switch 265 is controlled by the switch signal SW2.

The amplifier 115 outputs a sub analog signal (Vout) to the next stage.
FIG. 7 is a diagram showing the configuration of the reference voltage generation unit included in FIG.

  As shown in FIG. 7, the reference voltage generation unit 106 includes a plurality of resistors R in which two reference potentials (+ Vref, −Vref) are connected in series, and two reference potentials by the plurality of resistors R. Are provided with a plurality of terminals T1 to T20 that output potentials internally divided and switch circuits 501 to 504.

  The plurality of terminals T1 to T20 are classified into a first group of terminals T1 to T5, a second group of terminals T6 to T10, a third group of terminals T11 to T15, and a fourth group of terminals T16 to T20.

  The switch circuit 501 is provided for the first group, selects one of the terminals of the first group based on the switch signals SW [0] to SW [4], and sets the potential of the selected terminal. Output as the reference voltage Vref4.

  The switch circuit 502 is provided for the second group, selects one of the terminals of the second group based on the switch signals SW [0] to SW [4], and sets the potential of the selected terminal. Output as the reference voltage Vref3.

  The switch circuit 503 is provided for the third group, selects one of the terminals of the third group based on the switch signals SW [0] to SW [4], and sets the potential of the selected terminal. Output as the reference voltage Vref2.

  The switch circuit 504 is provided for the fourth group, selects one of the terminals of the fourth group based on the switch signals SW [0] to SW [4], and sets the potential of the selected terminal. Output as the reference voltage Vref1.

FIG. 8 shows a configuration of the random number generation source included in FIG.
The random number generation source 105 includes a plurality of flip-flops 111, 112, 113, a logic circuit 251, and a decoder 114 that are connected cyclically. The random number generation source 105 generates switch signals SW [0] to SW [4] for controlling a plurality of switches in the reference voltage generation unit 106 based on random number values that change with time.

FIG. 9 shows a truth table of the decoder included in FIG.
The input “abc” indicates that the output of the flip-flop 111 is “a”, the output of the flip-flop 112 is “b”, and the output of the flip-flop 113 is “c”.

  When the input is “001”, only the switch signal SW [0] is activated to a high level, and the other switch signals SW [1] to SW [4] are deactivated to a low level. When the input is “010”, only the switch signal SW [1] is activated to a high level, and the other switch signals SW [0], SW [2] to SW [4] are deactivated to a low level. Is done. When the input is “011”, only the switch signal SW [2] is activated to a high level, and the other switch signals SW [0], SW [1], SW [3], SW [4] Deactivated to low level. When the input is “100”, only the switch signal SW [3] is activated to a high level, and the other switch signals SW [0] to SW [2] and SW [4] are deactivated to a low level. Is done. When the input is “110”, only the switch signal SW [4] is activated to a high level, and the other switch signals SW [0] to SW [3] are deactivated to a low level.

(Comparison)
Next, differences from the method described in Patent Document 1 (Japanese Patent Laid-Open No. 2010-21918) which is a conventional document will be described.

  In Patent Document 1, in order to increase the feedback rate of the amplifier, the stage gain is relaxed to 1/2 or the like without changing the number of turns or the number of bits. On the other hand, in the present embodiment, the stage gain is not changed, and the number of turns is increased by a factor of about two to enhance the tolerance against the deviation of the comparator judgment point. If limited by the output amplitude of MDAC, it is ½ as well, but its purpose is very different.

The differences between the present embodiment and Patent Document 1 are summarized as follows.
(A) In Patent Document 1, the stage gain changes, but in this embodiment, the stage gain does not change.

  (B) In Patent Document 1, the feedback rate of the amplifier is relaxed. However, in this embodiment, the feedback rate of the amplifier is not relaxed. This is because in Patent Document 1, priority is given to the accuracy and power characteristics of the amplifier.

  (C) In Patent Document 1, the number of turns (the number of SADC bits) is not changed, but in this embodiment, the number of turns (the number of bits) is increased.

  (D) In Patent Document 1, the accuracy of the comparator is deteriorated, but is not changed in the present embodiment. In this embodiment, priority is given to the accuracy of the comparator.

  (E) In Patent Document 1, the number of comparators does not change, but in the present embodiment, the number of comparators increases about twice.

  FIG. 10 is a diagram illustrating the redundancy due to the difference in overlap and the difference in the input range of the next stage.

  In Patent Document 1, the overlap of the SADC output with the next stage is 1 bit, but in this embodiment, it is 2 bits.

  Further, in Patent Document 1, it is necessary to narrow the input range of the next stage to ½ in accordance with the output amplitude of the own stage being halved. On the other hand, in the present embodiment, by using the fact that the overlap is one bit larger, all outputs of −Vref to + Vref that cannot be expressed by one overlap can be expressed.

FIG. 11 is a diagram illustrating the redundancy as seen from another overlapping bit.
The left side of FIG. 11 is the present embodiment, and the right side is Patent Document 1. Both are 3 bits and the size of 1LSB does not change. The part that overlaps the next stage can be expressed by the combination of the own stage and the next stage, and considering that the next stage follows the result of the own stage, the own stage It can be said that there is freedom of expression. On the right side of FIG. 11 (Patent Document 1), since 1 bit overlaps, it can be said that there is freedom of expression for 1 LSB. On the other hand, on the left (this embodiment), since the two bits overlap, the range of expression is expanded to 0 to 3, and there is freedom of expression for 3 LSBs. Therefore, in the present embodiment, even if it deviates by 2 LSB more than Patent Document 1, correct expression can be achieved without failure due to redundancy. Since this deviation can be used as a dither or comparator offset, a large dither can be applied without increasing the accuracy of the comparator.

(effect)
As described above, according to the present embodiment, while inheriting many of the advantages of the threshold dither, the limitation on the dither amount due to the offset of the comparator can be eliminated and the linearity can be improved.

  In this embodiment, each stage except stage 8 outputs a 3-bit sub-digital signal, the transfer function gain is 2, the number of turns is 4, and the bits that overlap when error correction is performed with an adjacent stage. The number is 2 bits.

[Modification 1 of the first embodiment]
FIG. 12 is a diagram illustrating a transfer function of the SADC according to the first modification of the first embodiment. FIG. 13 is a diagram illustrating a transfer function of the MDAC according to the first modification of the first embodiment.

  The SADC has determination points at ± Vref / 4 and ± Vref / 2 with respect to the input voltage Vin, and the output Do is expressed by the following equation.

Do = 0 (Vin <−Vref / 2)
Do = 1 (−Vref / 2 <Vin <−Vref / 4)
Do = 2 (−Vref / 4 <Vin <0)
Do = 3 (0 <Vin <Vref / 4)
Do = 4 (Vref / 4 <Vin <Vref / 2)
Do = 5 (Vref / 2 <Vin)
Since the value of the output SDo of SADC varies between ± Vref / 4 and ± Vref / 2, the transfer function of MADC has a polygonal line characteristic as shown in FIG.

  In this modification, each stage except stage 8 outputs a 3-bit sub-digital signal, the transfer function gain is 2, the number of turns is 5, and the number of bits that overlap when error correction is performed with an adjacent stage. Is 2 bits.

[Modification 2 of the first embodiment]
In the first embodiment, the gain of the stage is 2, but in this modification, a case where the gain of the stage is 4 will be described.

  FIG. 14 is a diagram showing a transfer function of SADC when the stage gain is 4. FIG. FIG. 15 is a diagram showing a transfer function of MADC when the stage gain is 4. FIG.

  The SADC is ± Vref × 11/16, ± Vref × 9/16, ± Vref × 7/16, ± Vref × 5/16, ± Vref × 3/16, ± Vref × 1/16 with respect to the input voltage Vin. There is a decision point, and the output Do is expressed by the following equation.

Do = 0 (Vin <−Vref × 11/16)
Do = 1 (−Vref × 11/16 <Vin <−Vref × 9/16)
Do = 2 (−Vref × 9/16 <Vin <−Vref × 7/16)
Do = 3 (−Vref × 7/16 <Vin <−Vref × 5/16)
Do = 4 (−Vref × 5/16 <Vin <−Vref × 3/16)
Do = 5 (−Vref × 3/16 <Vin <−Vref × 1/16)
Do = 6 (−Vref × 1/16 <Vin <Vref × 1/16)
Do = 7 (Vref × 1/16 <Vin <Vref × 3/16)
Do = 8 (Vref × 3/16 <Vin <Vref × 5/16)
Do = 9 (Vref × 5/16 <Vin <Vref × 7/16)
Do = 10 (Vref × 7/16 <Vin <Vref × 9/16)
Do = 11 (Vref × 9/16 <Vin <Vref × 11/16)
Do = 12 (Vref × 11/16 <Vin)
The value of the SDo output Do varies with Vref × 11/16, ± Vref × 9/16, ± Vref × 7/16, ± Vref × 5/16, ± Vref × 3/16, and ± Vref × 1/16. Therefore, the transfer function of MADC has a broken line characteristic as shown in FIG.

  FIG. 16 is a diagram showing the configuration of the SADC when the stage gain is 4. As shown in FIG. FIG. 17 is a diagram showing the configuration of the MADC when the stage gain is 4. FIG. 18 is a diagram illustrating the configuration of the reference voltage generation unit when the stage gain is 4. In FIG.

  In this modification, each stage except stage 8 outputs a 4-bit sub-digital signal, the transfer function gain is 4, the number of turns is 12, and the number of bits that overlap when error correction is performed with an adjacent stage. Is 2 bits.

[Modification 3 of the first embodiment]
In this modification, the modification 2 of the first embodiment is further modified to increase the number of turns.

  FIG. 19 is a diagram illustrating a transfer function of the SADC when the stage gain is 4 and both ends are folded. FIG. 20 is a diagram showing a transfer function of MADC when the stage gain is 4 and both ends are folded.

  The SADC is ± Vref × 11/16, ± Vref × 9/16, ± Vref × 7/16, ± Vref × 5/16, ± Vref × 3/16, ± Vref × 1/16 with respect to the input voltage Vin. There is a decision point, and the output Do is expressed by the following equation.

Do = -2 (Vin <−Vref × 15/16)
Do = −1 (−Vref × 15/16 <Vin <−Vref × 13/16)
Do = 0 (−Vref × 13/16 <Vin <−Vref × 11/16)
Do = 1 (−Vref × 11/16 <Vin <−Vref × 9/16)
Do = 2 (−Vref × 9/16 <Vin <−Vref × 7/16)
Do = 3 (−Vref × 7/16 <Vin <−Vref × 5/16)
Do = 4 (−Vref × 5/16 <Vin <−Vref × 3/16)
Do = 5 (−Vref × 3/16 <Vin <−Vref × 1/16)
Do = 6 (−Vref × 1/16 <Vin <Vref × 1/16)
Do = 7 (Vref × 1/16 <Vin <Vref × 3/16)
Do = 8 (Vref × 3/16 <Vin <Vref × 5/16)
Do = 9 (Vref × 5/16 <Vin <Vref × 7/16)
Do = 10 (Vref × 7/16 <Vin <Vref × 9/16)
Do = 11 (Vref × 9/16 <Vin <Vref × 11/16)
Do = 12 (Vref × 11/16 <Vin <Vref × 13/16)
Do = 13 (Vref × 13/16 <Vin <Vref × 15/16)
Do = 14 (Vref × 15/16 <Vin)
The value of the output SDo of SADC is Vref × 15/16, Vref × 13/16, Vref × 11/16, ± Vref × 9/16, ± Vref × 7/16, ± Vref × 5/16, ± Vref × Since it changes between 3/16 and ± Vref × 1/16, the transfer function of the MADC has a characteristic of a broken line as shown in FIG.

  In this modification, each stage except stage 8 outputs a 4-bit sub-digital signal, the transfer function gain is 4, the number of turns is 16, and the number of bits that overlap when error correction is performed with an adjacent stage. Is 2 bits.

  FIG. 21 is a diagram showing the configuration of the SADC when the stage gain is 4 and both ends are folded. FIG. 22 is a diagram showing the configuration of the MADC when the stage gain is 4 and both ends are folded. FIG. 23 is a diagram showing another configuration of the MADC when the stage gain is 4 and both ends are folded. FIG. 24 is a diagram illustrating the configuration of the reference voltage generation unit when the stage gain is 4 and both ends are folded.

[Modification 4 of the first embodiment]
This modification is a modification obtained by further modifying Modification 3 of the first embodiment.

  FIG. 25 is a diagram showing the configuration of a differential SADC when the stage gain is 4 and both ends are folded. FIG. 26 is a diagram showing the configuration of a differential MADC when the stage gain is 4 and both ends are folded. FIG. 27 is a diagram showing another configuration of the differential MADC when the stage gain is 4 and both ends are folded.

[Modification 5 of the first embodiment]
In general, when the stage except the last stage outputs an N-bit sub-digital signal, the stage gain of the transfer function is 2 ^N−2 and the number of turns is 2 ^N −4, or 2 ^N −2, or 2 ^N , or the transfer function stage gain is 2 ^Nk−2 and the number of turns is 2 ^Nk −4, 2 ^Nk −2 or 2 ^Nk . However, the integer K has a relationship of 0 ≦ K ≦ N−3, and the number of bits that overlap when performing error correction with an adjacent stage is 2 bits.

[Second Embodiment]
In the first embodiment, the dither is generated by the reference voltage generation circuit. In the second embodiment, the dither is applied to the input of the SADC.

FIG. 28 is a diagram illustrating the configuration of the pipeline ADC according to the second embodiment.
As illustrated in FIG. 28, the pipeline ADC includes a dither generation unit 102, an addition unit 410, a SADC 103, and a MADC 104.

  In the second embodiment, the reference voltage generation unit in the SADC 103 outputs 3/8 Vref as the reference voltage Vref4, outputs 1/8 Vref as the reference voltage Vref3, and outputs −1/8 Vref as the reference voltage Vref2, −3 / 8Vref is output as the reference voltage Vref1.

FIG. 29 is a diagram illustrating a specific configuration of the dither generation unit.
The dither generation unit 101 includes a random number generation circuit 411 and a DAC (Digital to Analog Converter) 412.

The random number generation circuit 411 generates a random value that varies with time.
The DAC 412 converts the generated random numerical value into an analog signal.

  The adder 410 adds the output of the DAC 402 and the input voltage Vin of the stage and outputs the result to the SADC 103.

  This input voltage Vin is the output voltage of the MDAC 104 of the previous stage when the SADC 103 is the SADC 103 of the stage 2 to the stage 8, and is input to the pipeline ADC 100 when the SADC 103 is the SADC 103 of the stage 1. Analog input voltage.

[Modification 1 of Second Embodiment]
This modification relates to dither generation different from that of the second embodiment. In this modification, dither is generated using the SADC 103.

FIG. 30 is a diagram illustrating a configuration of a stage according to the first modification of the second embodiment.
FIG. 31 is a diagram illustrating a specific configuration of the dither generation unit.

  As shown in FIG. 31, outputs of a plurality of terminals of the reference voltage generation unit in the SADC 103 are connected to the selector 423.

  The selector 423 selects one of the output of the plurality of input terminals according to the random number value output from the random number generation circuit 421, and outputs the output voltage of the selected terminal to the adding unit 410.

  The adder 410 adds the output of the selector 423 and the input voltage Vin of the stage and outputs the result to the SADC 103.

[Modification 2 of the second embodiment]
This modification relates to dither generation different from the second embodiment and modification 1. In this modification, dither is generated using element noise.

FIG. 32 is a diagram illustrating a configuration of a pipeline ADC according to the second modification of the second embodiment.
As shown in FIG. 32, the dither generation unit 430 includes an element noise generation source 431 and an amplifier 432.

  The element noise generation source 431 generates element noise. The amplifier 432 amplifies element noise.

  The adder 410 adds the amplified element noise and the input voltage Vin of the stage, and outputs the result to the SADC 103.

  In this example of displacement, since continuous numerical values are input by using element noise, the number of divisions becomes infinite, and a smoother result can be obtained.

[Third Embodiment]
In the third embodiment, the reference voltage generation unit of the first embodiment is modified.

The present SADC 103 has a configuration similar to that of the SADC in FIG.
The random number generation source 105 has the configuration of FIG. 8 as in the first embodiment. The random number generation source 105 generates switch signals SW [0] to SW [4] for controlling a plurality of switches in the reference voltage generation unit 106 based on random number values that change with time.

FIG. 33 is a diagram illustrating the configuration of the reference voltage generation unit of the third embodiment.
The reference voltage generation unit includes a plurality of resistors R connected in series between the first potential (V1) and the second potential (V2), and between the first potential (V1) and the reference voltage (+ Vref). Outputs a plurality of resistors R connected to each other, a plurality of resistors R connected between the second potential (V2) and the reference voltage (−Vref), and a plurality of reference voltages Vref4, Vref3, Vref2, and Vref1. And a switching circuit 621, 622.

  The switch circuit 621 includes a plurality of switches each controlled by switch signals SW [0] to SW [4]. Each switch is connected to a terminal that internally divides a path between the reference voltage (+ Vref) and the first potential (V1). Therefore, the first potential (V1) is set by applying the switch signals SW [0] to SW [4] to the switch circuit 621.

  The switch circuit 622 includes a plurality of switches each controlled by switch signals SW [0] to SW [4]. Each switch is connected to a terminal that internally divides a path between the reference voltage (−Vref) and the second potential (V2). Therefore, the second potential (V2) is set by applying the switch signals SW [0] to SW [4] to the switch circuit 622.

  In the present embodiment, as in the first embodiment, dither generation is performed by the reference voltage generation circuit. However, as in the first embodiment, many taps are not provided in the ladder resistor, but FIG. As shown in FIG. 6, the dither value can be switched by changing the resistance value of the resistor connected to the reference voltage with the switch and shifting the internal dividing point of the tap.

[Fourth Embodiment]
In this embodiment, by adding a DEM logic circuit to the output of the SADC, the step mismatch between the turns is averaged and the INL is improved.

FIG. 34 is a diagram showing a transfer curve of MADC.
As shown in FIG. 34, there are different portions in the amount of folding at the ADC determination point, and it appears that the entire surface is wavy.

FIG. 35 shows input / output characteristics of a conventional pipeline ADC.
As shown in FIG. 35, in the input / output characteristics without dither, the size of the generated step differs depending on the location.

  On the other hand, when dither is applied, the step is diffused but deviates from an ideal straight line.

  FIG. 36 is a diagram illustrating an image of an INL curve when dither is applied. Since dither is applied, the result is better than when dither is not applied, but it can be seen that INL is wavy.

In the present embodiment, the above problem is improved.
FIG. 37 is a diagram illustrating a configuration of a stage according to the fourth embodiment.

  As shown in FIG. 37, among the capacitors constituting the MADC 104, a plurality of capacitors C1, C2, C3, and C4 are connected to the DAC, and each of the capacitors varies independently, so that the generated step varies. .

  In FIG. 37, by adding a DEM logic circuit 711 between the output of the SADC 103 and the input of the MADC 104, the variation in capacitance is made uniform.

  As a result, as shown in FIG. 38, the amount of folding at the ADC determination point becomes uniform. As shown in FIG. 39, the steps of the input / output of the ADC are also equalized. When dithering is applied in this state, the undulation of INL is also improved as shown in FIG.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  100 Pipeline ADC, 90, 101 Error Correction Circuit, 103 SADC, 104 MADC, 105, 122, 305 Random Number Source, 106, 121, 206, 306 Reference Voltage Generation Unit, 110-113, 123-134, 210-235 , 310-335 Comparator, 102, 430 Dither generator, 410 Adder, 411, 421 Random number generator, 412 DAC, 431 Element noise source, 114, 141 Encoder, 108, 109, 135-140, 231-238 , 331 to 338 MADC decoder, 115, 422, 432 amplifier, 261 to 272 switch, 111 to 113 flip-flop, 114 decoder, 251 logic circuit, 350 differential amplifier, 501 logic.

Claims (5)

A pipeline type A / D converter for converting an analog signal into a digital signal,
Multiple stages connected in cascade,
An error correction circuit that generates the digital signal based on a sub-digital signal output from each of the plurality of stages;
When at least one of the plurality of stages outputs the N-bit sub-digital signal, the stage gain of the transfer function is 2 ^N−2 and the number of turns is 2 ^N −4 or 2 ^N -2 or 2 ^N
A pipeline type A / D converter in which the number of bits that overlap when error correction is performed with an adjacent stage is 2 bits. A pipeline type A / D converter for converting an analog signal into a digital signal,
Multiple stages connected in cascade,
An error correction circuit that generates the digital signal based on a sub-digital signal output from each of the plurality of stages;
When at least one of the plurality of stages outputs the N-bit sub-digital signal, the stage gain of the transfer function is 2 ^Nk−2 and the number of turns is 2 ^Nk −4 or 2 ^Nk −2 or 2 ^Nk , where the integer K has a relationship of 0 ≦ K ≦ N−3, and the number of bits that overlap with each other when error correction is performed is 2 bits. Pipeline type A / D converter. The stage is
The sub-digital signal corresponding to the analog signal or the sub-analog signal output from the preceding stage is generated and output to the error correction circuit, and the analog signal or the sub-analog output from the preceding stage is output. A sub AD circuit that generates a voltage selection signal according to the magnitude of the signal;
A DA circuit that generates a sub-analog signal according to the magnitude of the analog signal or the sub-analog signal and a voltage input according to the voltage selection signal generated by the sub-AD circuit, and outputs the sub-analog signal to the next stage. And
The sub AD circuit includes:
A random number generation circuit;
A reference voltage generation circuit for generating a plurality of reference voltages;
Including a plurality of reference voltages generated by the reference voltage generation circuit and a plurality of comparators for comparing the magnitudes of the analog signal or the sub-analog signal;
The reference voltage generation circuit includes:
A plurality of resistors connected in series between two reference potentials;
The plurality of terminals that output a potential internally divided between two potentials by the plurality of resistors, and the plurality of terminals are classified into a plurality of groups,
A plurality of switch circuits provided for each group, selecting one of the terminals belonging to each group, and outputting the potential of the selected terminal as a reference voltage;
The pipeline type A / D converter according to claim 1, wherein the random number generation circuit generates a switch signal for controlling the plurality of switch circuits based on a random number value that changes with time. The stage is
The sub-digital signal corresponding to the analog signal or the sub-analog signal output from the preceding stage is generated and output to the error correction circuit, and the analog signal or the sub-analog output from the preceding stage is output. A sub AD circuit that generates a voltage selection signal according to the magnitude of the signal;
A DA circuit that generates a sub-analog signal according to the magnitude of the analog signal or the sub-analog signal and a voltage input according to the voltage selection signal generated by the sub-AD circuit, and outputs the sub-analog signal to the next stage. When,
A dither generator that converts a random value that changes with time into an analog signal and outputs the analog signal;
An output circuit for adding the dither generator and the analog signal or the sub-analog signal;
The sub AD circuit includes:
A reference voltage generation circuit for generating a plurality of reference voltages;
3. The pipeline A / D converter according to claim 1, further comprising a plurality of reference voltages generated by the reference voltage generation circuit and a plurality of comparators for comparing magnitudes of the analog signal or the sub-analog signal. The stage is
The sub-digital signal corresponding to the analog signal or the sub-analog signal output from the preceding stage is generated and output to the error correction circuit, and the analog signal or the sub-analog output from the preceding stage is output. A sub AD circuit that generates a voltage selection signal according to the magnitude of the signal;
A DA circuit that generates a sub-analog signal according to the magnitude of the analog signal or the sub-analog signal and a voltage input according to the voltage selection signal generated by the sub-AD circuit, and outputs the sub-analog signal to the next stage. And
The sub AD circuit includes:
A random number generation circuit;
A reference voltage generation circuit for generating a plurality of reference voltages;
Including a plurality of reference voltages generated by the reference voltage generation circuit and a plurality of comparators for comparing the magnitudes of the analog signal or the sub-analog signal;
The reference voltage generation circuit includes:
A plurality of resistors connected in series between the first potential and the second potential;
A terminal for outputting the plurality of reference voltages;
A plurality of switches for setting the first potential and the second potential;
The pipeline type A / D converter according to claim 1, wherein the random number generation circuit generates a switch signal for controlling the plurality of switches based on a random number value that changes with time.

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