JP2009516433A - Analog-to-digital converter with dither - Google Patents

Abstract

An analog-to-digital converter is provided, the converter being an array of capacitors for sampling the input, each capacitor controllably connecting a terminal of the capacitor to a first reference voltage or a second reference voltage. An array of capacitors having at least one associated switch for; and a sequence generator for generating a sequence of bits, wherein the output of the sequence generator is output during sampling of the input to the array of capacitors. Supplying to a switch of a group of capacitors controls whether a given capacitor in the first group is connected to the first reference voltage or the second reference voltage by its associated switch.

Description

  The present invention relates to an apparatus and method for applying dither to an analog-to-digital converter, and an analog-to-digital converter including such an apparatus.

An analog-to-digital converter should not only have good resolution, but also should exhibit good linearity. The resolution of a converter is indicated by the number of bits it converts. Typical high performance converters exhibit 14 or 18 bit resolution. However, the user should also pay attention to other performance metrics, such as integral non-linearity: INL and differential non-linearity: DNL. Differential nonlinearity refers to the relative step size of each discrete code generated by an analog to digital converter. In an ideal world, when a ramp input voltage is applied to an analog-to-digital converter, each transition from one digital code to the next should be equally spaced along an analog ramp. is there. However, differential nonlinearity errors can cause these transitions to be non-equally spaced. It is useful to think of the analog values as being classified into different digital “bins”, so each bin should be the same size. Differential nonlinearity can be represented by the size of the least significant bit. Using the description of DNL shown in FIG. 2, it can be seen that a transducer with a differential nonlinearity greater than −1LSB (−1LSB <DNL error) is guaranteed to have no missing code. For optimal DC performance, the DNL error must be zero for all codes.
Although manufacturers take great care to minimize differential nonlinearity, it is almost inevitable that some DNL errors remain due to process variations and physical accuracy limitations when manufacturing devices.

  US 5,010,339 discloses an arrangement in which a standard analog-to-digital converter is coupled in an additional external circuit including an adder in front of the analog-to-digital converter. The adder receives the signal to be converted at a first input and the output of the digital to analog converter at a second output. The digital-to-analog converter is driven to apply a varying but known voltage to the analog signal before conversion. This allows repeated input voltage signals of the same value to be converted in different bins of the analog to digital converter, thereby minimizing DNL errors due to unevenly spaced bin widths. However, this circuit increases the complexity of the analog-to-digital converter, and additional circuitry can be a source of offset and gain errors.

  US 7,015,853 discloses a converter provided with a switched capacitor array of N capacitors. The K capacitors can be switched to + Vref during sampling of the remaining (N−K) capacitor input signals. When the successive approximation conversion is initiated, all N capacitors are involved in the search process, so that (NK) capacitors used to sample the input and those K samples that do not sample the input. Charge redistribution occurs between the capacitors. This necessarily results in a gain error in the circuit. In addition, the dither is unipolar (ie, only a single sign).

SUMMARY OF THE INVENTION According to a first aspect of the invention, an analog to digital converter is provided, the converter being a first group of capacitors for participating in successive approximation conversion, each capacitor being a terminal of the capacitor. Said first group of capacitors having at least one associated switch for controllably connecting a first reference voltage or a second reference voltage to a first reference voltage or a second reference voltage; Said second group of capacitors having respective switches for connection to a fourth reference voltage, and a sequence generator for generating a sequence of bits, wherein at least some of the capacitors of the first group of capacitors During sampling of the input to or during sample conversion, the output of the sequence generator is fed to a switch of a second group of capacitors. , A predetermined capacitor in the second group, controlling whether to connect to a third reference voltage or the fourth reference voltage by its associated switch, thereby applying a dither to the analog-digital converter.

In this way, it is possible to provide a controlled perturbation to the sampled input using a capacitor. Multiple transformations of substantially the same input value can result in input values being assigned to different “bins” during the transformation process due to different perturbation results applied to each individual sampling point. This creates an improvement in DNL error, greatly reduces the possibility of missing codes, and effectively guarantees that there are no missing codes in a well-designed transducer.
The third and fourth reference voltages may be equal to the first and second reference voltages.
The second group of capacitors are preferably not involved in the SAR conversion.

However, the capacitors in the second group of capacitors may be used in the averaging step, in which one or more averaging transformations are performed and the previous transformation results (eg, conventional SAR transformations). , Obtained for a continuous set of capacitors CN to C1 and tests, but with dither applied arbitrarily) by multiple correction conversions, where the change in conversion results that each correction conversion can produce is generally small For example, about 1 or 0.5 LSB.
The first group of capacitors is included in the SAR transformation, so if, for example, the converter provides an Nth bit result, the first group of capacitors has N capacitors, in addition to redundancy. There are any additional capacitors that can be provided to allow.

Advantageously, several capacitors of the array are used to sample the input signal and participate in its conversion.
Preferably, the second group of capacitors is selected from the lowest capacitors in the capacitor array.
Advantageously, a plurality of capacitors having a bit weight substantially in the range of 0.5-2 LSB are provided as additional capacitors in the switched capacitor array, and these capacitors constitute a second group of capacitors.

Advantageously, the second group of capacitors is an integral part of the capacitor array, but alternatively they may be formed in a sub-array connected to the main array of capacitors via a coupling capacitor. The main array may itself be a segmented array.
Advantageously, the sequence generator generates a random or pseudo-random sequence for controlling the switches of the second group of capacitors. The use of a random or pseudo-random sequence helps to avoid system errors that can result in a short loss of some codes in worst case scenarios.

Advantageously, an arithmetic unit is provided, which receives the bit sequence from the sequence generator and thus has information about the magnitude of the perturbation applied to the input signal. The arithmetic unit also receives the conversion code from the switched capacitor array and applies compensation to the code from the switched capacitor array to account for the applied perturbations.
The sequence generator can generate a first switch control word that is used in the setup phase that can occur during sampling of the input signal, and can generate a second switch control word that is used during the conversion. The difference in the values of these words produces dither, which is bipolar, i.e., the dither can take either a positive or negative sign.

According to a second aspect of the present invention, an analog-to-digital converter is provided, the analog-to-digital converter comprising:
A switched capacitor array used to sample the analog values and convert the analog values to digital values; and a switched capacitor digital to analog converter responsive to the control word;
Where after the input signal is sampled into the switched capacitor array, the switched capacitor digital-to-analog converter is operated to create a known perturbation on the charge stored in the switched capacitor array, or the analog-digital A known perturbation is applied to the converter's comparator.

Preferably, the switched capacitor digital-to-analog converter is implemented using the same technology as the switched capacitor array and may optionally be an integral part of the switched capacitor array.
According to a third aspect of the present invention, there is provided a method of applying dither to an analog to digital converter, wherein the converter includes a first array of capacitors, each capacitor having a first reference to the capacitor end. At least one associated switch for controllably connecting to a voltage or a second reference voltage, and wherein the capacitors of the first array are under the control of a successive approximation controller during the successive approximation conversion. Switched between one and a second reference voltage; wherein a second array of capacitors is provided, the second array of capacitors having a respective switch, the input of at least one capacitor in the array of capacitors During sampling or sample conversion, a perturbation control word is provided to the switch of the capacitor of the second array and is in the second array Yapashita by its associated switch for controlling whether to connect to the first reference voltage or the second reference voltage.

  According to a fourth aspect of the present invention there is provided a method for adding dither to an input signal that is digitized by an analog to digital converter, wherein the analog to digital converter is for sampling an input value, and A switched capacitor array for converting an input value to a digital value, wherein the analog to digital converter further includes a switched capacitor digital to analog converter responsive to a control word, wherein the input signal is switched to the switched capacitor array; After sampling, the switched capacitor digital-to-analog converter operates to apply a known perturbation to the charge stored in the switched capacitor array, to the voltage generated in the array, or to the comparator of the analog-to-digital converter. create.

According to a fifth aspect of the present invention there is provided a method for improving the differential nonlinearity of an analog to digital converter, said method comprising:
a) generating a dither value;
b) applying the dither value to a comparator, thereby perturbing the comparison threshold of the comparator; and c) performing one or more analog-to-digital conversion steps;
Including the steps.

  Aspects of the present invention will be further described by way of non-limiting examples and with reference to the accompanying figures.

DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION Ideally, the analog to digital converter should be linear. Accordingly, as shown in FIG. 1, the digital code XX001 (where XX represents the bits preceding, these states are independent of the present discussion) is the input voltage _{V in} is 0.5 to 1.5 arbitrary units Range. Similarly, XX010 is in the range of input voltage 1.5-2.5. Each digital code should be at the same interval in the analog domain, ie over one voltage input unit as shown in FIG. However, as shown in FIG. 1, a DNL error occurs, and as a result, the code XX011 becomes an input range of 2.25 to 4.25 instead of the original 2.5 to 3.5. This means that some input values of Vin _in the range greater than 1.5 and less than 2.5 are correctly converted as XX010, and some input voltages in this range are incorrectly converted as XX011. means. In the example shown, the code XX100 is missing and the code XX101 is in the range of 4 to 5.5. The subsequent code shown in FIG. 1 covers their correct range.

  It is useful to further consider the DNL error. FIG. 2 shows a series of digital output codes for analog input voltages. In this example, the first digital output code, Code 1, spans exactly the correct range, 1LSB, so that its DNL error is zero. The next code, Code 2, spans only half of the analog input voltage that should be in that range. Code 2 has a DNL of -0.5LSB. The third code, code 3, spans a range that is too wide, in this example spans a range corresponding to 1.5 LSB, and thus has a DNL of +0.5 LSB. The fourth code, code 4, spans only the range corresponding to 0.25LSB, and thus has a DNL of -0.75LSB. Interestingly, the fifth code is missing and the sixth code, code 6, spans the correct length of 1 LSB in the analog voltage range, so its DNL = 0, but its expectation It is observed that there is a 1.75 LSB offset from the applied voltage range.

By adding known dither to the operation of the analog-to-digital converter, the missing code problem can be reduced and the differential nonlinearity error can be improved. This is because when converting a fixed input voltage to which dither is applied, the conversion result is distributed to multiple conversion bins rather than consistently entering the same bin.
As a prior art solution, as described in US 5,010,339, if the input voltage is sampled and then added to the dither voltage using an adder and then sent to the analog-to-digital converter, an additional analog The need for elements increases the complexity of the overall converter circuit. Furthermore, the DAC and adder used to generate the analog dither voltage can be a source of noise, offset and gain errors, which can degrade other aspects of the analog to digital converter performance. Even if the elements are integrated into the ADC, implementing the dither functionality is an expensive method in terms of silicon area used and power consumption of the ADC. In addition, in US 5,010,339 special care must be taken to prevent the sum of the input voltage and dither from exceeding the full scale range of the ADC.

  The inventors have realized that the switched capacitor structure used in many successive approximation converters can be used to load a perturbation or dither into the sampling signal. Depending on the structure of the switched capacitor array, the present invention may be implemented without modifying the switched capacitor array, particularly depending on whether or not it has error correction capacitors therein. However, in some cases, implementations of the present invention can be facilitated by the formation of multiple low value (ie, near 1 LSB) additional capacitors that can be used as a source of dither. The formation of an additional capacitor is advantageous because it may be used later to improve the signal-to-noise ratio of the converter by obtaining multiple conversion results, which is USPTO US Applicant's joint patent application, filed 11 / 226,071, is described in the name “analog-to-digital converter”, which is incorporated herein by reference.

  FIG. 3 is a schematic diagram of an analog / digital converter constituting an embodiment of the present invention. Typically, an analog to digital converter includes two switched capacitor arrays, one “P-ADC”, generally indicated at 2, connected to the non-inverting input 4 of the comparator 6. An equivalent switched capacitor array “N-DAC” is connected to the inverting input 8 of the comparator 6. Both arrays are identical and only one is listed for simplicity. In fact, the operation of the analog-to-digital converter can be more easily understood by omitting the “N-DAC” array and assuming that the inverting input 8 is connected to a reference voltage such as ground.

  In general, an N-bit converter, such as a 14-bit converter, has 14 binary weighted capacitors therein. The lowest capacitor C1 has a capacitance value of 1 arbitrary unit, the next highest capacitor C2 has a value of 2 arbitrary units, the next highest capacitor C3 has a value of 4 arbitrary units, and the next highest capacitor C3. The upper capacitor C4 has a value of 8 arbitrary units, and finally the CN (eg C14) capacitor has a value of 8,192 units. This actually indicates a very wide scaling from the smallest capacitor to the largest capacitor, and it is difficult to maintain accurate scaling over the entire 14-bit range. To overcome this problem, switched capacitor arrays can be implemented as segmented arrays. Therefore, as shown in FIG. 3, the uppermost capacitor is provided in the main array or the main array indicated by 2, and the lowest capacitor is provided in the sub-array indicated by 10. Capacitors in any array are binary weighted relative to each other (although other weights with radix <2 are possible), but the scaling between arrays can be broken, and the correct relative size of the capacitors is Is recovered by appropriate sizing of the coupling capacitor 12 that connects to the main array 2.

  Therefore, considering a 14-bit analog-to-digital converter, the lowest seven capacitors C1 to CA (A = 7) can be arranged in the subarray 10, and the highest capacitors CB to CN (B = 8 and N = 14) can be arranged in the main array 2. Within sub-array 10, the smallest capacitor C1 has a value of 1 arbitrary unit, while the largest capacitor CA in this array has a value of 64 arbitrary units. Similarly, in the main array, the minimum capacitor CB has a value of 1 arbitrary unit, and the maximum capacitor CN has a value of 64 arbitrary units. Thus, the scaling problem of capacitors in any array is greatly reduced, and the total area of silicon in the integrated circuit required by the capacitor array is also greatly reduced. In the context of a 16-bit converter, 8 capacitors are provided in the subarray 10 and 8 capacitors are provided in the main array 2. The relative size within each array only varies by a factor of 1 to 128. The converter designer does not have to divide the capacitors equally between the sub-array 10 and the main array 2. For example, the main array 2 may have more capacitors than the sub-array 10.

For a 14-bit DAC with no error correction capacitor, the relative size of the capacitor is:
C1 = 1, C2 = 2, C3 = 4, C4 = 8, C5 = 16, C6 = 32, C7 = 64
Coupling capacitor 12 = 1
C8 = 1, C9 = 2, C10 = 4, C11 = 8, C12 = 16, C13 = 32, C14 = 64.
Here, the capacitors C1 to C7 are in the sub-array, and the capacitors C8 to C14 are in the main array.
A similar scheme applies to a 16-bit ADC, except that each array has an additional 128 unit capacitor.

Each capacitor C1-CN has an associated switch S1-SA and SB-SN, which switches from the first plate (the bottom plate of the capacitor, as depicted in FIG. 3) to the first reference. It operates to connect to either the voltage “V _refp ” or the second reference voltage “V _refn ”. In general, V _refn corresponds to the ground. The capacitors CB to CN of the main DAC array 2 can be further connected to the signal path “A _in ” by the switches SB to SN, respectively, and the input voltage is sampled into the capacitors CB to CN. During sampling, switch 22 is closed, connecting the second plate of capacitors (the top one as shown in FIG. 3) to ground or other suitable reference voltage such as 1 / 2V _ref . The switch 22 is always open in other cases. In a segmented converter of the type shown in FIG. 3, the input voltage need not be sampled into capacitors C1-CA of subarray 10.

  As a result of sampling only the main capacitor array, a gain error occurs. This can be corrected by adding an additional unit value capacitor to correct for not sampling into the subarray. This additional capacitor can be referred to as the sampling capacitor because it is only used in the sampling phase and, as shown below, the sum of the bit weights of the subarray capacitors plus 1LSB (subarray error This is because it has an equivalent bit weight equal to (excluding this if there is a correction bit). It is known to those skilled in the art to correct gain errors using segmented arrays and sampling capacitors.

ここで、ＣＣ＝結合キャパシタ
ＳＣ＝サンプリングキャパシタ Thus, in a 16-bit ADC, has:

Where CC = coupling capacitor SC = sampling capacitor

When the input voltage A _in is sampled by the capacitors CB to CN, the switch 22 is opened, thereby capturing the charges of the capacitors of the main array 2. The successive approximation search can then be started. Iterative search strategies are known to those skilled in the art, so only minimal mention is necessary here. Basically, all switches S1-SN switch to connect the capacitor to the V _refn reference voltage. The top capacitor CN is then tested and connected to the voltage reference V _refp using its switch SN. The capacitors of the array effectively form a capacitive voltage divider, with the result that the voltage developed at the non-inverting input 4 changes. Comparator 6 tests whether this voltage is greater or less than the voltage at its inverting input. Depending on the result of the comparison, the bit corresponding to the capacitor CN is maintained (ie set) or discarded (reset). If the analog value to be converted is in the upper half of the conversion range, the bit CN is maintained, otherwise it is discarded. The result of the first bit attempt is carried forward to the next most significant bit attempt C (N-1), which is set and tested in a similar manner, then this result is again until the last bit C1 is tested. Carry over through successive approximation search.

It is known to create additional error correction capacitors in the array to enhance the performance of analog to digital converters and increase the overall conversion speed. These capacitors provide extra “weights” in the array, allowing the successive approximation search to recover from erroneous decisions, and as a result, from switching the switches S1-SN to capturing the decision of the comparator 6. The settling time is considerably shortened.
Capacitors C1-CN form a first group of capacitors involved in the successive approximation algorithm.

Many modern analog-to-digital converters include error correction capacitors and can recover from inaccurate decisions. In one example of the present invention, the effective weight of the capacitor takes the following pattern (as explained by rescaling in subarray 10):
32768, 16384, 8192, 4096, 2048, ± 1024, 1024, 512, 256, 128, ± 64, 64, 32, 16, 8, ± 4, 4, 2, ± 1, ± 1, 1, ± 0. 5, ± 0.5, ± 0.5, ± 0.5, ± 0.5, ± 0.5, ± 0.5.

In this preferred embodiment, seven additional capacitors AC1-AC7 having a weight of ± 0.5 are made, but for simplicity only three of these capacitors AC1-AC3 are shown in FIG. Has been. These additional capacitors AC1-AC7 are considered as a second group of capacitors and are used to apply dither to the ADC. The additional capacitors AC1 to AC7 are not switched under the control of the SAR controller and therefore participate in bit trials after obtaining the analog value to be converted and prior to the first analog to digital conversion. There is no.
The seven additional capacitors AC1-AC7 in the preferred embodiment, however, are used again in other processes to improve the signal to noise ratio of the analog to digital converter, which process does not form part of the present invention. . Therefore, for simplicity, only one capacitor AC1 needs to be provided in the P-DAC array, and this additional 1/2 LSB capacitor only needs to have a value of 0.5LSB.

For example, the formation of an error correction capacitor having a value of ± 1024 is known to those skilled in the art. In a preferred embodiment, a capacitor having a value of ± 1024 consists of two capacitors each having a weight of 1024 bits. Analog inputs are not sampled into these capacitors. During the sampling phase, the first of these capacitors is connected to V _refp and the second capacitor is connected to V _refn . During the bit trial, the second of these capacitors is _disconnected from V _refn , connected to V _refp and tested for a weight of ₊₁₀₂₄ . If the bit is allowed, both the first and second capacitors are left connected to V _refp . If the bit is rejected, both the first and second capacitors are disconnected from V _refp and connected to V _refn which generates a negative step of _{-1024 LSB} .

As previously mentioned, during the sampling phase, capacitors CB-CN have their first plates (the bottom plate shown in FIG. 3) connected to V _{refn of the} P-DAC. The corresponding capacitors (not shown in detail in FIG. 3) are connected to V _refp through their electrically controllable switches, the first plate of the capacitors of the subarray need to be connected to any particular reference voltage It should be pointed out that this is because we are only interested in the change in charge propagating through the coupling capacitor 12 from the subarray 10 to the main array 2.

We have introduced the dither to the analog-to-digital converter as follows, i.e., changing the switch position during sampling, so that some of the lower capacitor bit weights of the subarray 10 are This was achieved by connecting the first plate to V _refp instead of V _refn during the sampling phase. If the switch is reconnected to V _refn at some point during the successive approximation conversion process, it is not necessarily so, but preferably charge redistribution occurs before the most significant bit CN is tested. Thus, a negative perturbation is generated in the voltage at the common rail 14 of the sub-DAC 10, so that a negative perturbation is introduced into the main array 2 via the coupling capacitor 12, so that the voltage sampled into the main array 2 is slightly less than Causes a change that can be known. By applying the same dither technique to the N-DAC subarray, a positive perturbation is generated on the sampled input. Dither can be introduced by changing the switches S1-SA of any capacitor C1-CA of the subarray, but it is generally preferable to keep the dither small. Thus, selective switching of capacitors in the sub-capacitor array can be used to perturb the voltage sampled in the main capacitor array during the sampling phase, thus complicating the analog signal path in the converter. Without introducing positive or negative dither into the analog-to-digital converter.

  As pointed out above, the dither preferably has a resolution of up to 0.5 LSB. Therefore, it is desirable to form at least one additional capacitor AC1 having a value of 0.5LSB. Such a capacitor can be formed by connecting two units (1 LSB) in series with the capacitor. This additional capacitor AC1 may then be used with a few lower value capacitors, eg, subarrays C1 and C2, which have dithers in the range of 0--3.5LSB, Used to add to subarray 10. Similarly, N-DAC sub-array capacitors can be used to add dither in the range of 0 to +3.5 LSB.

  As shown in FIG. 3, if a plurality of additional capacitors AC1-AC3 are provided, these may be used alone or in addition to the low weight capacitors of the sub-DAC to achieve dither functionality. Use. In one aspect of the invention, seven additional capacitors AC1-AC7, each having a value of 0.5LSB, are implemented in the sub-DAC. For convenience, the first additional capacitor AC1 is switched individually to form a 0.5 LSB dither capacitor. The two capacitors AC2 and AC3 are switched simultaneously to synthesize a 1LSB dither capacitor, and the remaining capacitors AC4 to AC7 are simultaneously switched to synthesize a 2LSB dither capacitor. The switches SAC1, SAC2, etc. are driven in response to the pseudorandom numbers generated by the pseudorandom number generator 40. This randomly generates a number between -3.5 and +3.5, and switches the sub DAC 10 associated with the P-DAC and the corresponding sub DAC (not shown) associated with the N-DAC. Control.

For the embodiment with only one additional capacitor AC1, the pseudorandom number generator 40 controls the switches SAC1, S1, S2, S3, etc. Thus, to introduce a negative dither value of -5LSB, during the sampling phase, switches S1 and S3 are connected to V _{refp of} P-DAC, S2 is connected to V _refn and N-DAC as shown in FIG. A similar switch in the sub-array (omitted for clarity in the figure) is connected to V _refp . When the sampling phase is complete, switch 22 is opened followed by switches SB-SN to disconnect the first plates of capacitors CB-CN from the analog input signal. The switches SB-SN can then be set to the initial successive approximation state to prepare for the most significant bit trial. As pointed out earlier, when switches S1 and S3 are _reconnected to V _refn , a negative perturbation is introduced into the sampled voltage on main array 2.

Similar considerations apply to embodiments with additional capacitors, eg AC1-AC7, but for scaling purposes, in this case pseudo-random -5 is 0.5 LSB capacitor AC1, and capacitors AC4-AC7. Operate the switch associated with the composite 2LSB capacitor formed by the -2.5LSB dither.
In either case, bit trials are performed to the end, and the result of the successive approximation conversion is passed to the adder 42 by the successive approximation controller 44. The adder then corrects the result to account for the dither size applied to the sampled signal after sampling is complete.

It is also clear that during sampling, all capacitors may be connected to the same reference voltage, and once the sampling phase is complete, some of the capacitors are switched in response to a pseudo-random number generator. The switching can occur before the bit trial begins or during the bit trial.
Furthermore, since the sampled charge is not lost from the capacitor array, two or more conversions can be performed after a single sampling event to completely or partially reconvert some of the least significant bits. Well, here these transformations are associated with one sampling event, but different dithers can be applied in each of these transformations.

  Thus, it can be seen that the present invention can apply dither to the sampled voltage without introducing additional elements in the analog signal path. Furthermore, the dither can be applied without creating any additional elements in the analog to digital converter. However, in some implementations of the present invention, additional capacitors may be made in the sub-array, which can be conveniently used to apply dither less than 1 LSB.

Sub-LSB capacitance can be provided very easily if additional capacitors are made. In the given example, the minimum capacitance produced is 0.5 LSB, but smaller capacitances can be easily created using unit size capacitors that are installed during the fabrication of the analog to digital converter. Therefore, a 1/3 LSB capacitor can be manufactured by connecting three unit capacitors in series. Similarly, a 1/4 LSB capacitor can be made by connecting 4 unit capacitors in series, a 1/5 LSB capacitor can be made by connecting 5 unit capacitors in series, and so on. This shows that the dither can easily leave the permutation of the nominal binary weights of the capacitor values.
As pointed out earlier, the dither capacitor need not necessarily be an additional capacitor, but could be selected from the capacitors of the sampling and conversion switched capacitor array. Furthermore, although this technique has been described with respect to segmented ADCs, it is equally applicable to non-segmented arrays. Therefore, DNL errors can be corrected by using capacitors present in the array or by adding a few extra capacitors. This provides a solution that is inexpensive and consumes low power and has good suitability for ADC design.

  The arrangement shown in FIG. 4 is a modification of that shown in FIG. 3 and is involved in successive approximation conversion, and is provided in the main array. The capacitors C1 to CN generally indicated by 80 are the first ones provided with the lowest capacitors C1 to CA. 1 capacitor array 82, and second capacitor array 84 provided with uppermost capacitors CB to CN. These arrays are coupled through a coupling capacitor 86. Capacitors AC1 to ACN used to supply dither are provided in subarray 90, which is coupled to main array 80 via a further coupling capacitor 92. As before, the switches for capacitors AC1-ACN are responsive to pseudorandom number generator 40, while the switch for controlling the connection of the lower plate to capacitors C1-CN is responsive to SAR controller 44.

In a further aspect of the present invention shown in FIG. 5, additional capacitors AC1, AC2, AC3, etc. are formed in subarray 100, and the lower plate of the capacitors is connected via respective switches that operate under the control of pseudorandom number generator 40. Dither criteria D _ref1 and D _ref2 can be combined and these are not absolutely necessary, but can correspond to V _refn and V _refp for convenience. However, the subarray 100 is now connected to the inverting input of the comparator 6, while the normal sampling and conversion array is connected to the non-inverting input of the comparator 6 (or vice versa). Thus, this single-ended converter does not require any change in the capacitor array used to sample and convert the input voltage sampled according to the successive approximation routine. The dither provided by the second array is used to perturb the voltage at the inverting input of the comparator 6, thereby adjusting the comparison threshold according to the dither value. With the arrangement shown in FIG. 3, a dither value is provided to the adder 42 so that the digital word forming the output result can be modified to compensate for the applied dither.

The subarray 100 is driven by the pseudorandom number generator 40, while the main array 80 is driven by the SAR controller. It will be appreciated that no modifications have been made to this single-ended signal path, rather effectively.
This concept can be further expanded as shown in FIG. 6 where a differential analog to digital converter similar to that shown in FIG. 3 is connected to the non-inverting input of the comparator 6. P capacitor array 120 and an N capacitor array 122 connected to the inverting input of comparator 6. The figure also shows alternatives, which are not mutually exclusive for applying dither. Digital-to-analog converter 130 is coupled to P-array 120 and the output of the digital-to-analog converter is summed with the voltage generated at the output of the P-array before being presented to comparator 6. If both the DAC and P array are implemented as switched capacitors, the DAC 130 can be directly connected to the P array 120 because charge transfer between these two elements causes dither. However, it should be noted that no charge is actually lost, and thus the effect of applying any dither can be undone. As an alternative, a further digital-to-analog converter 140 may be connectable to or part of the input stage of the comparator, where the output of the DAC 140 reduces the internal voltage in the comparator 6. The manner in which it is used to change, thereby shifting / changing the comparator switching threshold and applying dither.

For differential or single-ended ADCs, one or more additional inputs driven by a dedicated dither DAC can be added to the comparator. An example of such a configuration is shown in FIG. 7, which shows a first preamplifier stage of a comparator. MOS devices M1 and M2 are normal differential input devices and drive load resistors R1 and R2. P out and N The node of out may be connected to a further preamplifier stage or drive the latch directly. The gain of this preamplifier stage is equal to the value obtained by multiplying the transconductance gm1 of the input device by the load resistances of R1 and R2. Devices M3 and M4 with gm2 transconductance and associated current source I2 were added to provide the comparator with the ability to offset the input. The gates of these devices are controlled by the output of the dither DAC 150. The successive approximation algorithm functions to provide a zero differential output voltage from this stage. This is true even if dither DAC 150 provided dither offsets to devices M3 and M4. Therefore, whatever differential current is provided by devices M3 and M4, an equivalent and opposite current must be provided by input devices M1 and M2. Thus, the dither voltage _{V dither} at the output of the dither DAC, during the offset change _{V offset} at the input to consequently stage, a simple relationship is brought about, which is given by Equation 1.
V _offset / V _dither = gm2 / gm1 Equation 1

  Because the perturbation required for the preamplifier input offset is very small, devices M3 and M4 are expected to be much smaller than M1 and M2. Also, to ensure that Equation 1 is reasonably accurate, the differential voltage at the output of the dither DAC is small enough to ensure that both devices M3 and M4 operate in their linear region. To be limited. Obviously, this configuration allows for the provision of both positive and negative dither.

  FIG. 8 shows an alternative configuration where the current driven DAC 160 injects current into the output of the preamplifier. As in the previous example, the successive approximation algorithm functions to provide a zero differential output voltage from this stage. Any differential current provided by DAC2 will cause a corresponding change in the offset of the input to the preamplifier. This configuration can also be less sensitive to temperature and process changes by allowing the total current provided by the DAC to track the transconductance of the input device. In all such configurations, a digital value representing the required dither value is converted to a current change in the preamplifier input pair. This causes a change in the gate source voltage of this device (s), which is also a change in the offset to the preamplifier.

All methods of applying dither to the preamplifier offset are differential, but the same technique can be applied to single-ended configurations. Also, if the gain of the first preamplifier is reasonably controlled, dither can be applied to the preamplifier stage following the first preamplifier stage.
Thus, it is possible to improve the dynamic non-linearity of the analog-to-digital converter and thus avoid problems associated with missing codes.

It is a schematic diagram of the example of the differential nonlinearity error in an analog / digital converter. It is a graph which shows a differential nonlinearity error. It is a schematic diagram of the analog-digital converter which comprises 1 aspect of this invention. FIG. 5 shows a further embodiment where the main array of capacitors is a segmented array. FIG. 5 shows a further aspect of the invention in which dither is applied to the input of the comparator to change the comparison threshold of the comparator. FIG. 6 illustrates a further aspect of a differential ADC and an alternative method of adding dither (but not mutually exclusive). FIG. 6 is a schematic diagram of an input stage of a comparator having a mechanism for adding dither via a voltage mode DAC. FIG. 6 is a schematic diagram of an input stage of a comparator having a current mode DAC for adding dither.

Claims (25)

  An analog-to-digital converter, a first group of capacitors for participating in successive approximation conversion, each capacitor controllably connecting a terminal of the capacitor to a first reference voltage or a second reference voltage Said first group of capacitors having at least one associated switch; a second group of capacitors for applying dither, for selectively connecting said capacitors to a third reference voltage or a fourth reference voltage Said second group of capacitors, and a sequence generator for generating a sequence of bits, wherein during sampling of the input to at least some of the capacitors of the first group or samples During the conversion of the second group, the output of the sequence generator is supplied to the switches of the second group of capacitors to obtain a predetermined capacity in the second group. The controls whether to connect to a third reference voltage or the fourth reference voltage by its associated switch, thereby applying a dither, the analog-digital converter.   The analog-to-digital converter of claim 1, wherein some of the capacitors in the first group have switches operable to connect the capacitors to the input during sampling.   The analog to digital converter of claim 1, wherein the second group of capacitors has a total capacitance of less than 1% of the capacitance of the capacitor array.   The analog-to-digital converter of claim 1, wherein the second group of capacitors is part of a sub-array capacitor connected to a capacitor of the main array via a coupling capacitor.   The analog-to-digital converter of claim 1, wherein the capacitors in the array are nominally binary weighted.   The analog to digital converter of claim 1, wherein the capacitor array includes error correction bits.   The analog-to-digital converter of claim 2, wherein after sampling the input signal into the first group of capacitors, the second group of capacitors is switched to a predetermined state.   8. The analog to digital converter of claim 7, wherein after sampling, the second group of capacitors is connected to a second reference voltage.   The analog to digital converter of claim 1, wherein the sequence generator generates a pseudo-random bit sequence.   The analog to digital converter of claim 1, wherein the adder receives the conversion result from the converter and the output of the sequence generator and applies a correction based on the output of the sequence generator.   The analog to digital converter of claim 1, further comprising at least one capacitor in the second group having a value less than 1 LSB.   A P-DAC connected to the non-inverting input of the comparator and an N-DAC connected to the inverting input of the comparator, wherein at least one of the N-DAC and P-DAC is a switch whose sequence is The analog-to-digital converter of claim 1 having a second group of capacitors responsive thereto. An analog to digital converter,
A switched capacitor array used to sample the input and convert the input to a digital value; and a switched capacitor digital to analog converter responsive to the control word;
After sampling the input signal into the switched capacitor array, the switched capacitor digital-to-analog converter operates to create a known perturbation on the charge stored in the switched capacitor array or to the comparator of the analog-to-digital converter The analog-digital converter that perturbs the operation of   14. The analog to digital converter of claim 13, wherein the switched capacitor digital to analog converter is an integral part of the switched capacitor array.   14. The analog of claim 13, wherein during sampling of the signal, the digital to analog converter is set to a dither value, and then after completion of sampling, the capacitor is switched to a further value, thereby applying the dither to the sampled value.・ Digital converter.   A method of applying dither to an analog-to-digital converter, wherein the converter is a first group of capacitors, each capacitor being capable of controlling a terminal of the capacitor to a first reference voltage or a second reference voltage. Including the first group of capacitors having at least one associated switch for connecting, wherein the method sets a perturbation control word during sampling of the signal into at least one capacitor of the capacitor array or during conversion. Including supplying to a switch of the two groups of capacitors and controlling whether a given capacitor in the second group is connected to the first reference voltage or the second reference voltage by its associated switch, and here Wherein the first group of capacitors is bit-triggered by the successive approximation controller to obtain a digital value.   The method of claim 16, wherein the perturbation control word varies from one sample to the next randomly or pseudo-randomly.   A method of adding dither to an input signal to be digitized by an analog-to-digital converter, the analog-to-digital converter being used for sampling an input value and converting the input value to a digital value The analog-to-digital converter further includes a switched-capacitor digital-to-analog converter responsive to a control word, wherein the switched-capacitor digital-to-analog converter operates after sampling the input signal into the switched-capacitor array The method of creating a known perturbation in the charge stored in the switched capacitor array or in the voltage generated in the array.   The analog to digital converter of claim 1, wherein the dither is additive in some cases and subtractive in others.   A segmented analog-to-digital converter having an array of capacitors divided into a main array and a sub-array, wherein the capacitors can be connected to either a first reference voltage or a second reference voltage, where The capacitors of the main array are further connectable to an input signal and have a sequence generator for storing the input signal and generating a dither word, wherein the dither word includes at least one capacitor of the sub-array. The segmented analog-to-digital converter that controls whether it is connected to a first reference voltage or a second reference voltage and thereby applies dither to the conversion result.   21. The segmented analog to digital converter of claim 20, wherein the capacitor for applying the dither is not changed during the successive approximation conversion.   21. The segmented analog to digital converter of claim 20, wherein the dither can be subtracted from the sampled value.   14. The analog to digital converter of claim 13, wherein the digital to analog converter is set to a dither value after sampling is complete, thereby applying the dither.   The analog-to-digital conversion of claim 1, wherein a second group of capacitors are switched to a dither value during sampling of the signal and are switched to a further value after sampling is complete, thereby applying the dither to the sampled value. vessel.   The analog-to-digital converter of claim 1, wherein the second group of capacitors are switched to a dither value after sampling is complete, thereby applying the dither to the sampled value.

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