JP5904240B2 - A / D conversion circuit, electronic device, and A / D conversion method - Google Patents

Description

  The present invention relates to an A / D conversion circuit, an electronic device, an A / D conversion method, and the like.

  Conventionally, a successive approximation type A / D conversion circuit is known as an A / D conversion circuit for converting an analog signal into digital data. This successive approximation type A / D conversion circuit includes a comparison circuit, a successive approximation register, and a D / A conversion circuit, and performs A / D conversion on a signal obtained by sampling (sample-holding) an input signal by a successive approximation operation. To output digital data. As a conventional technique of such a successive approximation type A / D conversion circuit, a technique disclosed in Patent Document 1 is known.

  In such an A / D conversion circuit, most of the conversion accuracy depends on the accuracy of the D / A conversion circuit. When trying to increase the accuracy of the D / A conversion circuit, the area of the capacitor (in the case of the charge redistribution type) is caused by the area of the resistor (in the case of the ladder resistance type), and the circuit becomes large in scale. . On the other hand, if the circuit of the D / A converter circuit is devised in order to suppress an increase in the scale of the circuit, this time, DNL (Differential Non Linearity) which is differential nonlinearity or INL (which is integral nonlinearity) Due to the error of Integral Non Linearity, problems such as so-called missing codes occur.

  Even if the A / D conversion characteristics such as DNL and INL are improved, if the dynamic range of A / D conversion decreases, the performance required for A / D conversion is not desirable.

JP-A-8-321779

  According to some aspects of the present invention, it is possible to provide an A / D conversion circuit, an electronic device, an A / D conversion method, and the like that can improve the A / D conversion characteristics and suppress a decrease in dynamic range.

  One embodiment of the present invention includes a comparison circuit, a successive approximation register in which a register value is set by a comparison result signal from the comparison circuit, a control circuit that outputs successive comparison data, and the control circuit A first D / A conversion circuit for D / A converting the successive approximation data and outputting a D / A output signal corresponding to the successive approximation data, and D / A conversion of code data that changes over time A second D / A conversion circuit that outputs a code signal corresponding to the code data, and a correction unit that performs correction processing, and the comparison circuit adds the sampling signal of the input signal and the code signal A process for comparing a signal with the D / A output signal, or a process for comparing the sampling signal with an addition signal of the D / A output signal and the code signal. Output data obtained based on the successive comparison result data of the register and the code data is output as A / D conversion data of the input signal, and the correction unit performs the successive comparison result by code shift using the code data. The present invention relates to an A / D conversion circuit that performs correction processing for correcting overflow of data.

  According to one aspect of the present invention, the successive approximation data from the control circuit having the successive approximation register is input to the first D / A conversion circuit, and the D / A output signal corresponding to the successive approximation data is output. Is done. Also, code data that changes with time is input to the second D / A conversion circuit, and a code signal corresponding to the code data is output. Then, a process of comparing the sampling signal of the input signal and the addition signal of the code signal and the D / A output signal or a process of comparing the sampling signal and the addition signal of the D / A output signal and the code signal is performed. Then, output data obtained based on the successive comparison result data and the code data is output as A / D conversion data of the input signal. In this way, code shift is performed by code data that changes over time, and the A / D conversion characteristics can be improved.

  Furthermore, according to an aspect of the present invention, it is possible to prevent the sequential comparison result data from overflowing due to the code shift using such code data by the correction process. Accordingly, it is possible to suppress a decrease in dynamic range due to code shift while improving A / D conversion characteristics by code shift.

  In the aspect of the present invention, RS2 ≧ RS1 may be satisfied when the minimum resolution of the first D / A converter circuit is RS1 and the minimum resolution of the second D / A converter circuit is RS2. .

  In this way, the code shift can be realized by performing the addition process of the code signal having a magnitude equal to or larger than the minimum resolution RS1 of the first D / A conversion circuit.

  In the aspect of the invention, the correction unit may perform the correction process by correcting the code data.

  In this way, it is possible to realize the correction process for suppressing the decrease in the dynamic range due to the code shift by a simple process of correcting the code data.

  In the aspect of the invention, the correction unit may perform the correction process by correcting the code data based on the previous successive comparison result data that is the successive comparison result data in the previous A / D conversion. Good.

  In this way, by using the successive approximation result data in the previous A / D conversion and predicting whether or not the successive approximation result data in the current A / D conversion overflows, the dynamic range by the code shift is determined. It is possible to realize a correction process that suppresses a decrease in the amount of noise.

  In the aspect of the invention, the correction unit may determine that the previous A / D input voltage range corresponds to the first range on the high potential side of the A / D input voltage range. The code data is corrected so that the successive approximation result data in D conversion is shifted to the low potential side, and the previous successive comparison result data is the second potential on the low potential side of the A / D input voltage range. If the data corresponds to the above range, the code data correction processing may be performed so that the successive comparison result data in the current A / D conversion is shifted to the high potential side.

  In this way, when the previous successive approximation result data is data in the first range on the high potential side, the code data is corrected so that the successive approximation result data is shifted to the lower potential side, thereby The dynamic range can be prevented from decreasing due to the shift. When the previous successive approximation result data is data in the second range on the low potential side, the code range is corrected so that the successive approximation result data is shifted to the higher potential side, so that the dynamic range is increased by the code shift. Decrease can be suppressed.

  Further, in one aspect of the present invention, a code data generation unit that generates the code data and outputs the code data to the second D / A conversion circuit, the code data generation unit includes the previous successive comparison result data, In the case of data corresponding to a third range between the first range and the second range, the code data that is alternately positive and negative is generated to generate the second D / A conversion circuit May be output.

  As described above, the code data alternately becomes positive and negative, so that the influence of the frequency component due to the change of the code data can be reduced, and the adverse effect on the A / D conversion characteristics can be suppressed.

  In the aspect of the invention, the correction unit may include an information register that stores information about whether the previous successive approximation result data is data corresponding to the first range or the second range. But you can.

  In this way, based on the information stored in the information register, it is determined whether or not the previous successive comparison result data was data corresponding to the first range or the second range, and the current A / D is determined. It becomes possible to correct the code data in the conversion.

  In the aspect of the invention, the information register may include the first successive comparison result data for each channel of the plurality of channels when the signals of the plurality of channels are A / D converted in a time division manner. The information about whether the data corresponds to the range or the second range may be stored.

  In this way, even when the signals of a plurality of channels are A / D converted in a time division manner, whether the previous successive comparison result data of each channel was data corresponding to the first range or the second range. This is determined based on the information stored in the information register, and the code data for each channel can be corrected.

  In one aspect of the present invention, a code data generation unit that generates the code data and outputs the code data to the second D / A conversion circuit is included. Data having a different value for each one or a plurality of A / D conversion timings may be output as the code data.

  In this way, the code signal corresponding to the code data having a different value at every one or a plurality of A / D conversion timings is added, thereby realizing the code shift. Thereby, for example, the deterioration of the DNL characteristic can be diffused in the surrounding code over time, and the A / D conversion characteristic can be improved.

  In one aspect of the present invention, the code data generation unit may generate and output a prime number of code data when an oversampling A / D conversion that is a power of 2 is performed.

  In this way, it is possible to realize an improvement in A / D conversion characteristics by a synergistic effect of oversampling and code shift.

  In the aspect of the invention, the first D / A conversion circuit and the second D / A conversion circuit may be a charge redistribution type D / A conversion circuit.

  A part or all of the first and second D / A conversion circuits may be realized by a ladder resistance type.

  In the aspect of the invention, the first D / A conversion circuit includes a first capacitor array unit having a plurality of capacitors, one end of which is connected to a comparison node of the comparison circuit, and the first capacitor array. A first switch array unit having a plurality of switch elements connected to the other ends of the plurality of capacitors of the unit and controlled to be switched based on upper bit data of the successive approximation data; the comparison node and the first node; A first series capacitor provided between the second capacitor array unit, a second capacitor array unit having a plurality of capacitors having one end connected to the first node, and the plurality of capacitors in the second capacitor array unit. And a second switch array unit having a plurality of switch elements connected to the ends and controlled to be switched based on the lower-order bit data of the successive approximation data. The second D / A conversion circuit includes a second series capacitor provided between the comparison node and the second node, and a plurality of capacitors having one end connected to the second node. And a third switch array unit having a plurality of switch elements connected to the other ends of the plurality of capacitors of the third capacitor array unit and controlled to be switched based on the code data. .

  By using the first D / A conversion circuit having such a configuration, it is possible to increase the bit of A / D conversion while minimizing an increase in circuit area. Further, by using the second D / A conversion circuit having such a configuration, it is possible to realize processing for comparing the sampling signal, the D / A output signal, and the addition signal of the code signal.

  In one aspect of the present invention, the control circuit may perform the successive approximation result of the successive approximation register when a comparison process is performed between the sampling signal and the addition signal of the code signal and the D / A output signal. A process of subtracting the code data from the data may be performed.

  In this way, when comparison processing of the addition signal of the sampling signal and the code signal and the D / A output signal is performed, the code data is subtracted to output appropriate A / D conversion data. become able to.

  In the aspect of the invention, the control circuit may perform the successive comparison result of the successive approximation register when the sampling signal is compared with the D / A output signal and the addition signal of the code signal. You may perform the process which adds the said code data to data.

  In this way, when the comparison process of the sampling signal, the D / A output signal, and the addition signal of the code signal is performed, the code data addition process is performed to output appropriate A / D conversion data. become able to.

  Another aspect of the invention relates to an electronic device including any of the A / D conversion circuits described above.

  Another aspect of the present invention is an A / D conversion method in a successive approximation type A / D conversion circuit having a comparison circuit, a successive approximation register, and a D / A conversion circuit. A corresponding code signal is generated, and the sampling signal of the input signal, the addition signal of the code signal, and the D / A output signal from the D / A conversion circuit are compared, or the sampling signal and the D / A A process of comparing the A output signal and the addition signal of the code signal is performed, and output data obtained based on the successive comparison result data from the successive approximation register and the code data is converted into A / D conversion data of the input signal. And a correction process for correcting overflow of the successive approximation result data due to code shift using the code data. Related to the conversion method.

  According to another aspect of the present invention, a code signal corresponding to code data is generated, a process of comparing a sampling signal of an input signal, an addition signal of the code signal, and a D / A output signal, or a sampling signal; A process of comparing the D / A output signal and the addition signal of the code signal is performed. Then, output data obtained based on the successive comparison result data and the code data is output as A / D conversion data of the input signal. In this way, code shift is performed by code data that changes over time, and the A / D conversion characteristics can be improved.

  Furthermore, according to another aspect of the present invention, it is possible to prevent the sequential comparison result data from overflowing due to the code shift using such code data by the correction process. Accordingly, it is possible to suppress a decrease in dynamic range due to code shift while improving A / D conversion characteristics by code shift.

2 is a configuration example of an A / D conversion circuit according to the present embodiment. A first comparative example of an A / D conversion circuit. FIG. 3A to FIG. 3C are explanatory diagrams of the code shift method of this embodiment. Explanatory drawing of the problem of the reduction | decrease of the dynamic range by a code shift. Explanatory drawing of the correction method of this embodiment. FIG. 6A to FIG. 6C are explanatory diagrams of code data correction processing according to the present embodiment. The structural example of a correction | amendment part. The structural example of a code data generation part. Explanatory drawing of the method of A / D-converting the signal of a several channel by a time division. FIGS. 10A and 10B are explanatory diagrams of an oversampling A / D conversion method and a method of performing A / D conversion on a plurality of channels in a time division manner. 2 is a detailed configuration example of an A / D conversion circuit according to the present embodiment. The figure for demonstrating operation | movement of an A / D conversion circuit. A second comparative example of the A / D conversion circuit. A third comparative example of the A / D conversion circuit. Explanatory drawing about the bad influence which parasitic capacitance has. 16A and 16B are explanatory diagrams of DNL and INL. FIGS. 17A and 17B show examples of simulation results of DNL. 2 is a configuration example of a fully differential A / D conversion circuit of the present embodiment. 1 is a configuration example of an electronic apparatus according to an embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration FIG. 1 shows a configuration example of an A / D conversion circuit according to this embodiment. The A / D conversion circuit includes a comparison circuit 10, a control circuit 20, a first D / A conversion circuit DAC 1, a second D / A conversion circuit DAC 2, and a correction unit 80. Further, an S / H (sample and hold) circuit 30 and a code data generation unit 90 can be included.

  The A / D conversion circuit according to the present embodiment is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of the components or adding other components are possible. For example, the components of the S / H circuit 30 may be omitted, and the D / A conversion circuit may have a sample and hold function for the input signal VIN. The constituent elements of the code data generation unit 90 may be omitted, and the code data CDA may be directly input from the outside.

  The comparison circuit 10 is realized by a comparator (for example, a latch-type comparator), and performs, for example, a comparison process between the signal SADD and the signal DQ.

  The control circuit 20 includes a successive approximation register SAR (Successive Approximation Registor), and outputs successive comparison data RDA (D / A input data). The successive approximation register SAR is a register whose register value is set by the comparison result signal CPQ from the comparison circuit 10. For example, when the comparison circuit 10 performs a sequential comparison process from the MSB bit to the LSB bit, the comparison process result (“1”, “0”) in each bit is stored in each register of the successive approximation register SAR. Stored as a value.

  The control circuit 20 can also perform control processing of each circuit block of the A / D conversion circuit. For example, on / off control of switch elements (switch arrays) included in the D / A conversion circuits DAC1 and DAC2 is performed.

  The D / A conversion circuit DAC1 performs D / A conversion of the successive approximation data RDA from the control circuit 20. Then, a D / A output signal DQ (analog signal obtained by D / A converting RDA) corresponding to the successive approximation data RDA is output. The D / A conversion circuit DAC1 may be a charge redistribution type using a capacitor array, or a part or all of the D / A conversion circuit DAC1 may be a ladder resistance type.

  The D / A conversion circuit DAC2 performs D / A conversion on the code data CDA. Then, a code signal SCD (a signal obtained by D / A converting CDA) corresponding to the code data CDA is output. Here, the code data CDA is data that changes with time (digital data that changes at every predetermined timing). Specifically, the data is a different value for each one or a plurality of A / D conversion timings within a predetermined data range.

  In this case, the data range is a range in which the first digital data is the upper limit value and the second digital data is the lower limit value. The A / D conversion timing is a timing corresponding to each A / D conversion period for converting digital data into an analog signal, for example.

  The S / H (sample and hold) circuit 30 is a circuit that samples and holds an input signal VIN to be subjected to A / D conversion. In the case of the charge redistribution type, the function of the S / H circuit 30 can be realized by a D / A conversion circuit.

  The code data generation unit 90 generates code data CDA and outputs it to the D / A conversion circuit DAC2. For example, within a predetermined data range, code data CDA having a different value for each one or a plurality of A / D conversion timings is output. Specifically, code data CDA having different values at one or a plurality of A / D conversion timings is output within the data range of the lower-order bit data of the successive comparison data.

  The correction unit 80 performs correction processing. Specifically, correction processing is performed to prevent the dynamic range from being reduced due to code shift using the code data CDA. The correction unit 80 has an information register 84.

  In this embodiment, the comparison circuit 10 performs a process of comparing the sampling signal SIN of the input signal VIN (a signal obtained by sampling and holding VIN), the addition signal SADD of the code signal SCD, and the D / A output signal DQ. Specifically, the comparison circuit 10 compares the addition signal SADD (addition voltage) input to the first input terminal with the D / A output signal DQ (D / A conversion voltage) input to the second input terminal. To do. In the case of the charge redistribution type or the like, the comparison circuit 10 performs processing for comparing the sampling signal SIN, the D / A output signal DQ, and the addition signal of the code signal SCD. For example, the sampling voltage of the signal SIN is compared with the added voltage of the signals DQ and SCD.

  Then, the control circuit 20 outputs the output data DOUT obtained based on the successive approximation result data QDA (final data) from the successive approximation register SAR and the code data CDA as A / D conversion data of the input signal VIN. For example, when the comparison process between the addition signal SADD of the sampling signal SIN and the code signal SCD and the D / A output signal DQ is performed as shown in FIG. 1, the control circuit 20 performs the successive comparison result data of the successive approximation register SAR. A process of subtracting code data CDA from QDA is performed. On the other hand, when the comparison process of the sampling signal SIN and the addition signal of the D / A output signal DQ and the code signal SCD is performed as in the charge redistribution type described later, the code data CDA is added to the successive comparison result data QDA. The process which adds is performed.

  The correction unit 80 performs a correction process for correcting (preventing) overflow of the successive comparison result data QDA due to code shift using the code data CDA. Here, the code shift by the code data means that the sampling signal of the input signal and the code signal are added, or the D / A output signal and the code signal are added, so that the successive comparison result data is converted into the input signal. Shifting from corresponding data to a high potential side or a low potential side.

  For example, the correction unit 80 performs the correction process by correcting the code data CDA. Then, the correction instruction signal SDR is output to the code data generation unit 90. Specifically, the correction process is performed by correcting the code data CDA (the current code data) based on the previous successive comparison result data which is the successive comparison result data in the previous A / D conversion. The correction process of the present embodiment is not limited to the process of correcting the code data CDA, and various modifications can be made as long as it can correct the overflow of the successive comparison result data QDA. Further, in addition to the previous successive comparison result data, the code or the like of the code data CDA may be determined and correction processing may be performed.

  Next, the code shift method of the present embodiment will be described by taking an example in which the number of bits of A / D conversion is 8 bits.

  First, the S / H circuit 30 samples and holds the input signal VIN and outputs a sampling signal SIN. The code data generation unit 90 outputs arbitrary code data CDA within a predetermined data range (for example, 0000 to 1111), and the D / A conversion circuit DAC2 outputs a code signal SCD corresponding to CDA.

  For example, the control circuit 20 outputs successive approximation data RDA = 10000000 in which the MSB bit is set to “1”, and the D / A conversion circuit DAC1 outputs a D / A output signal DQ corresponding to RDA.

  The comparison circuit 10 compares the voltage of the signal SADD obtained by adding the code signal SCD to the sampling signal SIN and the voltage of the D / A output signal DQ, and outputs a comparison result signal CPQ of “1” or “0”. For example, if the voltage of the signal DQ is larger than the voltage of the signal SADD, “1” is output, and if it is smaller, “0” is output. As a result, “1” or “0” is set in the MSB bit of the register value of the successive approximation register SAR.

  Next, the control circuit 20 outputs the successive approximation data RDA = 11,000,000 or 01000000 in which the next bit of the MSB is set to “1”. For example, when the comparison result of MSB is “1”, RDA = 11,000,000 is output, and when it is “0”, RDA = 01000000 is output. Then, the D / A conversion circuit DAC1 outputs a D / A output signal DQ corresponding to RDA.

  The comparison circuit 10 compares the voltage of the signal SADD obtained by adding the code signal SCD to the sampling signal SIN and the voltage of the D / A output signal DQ, and outputs a comparison result signal CPQ of “1” or “0”. As a result, “1” or “0” is set in the next bit of the MSB of the register value of the successive approximation register SAR.

  By executing the successive approximation operation from the MSB bit to the LSB bit as described above, final successive comparison result data QDA is obtained. That is, the final successive approximation result data QDA is obtained by performing the successive approximation operation so that the voltage of the input signal VIN and the voltage of the D / A output signal DQ are equal. Then, data obtained by subtracting the code data CDA from the acquired successive comparison result data QDA is output as data DOUT obtained by A / D converting the input signal VIN.

  FIG. 2 shows an A / D conversion circuit according to a first comparative example of the present embodiment. In the first comparative example, the code data generation unit 90 and the second D / A conversion circuit DAC2 are not provided. In the first comparative example, as shown in FIG. 3A, for example, a missing code is generated with a specific code due to a DNL error or the like. For example, when DNL exceeds 1LSB, a missing code phenomenon occurs in which a code having no output code is generated.

  In this regard, according to the present embodiment, even if such a missing code is generated, the signal SCD of the code data CDA that changes with time is added to the sampling signal SIN, as shown in FIG. A code shift like this is performed. Note that the solid line in FIG. 3B represents the characteristic after code shift, and the broken line represents the characteristic before code shift.

  That is, in this embodiment, the code data CDA is set to a different value for each one or a plurality of A / D conversion timings, so that the code location where the missing code is generated is 1 or as shown in FIG. It changes at every A / D conversion timing. For example, even if a missing code is generated with a code of 1000010000, the location is shifted to a location of 00010001, 00010010, or 00001111. As a result, when viewed over a long time range, as shown in FIG. 3C, DNL and INL are improved, and good characteristics that do not cause the phenomenon of missing codes can be obtained. In other words, the deterioration of the DNL characteristic (missing code) that has occurred in a specific code is diffused to surrounding codes by the code data CDA that changes with time to improve the characteristic.

  That is, consider a case where an offset voltage is intentionally added to the input voltage in the state where the missing code is generated as shown in FIG. At this time, the DNL and INL characteristics are shifted as if by a code corresponding to the applied offset voltage, as shown in FIG. In this case, since the code corresponding to the offset voltage is added to the digital data converted by the A / D conversion circuit, the final result can be obtained by subtracting the code corresponding to the offset voltage. The code shift method of this embodiment uses this characteristic and adds a different offset voltage to the input voltage every time. By doing this, the conversion is apparently performed by the A / D conversion circuit having the characteristics shown in FIG.

  For example, consider a case in which a voltage corresponding to a code in which a missing code is generated is A / D converted. When code shift is not performed, nonlinear conversion is performed around this input voltage. On the other hand, when code shift is performed by a certain value, conversion with good linearity is performed around the input voltage. In other words, by performing code shift with various values, a certain code shift value is non-linear, but most code shift values are linearly converted. Finally, by performing the code shift, a relatively linear conversion is performed even in the input voltage where the missing code is originally generated.

  As described above, according to the present embodiment, by the simple process of generating and adding the code data CDA, the occurrence of the missing code is prevented, and the DNL and INL characteristics of the A / D conversion circuit are improved. Has succeeded.

2. Correction Processing Now, it has been found that the code shift method described above has a problem that the dynamic range decreases. In other words, if an offset voltage due to code shift is applied when the input voltage is near the limit of the dynamic range, the data that actually undergoes A / D conversion will exceed the dynamic range, effectively reducing the dynamic range. End up.

  In order to avoid such a problem, in the present embodiment, for example, the previous conversion value is stored, and when the dynamic range is likely to be exceeded due to code shift, the dynamic range is calculated based on the stored conversion value. Generate code data that does not exceed. Then, the generated code data is input to the D / A conversion circuit DAC2 for code shift, thereby avoiding deterioration of the dynamic range.

  For example, in FIG. 4, the A / D input voltage range represents the dynamic range of the A / D conversion circuit, and the A / D conversion circuit appropriately sets the A / D input voltage within this A / D input voltage range. Conversion can be performed.

  When the input voltage is the first range RA1 on the high potential side of the A / D input voltage range, if the code shift in the high potential side direction (positive direction) is performed as indicated by A1, The dynamic range is exceeded and the dynamic range is effectively reduced. Similarly, when the input voltage is the second range RA2 on the low potential side of the A / D input voltage range, if a code shift in the low potential side direction (negative direction) is performed as indicated by A2. The dynamic range is exceeded, and the dynamic range is effectively reduced.

  In order to solve such a problem, in this embodiment, when the input voltage is in the first range RA1 on the high potential side, the A / D conversion result is on the low potential side as shown in B1 of FIG. The code data is corrected so as to shift to. When the input voltage is in the second range RA2 on the low potential side, the code data is corrected so that the A / D conversion result is shifted to the high potential side as indicated by B2. The first range RA1 is a high-potential side voltage range including, for example, the maximum voltage (for example, power supply voltage) of the A / D input voltage range, and the second range RA2 is, for example, the A / D input voltage range. This is a voltage range on the low potential side including the minimum voltage (for example, 0 V). The third voltage range RA3 is a voltage range (intermediate voltage range) between the first range RA1 and the second range RA2.

  For example, in the present embodiment, the correction unit 80 corrects the code data based on the previous successive comparison result data that is the successive comparison result data in the previous A / D conversion.

  Specifically, as illustrated in FIG. 6A, the correction unit 80 determines that the previous successive approximation result data QDA is data corresponding to the first range RA1 on the high potential side of the A / D input voltage range. First, the code data CDA is corrected so that the successive comparison result data QDA in the current A / D conversion is shifted to the low potential side. For example, it is assumed that the previous successive approximation result data QDA is data in the first range RA1, and the code shift direction is the high potential side direction (positive direction) as indicated by A1 in FIG. In this case, the code data generation unit 90 uses the correction instruction signal SDR from the correction unit 80 to shift the code data CDA so that the successive comparison result data QDA is shifted toward the low potential side as shown by B1 in FIG. Is output to the second D / A conversion circuit DAC2 for code shift.

  As shown in FIG. 6B, the correction unit 80, when the previous successive approximation result data QDA is data corresponding to the second range RA2 on the low potential side of the A / D input voltage range, The code data CDA is corrected so that the successive comparison result data QDA in this A / D conversion is shifted to the high potential side. For example, it is assumed that the previous successive approximation result data QDA is data within the second range RA2, and the code shift direction is the low potential side direction (negative direction) as indicated by A2 in FIG. In this case, the code data generation unit 90 uses the correction instruction signal SDR from the correction unit 80 so that the successive comparison result data QDA is shifted in the high potential side direction as indicated by B2 in FIG. Is output to the second D / A conversion circuit DAC2.

  Further, it is assumed that the previous successive approximation result data QDA is data corresponding to the third range RA3 between the first range RA1 and the second range RA2 in FIG. In this case, as shown in FIG. 6C, the code data generation unit 90 generates code data that is alternately positive and negative and outputs the code data to the second D / A conversion circuit DAC2.

  The information register 84 included in the correction unit 80 stores information on whether or not the previous successive approximation result data QDA was data corresponding to the first range RA1 or the second range RA2. As will be described later, when signals of a plurality of channels are A / D converted in a time division manner, the information register 84 stores the previous successive comparison result data in the first range RA1 for each channel of the plurality of channels. Or the information about whether it was the data corresponding to the 2nd range RA2 is memorize | stored.

  Specifically, for example, the correction unit 80 determines whether or not the successive comparison result data QDA in the previous A / D conversion is data in the first range RA1 and the code shift direction is the high potential side direction, or It is determined whether or not the previous successive comparison result data QDA is data in the second range RA2 and the code shift direction is the low potential side direction. The determination result information is stored in the information register 84. Then, the correction unit 80 generates a correction instruction signal SDR based on the stored determination result information and outputs the correction instruction signal SDR to the code data generation unit 90 to instruct correction of the code data CDA. As a result, the code data generation unit 90 corrects the code data CDA in the current A / D conversion and outputs it to the second D / A conversion circuit DAC2.

3. Correction Unit, Code Data Generation Unit FIGS. 7 and 8 show configuration examples of the correction unit 80 and the code data generation unit 90. FIG. The correction unit 80 and the code data generation unit 90 are not limited to the configurations shown in FIGS. 7 and 8, and various modifications may be made such as omitting some components or adding other components. It is.

  The correction unit 80 includes a determination unit 82, an information register 84, a selector 86, and an output register 88.

  The determination unit 82 receives from the code shift counter 92 an inverted code bit obtained by inverting the upper one bit that is the code bit of the code data. Further, the upper 2 bits of the successive approximation result data QDA are received from the successive approximation register SAR. The code shift counter 92 is a 5-bit counter, and outputs 5-bit code data in 2's complement representation. Therefore, the upper 1 bit of the code data becomes a sign bit. The upper 2 bits of the successive approximation result data QDA from the successive approximation register SAR are the MSB bit and the next bit of the MSB.

  The determination unit 82 determines whether all the 3 bits including the inverted sign bit of the code data and the upper 2 bits of the successive approximation result data QDA are “1” or “0”, and all are “1” or “0”. ", The determination result signal RS = 1 is output.

  Here, the upper one bit of the code data being “1” means that the sign of the code data is positive, and “0” means that the sign is negative. As will be described later, the code data alternately becomes positive and negative every A / D conversion. Therefore, if the inverted sign bit input to the determination unit 82 is “1”, the sign of the code data in the previous A / D conversion is negative, and the sign of the code data in the current A / D conversion is Means positive. The inverted sign bit being “0” means that the sign of the code data in the previous A / D conversion is positive and the sign of the code data in the current A / D conversion is negative.

  Further, the upper 2 bits of the successive approximation result data QDA being “11” means that the QDA is data corresponding to the first range RA1 of FIG. 5, and the upper 2 bits are “00”. Being present means that QDA is data corresponding to the second range RA2.

  When the 3 bits consisting of the inverted sign bit of the code data and the upper 2 bits of the successive approximation result data QDA are “111” or “000”, the determination result signal is RS = 1. Accordingly, the determination result signal RS = 1 indicates that the successive comparison result data QDA of the previous A / D conversion is within the first range RA1 and the sign of the current code data is positive (the shift direction is the high potential side direction). It means that the QDA is in the second range RA2 and the sign of the current code data is negative (the shift direction is the low potential side direction).

  The information register 84 receives and stores the determination result signal RS from the determination unit 82. Here, as shown in FIG. 9, in the present embodiment, the A / D conversion circuit 530 performs A / D conversion on the signals of the plurality of channels CH1 to CH16 in a time division manner. That is, a multiplexer 500 is provided on the front stage side of the A / D conversion circuit 530, and this multiplexer 500 selects a signal of one of the channels CH1 to CH16 based on the channel selection index signal CHIDX. . The A / D conversion circuit 530 A / D converts the signal (voltage) of the selected channel. At this time, since the index signal CHIDX instructs channel selection in the order of CH1, CH2, CH3,..., CH16, the A / D conversion circuit 530 causes each channel in the order of CH1, CH2, CH3,. The signal is A / D converted.

  The information register 84 is a 16-bit register (N bits in a broad sense) corresponding to 16 channels (N channels in a broad sense) of CH1 to CH16. The information register 84 receives the above-described channel selection index signal CHIDX and the 1-bit determination result signal RS from the determination unit 82. Then, among the 16 bits of the determination result information IRS, the bit corresponding to the channel currently undergoing A / D conversion is set as the value of the determination result signal RS. For example, when the determination result signal RS is “1”, the corresponding bit of the determination result information IRS is set to “1”, and when the RS is “0”, the corresponding bit of the IRS is “0”. Set to For example, in channel CH1, the successive approximation result data QDA is in the first range RA1 and the sign of the code data is positive (or in RA2 and the sign is negative), and in other channels CH2 to CH16, QDA is It is assumed that it is within the third range RA3. In this case, the determination result information IRS is set to “1000000000000000”.

  The selector 86 receives the determination result information IRS from the information register 84. Then, the value of the bit corresponding to the channel specified by the channel selection index signal CHIDX among the 16 bits of the determination result information IRS is output as a 1-bit signal SRQ. For example, when the determination result information IRS is “1000000000000000” as described above and the index signal CHIDX designates the channel CH1, the selector 86 outputs the signal SRQ = 1. On the other hand, when index signal CHIDX designates channels CH2 to CH16, selector 86 outputs signal SRQ = 0.

  The output register 88 latches the signal SRQ from the selector 86, and outputs the latched signal to the code data generation unit 90 as the correction instruction signal SDR at the next A / D conversion timing.

  By doing as described above, the successive approximation result data in the previous A / D conversion is in the first range RA1, and the code shift direction in the current A / D conversion is the high potential side direction (the sign of the code data). Is positive), the correction instruction signal in the current A / D conversion is SDR = 1. Similarly, the successive approximation result data in the previous A / D conversion is in the second range RA2, and the code shift direction in the current A / D conversion is the low potential side direction (the sign of the code data is negative). Even in this case, the correction instruction signal in the current A / D conversion is SDR = 1. On the other hand, when the previous successive approximation result data is in the third range RA3, the correction instruction signal in the current A / D conversion is SDR = 0. Therefore, the code data generation unit 90 can prevent the overflow due to the code shift by inverting the sign of the code data when the correction instruction signal is SDR = 1.

  As shown in FIG. 8, the code data generation unit 90 includes a code shift counter 92, a rearrangement unit 94, an inversion unit 96, and a selector 98.

  The code shift counter 92 is a 5-bit counter as described above, generates a 5-bit count value CCT, and outputs it to the rearrangement unit 94. The rearrangement unit 94 rearranges the 5-bit count value CCT in binary, 15, -1, 14, -2, 13, -3, 12, -4, 11, -5,. 31 (in the broad sense, prime number) data DA2 in the range of -15 to +15 such as 14, 1, -15, 0 are sequentially output to the node NC2. The inverting unit 96 inverts the sign of the data DA2 of the node NC2, and -15, 1, -14, 2, -13, 3, -12, 4, -11, 5, ... -2, 14,- Thirty-one data DA1 in the range of -15 to +15 such as 1, 15, 0 are sequentially output.

  The selector 98 selects either the data DA1 or DA2 based on the correction instruction signal SDR from the correction unit 80, and outputs it as code data CDA. For example, when SDR = 0, the data DA1 input to the terminal IN1 is selected and output as the code data CDA. When SDR = 1, the data DA2 input to the terminal IN2 is selected and output as the code data CDA. Data DA2 is data obtained by inverting the sign of data DA1. Therefore, when the correction instruction signal becomes SDR = 1, a signal obtained by inverting DA1 is output as code data CDA.

  For example, it is assumed that the previous successive approximation result data QDA is within the first range RA1 of FIG. In this case, if the data DA1 = 14 is selected as the current code data by the selector 98, an overflow to the positive side of the dynamic range occurs as indicated by A1 in FIG. Therefore, in this case, the correction instruction signal becomes SDR = 1, and the selector 98 selects the data DA2 = −14 obtained by inverting the sign of the data DA1 = 14. Therefore, DA2 = −14 is output as the code data CDA, and overflow to the positive side of the dynamic range is suppressed as indicated by B1 in FIG.

  On the other hand, it is assumed that the previous successive approximation result data QDA is in the second range RA2 and the data DA1 is −15. In this case, if this data DA1 = -15 is selected as the current code data, an overflow to the negative side of the dynamic range occurs as shown by A2 in FIG. Accordingly, in this case as well, the correction instruction signal becomes SDR = 1, and the selector 98 selects the data DA2 = 15 obtained by inverting the sign of the data DA1 = -15. Accordingly, DA2 = 15 is output as the code data CDA, and overflow to the negative side of the dynamic range is suppressed as shown by B2 in FIG.

  As described above, according to the present embodiment, the overflow of the successive comparison result data due to the code shift using the code data is corrected, so that the reduction of the dynamic range due to the code shift can be suppressed. Accordingly, it is possible to suppress a decrease in the dynamic range caused by the code shift while improving the DNL and INL characteristics of the A / D conversion circuit by the code shift.

  If the previous successive approximation result data QDA is within the third range RA3, the correction instruction signal is SDR = 0, so that the data DA1 is selected by the selector 98 and becomes positive and negative alternately. Code data CDA is output. Since the code data CDA alternately becomes positive and negative in this way, it is possible to suppress a situation in which the frequency component (low frequency component) of the change in the code data CDA adversely affects the A / D conversion characteristics. That is, as the code data CDA alternately becomes positive and negative, the frequency component of the change of the code data CDA shifts on the high frequency side. Since such a high frequency component can be cut by, for example, a digital filter (low pass filter) at the subsequent stage of the A / D conversion circuit, the influence of the frequency component of the change in the code data CDA can be reduced. An adverse effect on the D conversion characteristics can be suppressed.

  In addition, as shown in FIG. 1, when a method of comparing the sum signal of the sampling signal SIN of the input signal and the code signal SCD and the D / A output signal SCD is adopted, the code data of the positive sign has a high potential of QDA The data is shifted in the lateral direction, and the code data with a negative sign is data that shifts the QDA in the lower potential direction. However, when the method of comparing the sampling signal SIN, the D / A output signal DQ, and the addition signal of the code signal SCD is adopted, the code data with a positive sign is data that shifts the QDA in the low potential side direction. Therefore, the code data with a negative sign is data for shifting the QDA in the high potential side direction.

4). Oversampling In the present embodiment, oversampling A / D conversion that is a power of 2 is performed. For example, when 8 times oversampling is taken as an example, as shown in FIG. 10A, every time A / D conversion AD1 to AD8 is performed eight times, one final A / D output data is obtained. Is output. That is, the A / D converter circuit is operated in a wider band (faster frequency) than the originally required band, and a signal is extracted by filtering the required band using a digital filter subsequent to the A / D converter circuit. At this time, necessary out-of-band quantization noise is removed by the digital filter, and as a result, the SNR (Signal to Noise Ratio) is improved. For example, when OSR (Over-Sampling-Ratio) is doubled, theoretically, an effect of improving SNR by 3 dB (0.5 bits) can be obtained. Further, by performing oversampling, there is an advantage that the order of the pre-filter in the preceding stage of the A / D conversion circuit can be reduced.

  However, when such oversampling A / D conversion is performed, if there is a correlation between the change period of the code data and the oversampling period, the improvement of the SNR due to oversampling may be suppressed. There is. For example, when oversampling of a power of 2 is performed as shown in FIG. 10A, if the number of code data is also a power of 2, each A / D conversion of each power of 2 and each code data Will become constant. Therefore, an improvement in SNR and the like due to a synergistic effect of oversampling and code shift is suppressed.

  Therefore, in the present embodiment, the code data generation unit 90 performs prime sampling when oversampling A / D conversion of power of 2 (2, 4, 8, 16, 32, etc.) is performed. Code data is generated. Taking FIG. 8 as an example, the code data generation unit 90 generates 31 code data that are prime numbers and sequentially outputs them. In this way, the correspondence between each A / D conversion of power of 2 and each code data is not constant. Therefore, it is possible to improve SNR and the like due to the synergistic effect of oversampling and code shift.

  The oversampling A / D conversion is not limited to the method shown in FIG. 10A, and various modifications can be made. Further, the number of code data and the generation pattern are not limited to the example shown in FIG.

  Further, when A / D conversion is performed on a plurality of channels of signals in a time division manner as shown in FIG. 9, the A / D conversion circuit operates as shown in FIG. For example, after executing sampling SC1 and conversion CC1 for the signal of channel CH1, sampling SC2 and conversion CC2 for the signal of channel CH2 are executed. Thereafter, sampling and conversion of each channel of CH3 to CH16 are sequentially executed in the same manner. In this case, when C1 in FIG. 10B is the current A / D conversion, C2 is the previous A / D conversion. Accordingly, the information register 84 of FIG. 7 stores the determination result information of the previous A / D conversion indicated by C2, and the code in the current A / D conversion indicated by C1 is based on the determination result information of C2. Data will be corrected.

5. Detailed Configuration Example FIG. 11 shows a detailed configuration example of the A / D conversion circuit of this embodiment. FIG. 11 shows a detailed configuration example of the DAC 1, DAC 2, and comparison circuit 10 of FIG. 1, and the DAC 1 and DAC 2 are configured by a charge redistribution type D / A conversion circuit.

  Specifically, the first D / A conversion circuit DAC1 includes a first capacitor array unit 41 and a first switch array unit 51. Also included is a first series capacitor CS1 provided between comparison node NC and first node N1. The DAC 1 includes a second capacitor array unit 42 and a second switch array unit 52. In the sampling period, switch elements SS1 and SS2 for setting the nodes NC and N1 to GND (AGND) are included.

  Note that one end of the third series capacitor is connected to the node N1, and the capacitor array unit and the switch array having the same configuration as the capacitor array unit 42 and the switch array unit 52 are connected to the other end of the third series capacitor. A part may be provided.

  The first capacitor array unit 41 of the DAC 1 includes a plurality of capacitors CA1 to CA4. One end of each of the capacitors CA <b> 1 to CA <b> 4 is connected to the comparison node NC of the comparison circuit 10. Here, the comparison node NC (sampling node) is a node connected to the first input terminal (inverting input terminal) of the comparison circuit 10, and the second input terminal (non-inverting input terminal) of the comparison circuit 10 is GND. Set to The capacitors CA1 to CA4 are binary weighted. For example, the capacitance values of CA1, CA2, CA3, and CA4 are C, 2C, 4C, and 8C in the case of 4 bits. The first capacitor array unit 41 also includes a dummy capacitor CDM.

  The first switch array unit 51 of the DAC 1 includes a plurality of switch elements SA1 to SA4. The switch elements SA1 to SA4 are connected to the other ends of the capacitors CA1 to CA4 of the first capacitor array unit 41. The switch elements SA1 to SA4 are switch-controlled based on the higher-order bit data of the successive approximation data RDA (for example, the higher-order 4-bit data when the RDA is 8 bits).

  The second capacitor array unit 42 of the DAC 1 includes a plurality of capacitors CB1 to CB4. One end of each of the capacitors CB1 to CB4 is connected to the first node N1. Here, the first node N1 is a node on the other end side of the series capacitor CS1 whose one end is connected to the comparison node NC. The capacitors CB1 to CB4 are binary weighted. For example, the capacitance values of CB1, CB2, CB3, and CB4 are C, 2C, 4C, and 8C in the case of 4 bits.

  The second switch array unit 52 of the DAC 1 includes a plurality of switch elements SB1 to SB4. The switch elements SB1 to SB4 are connected to the other ends of the capacitors CB1 to CB4 of the second capacitor array unit 42. The switch elements SB1 to SB4 are switch-controlled based on lower-order bit data of the successive approximation data RDA (for example, lower-order 4-bit data when the RDA is 8 bits).

  The second D / A conversion circuit DAC2 includes a second series capacitor CS2 provided between the comparison node NC and the second node N2. A third capacitor array unit 43 and a third switch array unit 53 are also included. In addition, in the sampling period, a switch element SS3 for setting the second node N2 to GND is included.

  The third capacitor array unit 43 of the DAC 2 includes a plurality of capacitors CC1 to CC4. One end of each of the capacitors CC1 to CC4 is connected to the second node N2. Here, the second node N2 is a node on the other end side of the series capacitor CS2, one end of which is connected to the comparison node NC. The capacitors CC1 to CC4 are binary weighted. For example, the capacitance values of CC1, CC2, CC3, and CC4 are C, 2C, 4C, and 8C in the case of 4 bits.

  The third switch array unit 53 of the DAC 2 includes a plurality of switch elements SC1 to SC4. These switch elements SC <b> 1 to SC <b> 4 are connected to the other ends of the capacitors CC <b> 1 to CC <b> 4 of the third capacitor array unit 43. The switch elements SC1 to SC4 are switch-controlled based on the code data CDA.

  That is, the code data generation unit 90 in FIG. 1 outputs the code data CDA to the D / A conversion circuit DAC2, and the switch elements SC1 to SC4 are switch-controlled based on the code data CDA. For example, the code data generation unit 90 outputs, as code data CDA, data having a different value for each one or a plurality of A / D conversion timings in the data range of the lower-order bit data of the successive approximation data RDA.

  Specifically, in the case of 8-bit A / D conversion in FIG. 11, the code data CDA is changed within the lower 4-bit data range of the successive approximation data RDA. For example, the code data CDA is randomly changed within the data range of 0000 to 1111 (or within the data range narrower than 0000 to 1111) to switch the switch elements SC1 to SC4 of the switch array unit 53 of the D / A conversion circuit DAC2. Control. At this time, the switch elements SB1 to SB4 of the switch array unit 52 of the D / A conversion circuit DAC1 are also switch-controlled by the lower 4 bits of the successive approximation data RDA. As described above, by setting the range in which the code data CDA is changed within the data range of the successive approximation data RDA for switch-controlling the switching elements SB1 to SB4 of the DAC1, occurrence of missing codes can be effectively prevented.

  It is assumed that the minimum resolution (voltage corresponding to LSB, quantization voltage) of the D / A conversion circuit DAC1 is RS1, and the minimum resolution of the D / A conversion circuit DAC2 is RS2. In this case, RS2 = RS1 in FIG. Specifically, for example, the capacitance values of the series capacitors CS1 and CS2 are the same (substantially the same), and the capacitance value of the capacitor CB1 corresponding to the LSB of the DAC1 and the capacitance value of the capacitor CC1 corresponding to the LSB of the DAC2 are also the same. (Almost the same). That is, the DAC 2 outputs a code voltage larger than the noise voltage, not the noise voltage less than the minimum resolution RS1 (LSB) of the DAC 1. In this way, a code shift as shown in FIG. 3B can be realized. In addition, it is not limited to RS2 = RS1, RS2> = RS1 may be sufficient.

  Next, the operation of this embodiment will be described in detail with reference to FIG. As shown in FIG. 12, in the sampling period of the input signal VIN, the switch elements SS1 and SS2 of the main D / A conversion circuit DAC1 are turned on, and the nodes NC and N1 are set to GND. Further, the other ends of the capacitors CA1 to CA4 and CB1 to CB4 are set to the voltage level of VIN via the switch elements SA1 to SA4 and SB1 to SB4 of the D / A conversion circuit DAC1.

  As a result, the input signal VIN is sampled. When the switch elements SA1 to SA4 and SB1 to SB4 are turned off, the voltage of the input signal VIN at that timing is held. In the sampling period, the other end of the dummy capacitor CDM is set to a voltage level of VIN via the dummy capacitor switching element SDM.

  In the sampling period, the switch element SS3 of the D / A conversion circuit DAC2 for code shift is turned on, and the node N2 is set to GND. Also, the other ends of the capacitors CC1 to CC4 are set to GND via the switch elements SC1 to SC4. As a result, both ends of the capacitors CC1 to CC4 are set to GND, and no charge is accumulated.

  Next, in the successive comparison period of A / D conversion, the switch elements SS1 and SS2 of the main D / A conversion circuit DAC1 are turned off. The other end of the dummy capacitor switching element SDM is set to GND.

  Based on each bit of the successive approximation data RDA, the switch elements SA1 to SA4 and SB1 to SB4 of the DAC1 are switch-controlled, and the other ends of the capacitors CA1 to CA4 and CB1 to CB4 are set to VREF or GND.

  For example, when the successive approximation data is RDA = 10000000, the other end of the capacitor CA4 corresponding to the MSB of RDA is set to the reference voltage VREF. The other ends of the other capacitors CA3 to CA1 and CB4 to CB1 are set to GND.

  When the successive approximation data is RDA = 10001000, the other ends of the capacitors CA4 and CB4 are set to VREF. The other ends of the other capacitors CA3 to CA1 and CB3 to CB1 are set to GND.

  In the successive comparison period of A / D conversion, the switch element SS3 of the D / A conversion circuit DAC2 for code shift is turned off. Based on each bit of the code data CDA, the switch elements SC1 to SC4 of the DAC 2 are switch-controlled, and the other ends of the capacitors CC1 to CC4 are set to VREF or GND.

  For example, when the code data is CDA = 1000, the other end of the capacitor CC4 is set to VREF, and the other ends of the other capacitors CC3 to CC1 are set to GND. When the code data is CDA = 1100, the other ends of the capacitors CC4 and CC3 are set to VREF, and the other ends of the other capacitors CC2 and CC1 are set to GND.

  In this case, the code data CDA changes at each A / D conversion timing shown in FIG. That is, the code data CDA changes for each A / D conversion period constituted by the sampling period and the successive approximation period. Note that the code data CDA may be changed at every A / D conversion timing.

  In the charge redistribution type A / D conversion circuit of FIG. 11, comparison processing of a VIN sampling signal (sampling voltage) and a D / A output signal and a code signal (code voltage) addition signal (addition voltage) is performed. Done. In this case, the control circuit 20 in FIG. 1 performs a process of adding the code data CDA to the successive approximation result data QDA in the successive approximation register SAR.

  Specifically, in the sampling period, charges corresponding to the input signal VIN are accumulated in the capacitors CA1 to CA4 and CB1 to CB4. Then, the charge accumulated according to VIN is compared with the charges accumulated in capacitors CA1 to CA4, CB1 to CB4, and CC1 to CC4 according to successive comparison data RDA and code data CDA in the successive approximation period. The Then, the successive approximation data RDA when the two charges coincide is output from the successive approximation register SAR as successive comparison result data QDA. Data obtained by adding the code data CDA to the successive comparison result data QDA is output as data DOUT obtained by A / D converting the input signal VIN. In this way, it is possible to output appropriate A / D conversion data while realizing code shift based on the code data CDA as shown in FIG.

  FIG. 13 shows an A / D conversion circuit of a second comparative example of the present embodiment. The second comparative example is an example in which the first comparative example of FIG. 2 is realized by a charge redistribution type. The D / A conversion circuit DAC (and the S / H circuit 330) includes a capacitor array unit 321 and a switch. This is realized by the array unit 331 and the switch element SS.

  The major factor that determines the conversion accuracy of the A / D conversion circuit is the DAC conversion accuracy. In the second comparative example of FIG. 13, assuming that the DAC resolution is n bits, the capacitor array unit 321 includes n capacitors CA1 to CAn weighted in binary and one dummy capacitor CDM. In the sampling period, the other ends of the capacitors CA1 to CAn are connected to the input signal VIN, and the comparison node NC is set to GND.

  Then, in the successive approximation period, successive approximation processing is performed sequentially from the MSB that is the most significant bit. Specifically, the other end of the capacitors CA1 to CAn is connected to the reference voltage VREF or GND according to the input value of the D / A conversion circuit using the switch elements SA1 to SAn of the switch array unit 331. Switch. Thus, the voltage of the comparison node NC at the inverting input terminal of the comparison circuit 310 is a voltage obtained by subtracting the VIN sampling voltage from the DAC output value.

However, in the second comparative example of FIG. 13, if the resolution of the DAC is set to 12 bits in order to set the resolution of the A / D conversion circuit to 12 bits, for example, a total capacitance value of 2 ¹² × C is required. End up. For this reason, the circuit becomes large and a large current is required to charge the capacitor. Since this tendency becomes stronger as the resolution of the A / D conversion circuit is increased, there is a problem that the second comparative example in FIG.

  FIG. 14 shows a third comparative example of A / D conversion. In the third comparative example, in order to solve the problem of the second comparative example described above, a series capacitor CS is provided, and a binary weighted capacitor is provided in a plurality of stages. That is, a series capacitor CS having one end connected to the comparison node NC and the other end connected to the node N1 is provided. In addition, a capacitor array unit 341 connected to the comparison node NC and a switch array unit 351 that controls the switch, a capacitor array unit 342 connected to the node N1, and a switch array unit 352 that controls the switch are provided.

According to the configuration of the third comparative example in FIG. 14, for example, the capacitance value of the capacitor CA1 of the capacitor array unit 341 and the capacitance value of the capacitor CB1 of the capacitor array unit 342 can be made the same. Accordingly, taking the case of 8 bits as an example, the second comparative example of FIG. 13 requires a capacitance value of 2 ⁸ × C, whereas the third comparative example of FIG. 14 has a capacitance value of 2 ⁵ × C. That's it. For this reason, the circuit area can be reduced and the charging current of the capacitor can be reduced.

  However, in the third comparative example of FIG. 14, there is a problem that the capacitance parasitic to the node N1 deteriorates the DNL (Differential Non Linearity) or INL (Integral Non Linearity) of the DAC. This is because the capacitance ratio weighted for each binary is distorted by the parasitic capacitance. In the case of 8 bits in FIG. 14 as an example, this adverse effect is prominent in the vicinity of the code where the fifth bit changes from the LSB. Specifically, it occurs at the transition between 00001111 and 00010000 (MSB is first), and a problem of a missing code as shown in FIG. 3A occurs.

  As a technique for solving such a problem, a technique of trimming the capacitance value of the series capacitor CS and finely adjusting the characteristics can be considered. However, with trimming alone, there is a limit to the capacity unit and range that can be trimmed. In addition, a trimming process is required in the manufacturing process, resulting in high costs. Although a method for achieving high accuracy by performing digital compensation processing for digitally correcting A / D conversion data is conceivable, there is a problem that processing becomes complicated and extra processing is required.

  Next, a theoretical formula of the SAR type ADC when the parasitic capacitances CP1 and CP2 are added to the nodes NC and N1 will be described with reference to FIG. A theoretical formula that does not include the parasitic capacitances CP1 and CP2 can be derived by setting CP1 and CP2 to zero. Capacitance values of capacitors CA1 and CB1, CA2 and CB2, CA3 and CB3, CA4 and CB4 are C, 2C, 4C, and 8C, respectively. The capacitance value of the series capacitor CS is C. The dummy capacitor CDM is used for the purpose of adjusting the amount of charge charged at the time of sampling (full scale adjustment), but here the capacitance value of the dummy capacitor CDM is ignored for the sake of simplicity of explanation.

  FIG. 15 shows the state of the switch element during the sampling period. The amount of charge Q1 charged in the node NC during this sampling period is expressed by the following equation (1).

  In addition, the amount of charge Q2 charged in the node N1 during the sampling period is expressed by the following equation (2).

  The series capacitor CS and the parasitic capacitances CP1 and CP2 are not charged because the voltage at both ends is GND (ground potential).

  Next, the voltage V1 of the node NC and the voltage V2 of the node N1 in the successive approximation period are obtained. For example, in FIG. 15, the switch elements SB1 to SB4 are switched by the lower 4 bits D0 to D3 of the successive approximation data RDA, and the switch elements SA1 to SA4 are switched by the upper 4 bits D4 to D7 of the RDA. The Specifically, when bit Di = 1 (0 ≦ i ≦ 7), it is connected to VIN, and when bit Di = 0, it is connected to GND. In this case, the charge amounts Q1 and Q2 accumulated in the nodes NC and N1 in the successive approximation period are expressed as the following equations (3) and (4).

  Then, according to the law of charge conservation, the amount of charge Q1 in the equations (1) and (3) is equal, and the amount of charge Q2 in the equations (2) and (4) is equal. When the comparison operation for all the bits D0 to D7 of the successive approximation data RDA is completed, the voltage of the node NC of the inverting input terminal of the comparison circuit 310 becomes equal to the GND of the non-inverting input terminal. (5) is established.

  Therefore, solving the simultaneous equations of the equations (1) to (5) for VIN leads to the following equation (6).

  As is apparent from the equation (6), the A / D conversion result of VIN is not affected by the parasitic capacitance CP1 of the node NC, and only the parasitic capacitance CP2 of the node N2 adversely affects the characteristics. Therefore, the series capacitor CS needs to be trimmed in order to reduce the adverse effect of the parasitic capacitance CP2. Also, from equation (6), it can be understood that the adverse effect of the parasitic capacitance CP2 appears when the connection of the switch element corresponding to the bit of D4 or more changes, thereby generating a missing code as shown in FIG. Is done.

  16A and 16B are explanatory diagrams of DNL and INL. DNL shown in FIG. 16A is the difference between the ideal code width and the measured code width. For example, in FIG. 16A, due to the deterioration of the DNL characteristics, the width of the code 010 is narrowed and the width of the code 011 is widened. When the width of the code 010 is further narrowed and disappears, the code 010 becomes a missing code as shown in FIG.

  In FIG. 16B, INL is the maximum deviation between the actual code transition point (broken line) and the corresponding ideal transition point (solid line) after the gain error and offset error are removed. A positive INL indicates that the transition is later than ideal, and a negative INL indicates that the transition is earlier than ideal.

  FIG. 17A and FIG. 17B show examples of simulation results of DNL. Here, a case will be described as an example in which a fully differential A / D conversion circuit described later is used, the main DAC 1 is 14 bits, and the code shift DAC 2 is 4 bits. In FIG. 11, the main DAC 1 has a 4-bit + 4-bit two-stage serial configuration, but the 14-bit main DAC 1 has a 3-stage configuration of 6 bits + 4 bits + 4 bits.

  FIG. 17A is an example of a DNL simulation result when the code shift method of this embodiment is not employed. In FIG. 17A, a missing code with a DNL of 1 LSB or more is generated.

  FIG. 17B is an example of a DNL simulation result when the code shift method of the present embodiment is employed. In FIG. 17B, DNL is less than 1 LSB, and the occurrence of missing codes is prevented.

  As described above, according to the present embodiment, by adding the code shift DAC 2 as shown in FIG. 11 to the third comparative example of FIG. 14, and adding the code data signal by the DAC 2, The code shift is realized.

  That is, in the third comparative example of FIG. 14, the missing codes as shown in FIGS. 3A and 17A are generated due to the parasitic capacitance CP2 of the node N1. On the other hand, in this embodiment, the code data signal that changes over time is added by the DAC 2 to spread the deterioration of the DNL (missing code) generated in the specific code over the surrounding codes over time. Let For example, when a missing code is generated at the fourth bit from the MLSB such as 00010000, a random code data signal that changes in the data range of 0000 to 1111 is added. By doing so, as shown in FIG. 3B and FIG. 17B, DNL can be suppressed to less than 1 LSB, and occurrence of missing codes can be prevented. Therefore, even when the series capacitor CS1 is provided to reduce the circuit scale, it is possible to prevent the occurrence of missing codes due to the parasitic capacitance of the node N1. As a result, it is possible to achieve both reduction in circuit scale and prevention of deterioration of A / D conversion characteristics.

6). Fully Differential Type FIG. 18 shows a configuration example of a fully differential type A / D conversion circuit to which the code shift method of this embodiment is applied. The A / D conversion circuit of FIG. 18 includes a comparison circuit 10, a main D / A conversion circuit DAC1P connected to the non-inverting input terminal of the comparison circuit 10, and a main D / A conversion connected to the inverting input terminal. A circuit DAC1N is included. Further, a D / A conversion circuit DAC2P for code shift connected to the non-inverting input terminal of the comparison circuit 10 and a D / A conversion circuit DAC2N for code shift connected to the inverting input terminal are included.

  The configuration of the main DAC 1P on the non-inversion side (positive side) and the main DAC 1N on the inversion side (negative side) includes a capacitor array unit and a switch array unit, similarly to the main DAC 1 in FIG. The DAC 1P receives a non-inverted (positive) input signal PIN constituting a differential signal, and the DAC 1N receives an inverted (negative) input signal NIN constituting a differential signal. .

  In the sampling period, the nodes NCP and N1P of the DAC 1P are set to the common voltage (intermediate voltage) VCM by the switch elements SS1P and SS2P. The nodes NCN and N1N of the DAC 1N are set to the common voltage VCM by the switch elements SS1N and SS2N.

  In the sampling period, one end of the switch elements SA1P to SA4P and SB1P to SB4P of the DAC 1P is connected to the signal PIN on the non-inversion side of the differential signal, and one end of the switch elements SA1N to SA4N and SB1N to SB4N of the DAC 1N It is connected to the signal NIN on the inversion side of the motion signal.

  On the other hand, in the successive approximation period, one end of the switching elements SA1P to SA4P and SB1P to SB4P of the DAC 1P is connected to VREF when the corresponding bit of the successive approximation data is “1”, and is “0”. Is connected to GND.

  On the other hand, one end of the switching elements SA1N to SA4N and SB1N to SB4N of the DAC 1N is connected to the GND when the corresponding bit of the successive approximation data is “1”, and is one when the bit is “0”. Connected to VREF.

  The non-inverted code shift DAC 2P and the inverted code shift DAC 2N include a capacitor array unit and a switch array unit, similar to the code shift DAC 2 in FIG.

  In the sampling period, the node N2P of the DAC 2P is set to VCM by the switch element SS3P. The node N2N of the DAC 2N is set to VCM by the switch element SS3N. Further, one ends of the switching elements SC1P to SC4P of the DAC 2P and the switching elements SC1N to SC4N of the DAC 2N are connected to the VCM.

  On the other hand, in the successive approximation period, one end of the switch elements SC1P to SC4P of the DAC 2P is connected to VREF when the corresponding bit of the code data is “1”, and is connected to GND when the bit is “0”. The On the other hand, one end of each of the switching elements SC1N to SC4N of the DAC 2N is connected to GND when the corresponding bit of the code data is “1”, and is connected to VREF when the bit is “0”.

  18 can also improve the DNL and INL of the A / D conversion circuit by the code shift method, and prevent the occurrence of missing codes and the like. Further, by configuring the A / D conversion circuit as a fully differential type, the amplitude can be increased, the S / N ratio can be improved, and the influence of common mode noise can be reduced.

7). Electronic Device FIG. 19 shows a configuration example of an electronic device including the A / D conversion circuit of this embodiment. This electronic device includes a sensor 510, a detection circuit 520, an A / D conversion circuit 530, and a processing unit 540. Various modifications may be made such as omitting some of these components or adding other components. For example, the detection circuit 520, the A / D conversion circuit 530, and the processing unit 540 can be realized by an integrated circuit device.

  As the electronic device in FIG. 19, various devices such as a biological measurement device (pulse meter, pedometer, etc.), a portable information terminal, a video device (digital camera, video camera), and a clock can be assumed.

  The sensor 510 is a gyro sensor, an acceleration sensor, a photo sensor, a pressure sensor, or the like, and various sensors are used according to the application of the electronic device. The detection circuit 520 amplifies the sensor signal output from the sensor 510 and extracts a desired signal. The A / D conversion circuit 530 converts the detection signal (desired signal) from the detection circuit 520 into digital data and outputs the digital data to the processing unit 540.

  The processing unit 540 performs necessary digital signal processing on the digital data from the A / D conversion circuit 530. The processing unit 540 may perform gain control of the detection circuit 520 and the like. Here, as the digital signal processing performed by the processing unit 540, various processes such as fast Fourier transform for extracting an appropriate desired signal from the sensor signal can be assumed.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. Further, the configuration / operation of the A / D conversion circuit and the electronic device, the A / D conversion method, the code generation method, the code shift method, and the like are not limited to those described in this embodiment, and various modifications can be made. is there. For example, FIG. 11 shows an example in which the main DAC 1 has a two-stage configuration, but a configuration having three or more stages may be used.

DAC1 first D / A conversion circuit, DAC2 second D / A conversion circuit,
SAR successive approximation register, SDR correction instruction signal,
CA1-CA4, CB1-CB4, CC1-CC4 capacitors,
SA1 to SA4, SB1 to SB4, SC1 to SC4, SS1 to SS3 switch elements,
CS1 first series capacitor, CS2 second series capacitor,
10 comparison circuit, 20 control circuit, 30 S / H circuit,
41 1st capacitor array part, 42 2nd capacitor array part,
43 Third capacitor array part,
51 1st switch array part, 52 2nd switch array part,
53 3rd switch array part,
80 correction unit, 82 determination unit, 84 information register, 86 selector,
88 output register, 90 code data generation unit, 92 code shift counter, 94 rearrangement unit, 96 inversion unit, 98 selector,
310 comparison circuit, 320 control circuit, 330 S / H circuit,
510 sensor, 520 detection circuit, 530 A / D conversion circuit, 540 processing unit

Claims (15)

An A / D conversion circuit that performs A / D conversion based on an input signal and outputs A / D conversion data,
A comparison circuit;
A control circuit having a successive approximation register in which successive comparison result data is set by a comparison result signal from the comparison circuit, and outputting successive comparison data;
A first D / A conversion circuit for D / A converting the successive approximation data from the control circuit and outputting a D / A output signal;
A code data generation unit that generates code data that changes over time;
A second D / A conversion circuit for D / A converting the code data and outputting a code signal;
A correction unit for performing correction processing;
Including
The comparison circuit is
A process of comparing a sum signal of the sampling signal of the input signal and the code signal with the D / A output signal, or a sum signal of the D / A output signal and the code signal is compared with the sampling signal. Process,
The control circuit includes:
Output data obtained based on the successive comparison result data and the code data is output as the A / D conversion data,
The correction unit is
And characterized in that said code correction processing successive approximation result is corrected so as not to overflow by the comparison circuit I by the code shift with data, on the basis of said code data symbols and the successive approximation result data A / D conversion circuit. In claim 1,
The correction unit is
An A / D conversion circuit that performs the correction processing for correcting the code data so as not to overflow due to the code shift by inverting the sign of the code data. In claim 1 or 2,
The correction unit is
When the result of the successive approximation overflows to the high potential side of the A / D input voltage range, the code data is inverted so that the direction of the code shift is on the low potential side, and the A / D input voltage range A / D conversion characterized in that, when the result of the successive comparison overflows to the low potential side, the correction processing for inverting the sign of the code data so that the code shift direction is on the high potential side is performed. circuit. In any one of Claims 1 thru | or 3,
The correction unit is
The previous successive approximation result data, which is the successive approximation result data in the previous A / D conversion, is data corresponding to the first range on the high potential side of the A / D input voltage range, and the code shift When the direction is the high potential side direction, the correction processing for inverting the sign of the code data is performed so that the successive comparison result data in the current A / D conversion is shifted to the low potential side,
When the previous successive approximation result data is data corresponding to the second range on the low potential side of the A / D input voltage range and the direction of the code shift is the low potential side direction, An A / D conversion circuit that performs the correction process for inverting the sign of the code data so that the successive approximation result data in the A / D conversion is shifted to a high potential side. In claim 4,
The code data generator is
If the previous successive approximation result data is data corresponding to a third range between the first range and the second range, the code data that is alternately positive and negative is generated. An A / D conversion circuit which outputs to the second D / A conversion circuit. In claim 4 or 5,
The correction unit is
An A / D conversion circuit comprising an information register for storing information as to whether or not the previous successive approximation result data was data corresponding to the first range or the second range. In claim 6,
The information register is
When the A / D conversion is performed on the signals of a plurality of channels in a time division manner, the previous successive comparison result data is data corresponding to the first range or the second range for each channel of the plurality of channels. An A / D conversion circuit for storing the information as to whether or not there has been. In any one of Claims 1 thru | or 7,
The code data generator is
An A / D conversion circuit that outputs data having different values at one or more A / D conversion timings within a predetermined data range as the code data. In claim 8,
The code data generator is
An A / D conversion circuit which generates and outputs a prime number of code data when the A / D conversion of oversampling by a power of 2 is performed. In any one of Claims 1 thru | or 9,
The A / D conversion circuit, wherein the first D / A conversion circuit and the second D / A conversion circuit are charge redistribution type D / A conversion circuits. In claim 10,
The first D / A conversion circuit includes:
A first capacitor array unit having a plurality of capacitors, one end of which is connected to a comparison node of the comparison circuit;
A first switch array section having a plurality of switch elements connected to the other ends of the plurality of capacitors of the first capacitor array section and switch-controlled based on upper bit data of the successive approximation data;
A first series capacitor provided between the comparison node and the first node;
A second capacitor array unit having a plurality of capacitors, one end of which is connected to the first node;
A second switch array unit having a plurality of switch elements connected to the other ends of the plurality of capacitors of the second capacitor array unit and controlled to be switched based on lower bit data of the successive approximation data;
The second D / A conversion circuit includes:
A second series capacitor provided between the comparison node and a second node;
A third capacitor array unit having a plurality of capacitors, one end of which is connected to the second node;
An A / D conversion comprising: a third switch array unit having a plurality of switch elements connected to the other ends of the plurality of capacitors of the third capacitor array unit and controlled to be switched based on the code data circuit. In any one of Claims 1 thru | or 11,
The control circuit includes:
A process of subtracting the code data from the successive approximation result data of the successive approximation register when the process of comparing the sum signal of the sampling signal and the code signal with the D / A output signal is performed; An A / D conversion circuit characterized in that it is performed. In any one of Claims 1 thru | or 11,
The control circuit includes:
When the process of comparing the sum signal of the D / A output signal and the code signal with the sampling signal is performed, the process of adding the code data to the successive approximation result data of the successive approximation register is performed. An A / D conversion circuit characterized by the above.   An electronic apparatus comprising the A / D conversion circuit according to claim 1. A / D in a successive approximation type A / D conversion circuit having a comparison circuit, a successive approximation register, and a D / A conversion circuit, performing A / D conversion based on an input signal, and outputting A / D conversion data A conversion method,
Generate a code signal corresponding to code data that changes over time,
A process of comparing an addition signal between the sampling signal of the input signal and the code signal with a D / A output signal from the D / A conversion circuit, or an addition signal of the D / A output signal and the code signal , The comparison with the sampling signal is performed by the comparison circuit ,
Output data obtained based on the successive approximation result data from the successive approximation register and the code data is output as the A / D conversion data,
And characterized in that said code correction processing successive approximation result is corrected so as not to overflow by the comparison circuit I by the code shift with data, on the basis of said code data symbols and the successive approximation result data A / D conversion method.

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