TWI543170B - Operation method for memory device - Google Patents

Description

Memory device operation method 【0001】

The present disclosure relates to a method of operating a memory device, and more particularly to writing to a memory device.

【0002】

The writing of the memory device can be performed using various methods. One such method is Incremental Step Pulse Programming (ISPP). In the step-by-step pulse writing process, the memory cell is written to a high threshold voltage state by gradually increasing a small amount of fixed voltage ΔV _ISPP to the write voltage V _pgm . During such processing, memory cells located close to the memory cells being written may also be affected. This effect is called write interference. If the memory cell being written is a "slow memory cell", that is, a memory cell that requires more write pulses than other memory cells, the write disturb effect becomes more critical.

[0003]

In the present disclosure, a method of operating a memory device is provided to reduce write disturbance.

[0004]

According to some embodiments, a method of operating a memory device is provided. This method of operation includes writing to the memory device as described below. First, provide the complex data to the controller. These materials include complex codes. The respective numbers of the codes are calculated by the controller. Next, a mapping rule is generated by the controller according to the respective numbers of the codes. In the mapping rule, the codes are each mapped to one of a verifying voltage level that is sequentially arranged from low to high. Thereafter, the data is written into a memory array of the memory device according to the mapping rule.

[0005]

According to some embodiments, a method of operating a memory device is provided. This method of operation includes writing to the memory device as described below. A plurality of first write page bits are provided for the plurality of data, wherein the first write page bits comprise code 0 and code 1. The number of codes 0 and 1 in the first written page bit is calculated by a controller. The first mapping rule is generated by the controller based on the respective numbers of the encoding 0 and the encoding 1 in the first written page bit. Then, the first write page bit is written into a first write page of the memory device according to the first mapping rule. A plurality of second write page bits are provided for the data, wherein the second write page bits include code 0 and a code 1. Under the code 0 and code 1 of the first page bit, the controller calculates the number of codes 0 and 1 in the second page bit. The second mapping rule is generated by the controller based on the respective numbers of the code 0 and the code 1 in the second write page bit. Then, the second write page bit is written into a second write page of the memory device according to the second mapping rule. A plurality of third write page bits are provided for the data, wherein the third write page bits include code 0 and code 1. Under the code 0 and code 1 of each of the first write page bit and the code 0 and the code 1 of the second write page bit, the controller calculates the code 0 in the third write page bit and Code 1 is the number of each. A third mapping rule is generated by the controller based on the respective numbers of the code 0 and the code 1 in the third write page bit. Then, the third write page bit is written into a third write page of the memory device according to the third mapping rule.

[0006]

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

[0042]

152, 154, 156, 158, 160, 162‧ ‧ bits
252, 254, 256, 258, 260, 262‧ ‧ bits
352, 354, 356, 358, 360, 362‧ ‧ bits
A1, A2‧‧‧ groups
Group B1, B2, B3, B4‧‧‧
S102, S104, S106, S108‧‧‧ steps
S132, S134, S136‧‧‧ steps
S202, S204, S206, S208‧‧‧ steps
S232, S234, S236‧‧‧ steps
S302, S304, S306, S308, S310, S312, S314, S316, S318, S320, S322, S324, S326, S328, S330‧‧
S332, S334, S336‧‧‧ steps

【0007】

1 is a flow chart of a write process of an operation method of a multi-level-cell (MLC) memory device according to an embodiment.
2A to 2C are schematic diagrams showing the writing process of the operation method of the MLC memory device.
Fig. 3 is a flow chart showing the reading process of the operation method of the MLC memory device according to an embodiment.
4 is a flow chart of a write process of an operation method of a Triple-Level-Cell (TLC) memory device according to an embodiment.
5A to 5B are schematic views of the writing process of the operation method of the TLC memory device.
Fig. 6 is a flow chart showing the reading process of the operation method of the TLC memory device according to an embodiment.
Fig. 7 is a flow chart showing a write process of an operation method of a TLC memory device according to an embodiment.
8A to 8F are schematic diagrams showing the writing process of the operation method of the TLC memory device.
Fig. 9 is a flow chart showing the reading process of the operation method of the TLC memory device according to an embodiment.

[0008]

According to an embodiment, a method of operating an MLC memory device is provided. Fig. 1 is a flow chart showing the writing process of the operation method of the MLC memory device according to this embodiment.

【0009】

First, in step S102, a plurality of data is supplied to a controller. The data includes a first code, a second code, a third code, and a fourth code. The first code, the second code, the third code, and the fourth code are two bits. For example, each of the first code, the second code, the third code, and the fourth code may be one of codes 00, 01, 10, and 11.

[0010]

Next, in step S104, the controller calculates the respective numbers of the first code, the second code, the third code, and the fourth code. In step S106, a pairing rule is generated by the controller according to the respective numbers of the first code, the second code, the third code, and the fourth code. In the mapping rule, the first code, the second code, the third code, and the fourth code are respectively mapped to a first verification voltage level, a second verification voltage level, and a third verification voltage, which are sequentially arranged from low to high. One of the level and the fourth verification voltage level. For example, the first verification voltage level is an erase verification level (EV), and the second verification voltage level, the third verification voltage level, and the fourth verification voltage level may be write verification levels (PV1, PV2, PV3). In an example, in the mapping rule, the largest number of the first code, the second code, the third code, and the fourth code is mapped to the first verify voltage level. In another example, in the mapping rule, the largest number of the first code, the second code, the third code, and the fourth code is mapped to the second verify voltage level. The mapping rules can be stored in an MLC memory device or external memory. Since there are a total of 24 mapping rules, only five bits (less than one byte) are needed to store the mapping rules used.

[0011]

Thereafter, in step S108, the data is written into a memory array of the MLC memory device according to the mapping rule. Step S108 may include writing a write command to a page buffer of the MLC memory device and writing data from the page buffer to the memory array. In some examples, an error correction code can be calculated prior to writing an instruction to the page buffer.

[0012]

In some examples, prior to writing the data to the array of MLC memory devices (S108), the original data may be converted according to the mapping rules. After the original data is converted, the data is written to the page buffer of the MLC memory device. This conversion step can be performed by the controller. Alternatively, the conversion step can be implemented in a software management layer, such as a Flash Translation Layer (FTL), or a flash file system.

[0013]

An example of the writing process of the operation method of the MLC memory device is now provided, as shown in FIGS. 2A-2C. As shown in Figure 2A, sixteen pieces of data to be written are provided. These materials include four codes 00, 01, 10 and 11. The data includes a first write page bit 152 to be written and a second write page bit 154 to be written.

[0014]

The number of four codes 00, 01, 10, and 11 is calculated. The result is seven codes 00, five codes 01, one code 10, and three codes 11. That is to say, the codes are sorted from the most to the least to 00, 01, 11, and 10.

[0015]

Here, four verification voltage levels are provided, including a first verification voltage level, a second verification voltage level, a third verification voltage level, and a fourth verification voltage level. In the preset mapping rule, the first verification voltage level corresponds to the code 11, the second verification voltage level corresponds to the code 10, the third verification voltage level corresponds to the code 00, and the fourth verification voltage level corresponds to the code 01.

[0016]

In an example, since the most numbered code is code 00, code 00 is mapped to the first verify voltage level. Codes 01, 11, and 10 are respectively mapped to a second verification voltage level, a third verification voltage level, and a fourth verification voltage level. The codes 00, 01, 10, and 11 can then be converted to codes 11, 10, 00, and 01 and written to the array of MLC memory devices. The result of the write is shown in Figure 2B, where the first write page bit 156 and the second write page bit 158 written are different from the first write page bit 152 that was originally written. And a second write page bit 154 that is to be written. In this example, write disturb can be greatly reduced. In addition, the bit error rate can be reduced.

[0017]

In another example, the most numerous code, ie, code 00, is mapped to a second verify voltage level. Codes 01, 11, and 10 are respectively mapped to a first verification voltage level, a third verification voltage level, and a fourth verification voltage level. The codes 00, 01, 10, and 11 can then be converted to codes 10, 11, 00, and 01 and written to the array of MLC memory devices. The result of the writing is shown in Figure 2C, in which the first written page bit 160 written and the second written page bit 162 written are different from the first written page bit 152 that was originally written. And a second write page bit 154 that is to be written. In this example, write disturb can be reduced and the bit error rate can be greatly reduced. Users can choose the mapping rules according to their needs.

[0018]

Fig. 3 is a flow chart showing the reading process of the operation method of the MLC memory device according to this embodiment. First, in step S132, the mapping rule is obtained by the controller. At step S134, data is read from the memory array of the MLC memory device according to the mapping rule. In the mapping rule, the first verification voltage level, the second verification voltage level, the third verification voltage level, and the fourth verification voltage level, which are sequentially arranged from low to high, are respectively mapped to the first code and the second code. One of the encoding, the third encoding, and the fourth encoding. Thereafter, in step S136, the material is output. In some examples, data read from the memory array of the MLC memory device may be converted by the controller, flash translation layer, or flash file system prior to outputting the data.

[0019]

Now, according to an embodiment, a method of operating a TLC memory device is provided. Fig. 4 is a flow chart showing the writing process of the operation method of the TLC memory device according to this embodiment.

[0020]

First, in step S202, a plurality of data is supplied to a controller. The data includes a first code, a second code, a third code, a fourth code, a fifth code, a sixth code, a seventh code, and an eighth code. The first code, the second code, the third code, the fourth code, the fifth code, the sixth code, the seventh code, and the eighth code are three bits. For example, each of the first code, the second code, the third code, the fourth code, the fifth code, the sixth code, the seventh code, and the eighth code may be coded 000, 001, 010, 011, 100, One of 101, 110 and 111.

[0021]

Next, in step S204, the controller calculates the respective numbers of the first code, the second code, the third code, the fourth code, the fifth code, the sixth code, the seventh code, and the eighth code. In step S206, a pairing rule is generated by the controller according to the respective numbers of the first code, the second code, the third code, the fourth code, the fifth code, the sixth code, the seventh code, and the eighth code. In the mapping rule, the first coding, the second coding, the third coding, the fourth coding, the fifth coding, the sixth coding, the seventh coding, and the eighth coding are respectively mapped to the first in order from low to high. Verifying the voltage level, the second verifying voltage level, the third verifying voltage level, the fourth verifying voltage level, the fifth verifying voltage level, the sixth verifying voltage level, the seventh verifying voltage level, and an eighth Verify one of the voltage levels. For example, the first verification voltage level is an erase verification level (EV), a second verification voltage level, a third verification voltage level, a fourth verification voltage level, a fifth verification voltage level, and a sixth The verification voltage level, the seventh verification voltage level, and the eighth verification voltage level may be write verification levels (PV1, PV2, PV3, PV4, PV5, PV6, PV7). The mapping rules can be stored in a TLC memory device or external memory. Since there are a total of 40,320 mapping rules, only two bytes are needed to store the mapping rules used.

[0022]

Thereafter, in step S208, the data is written into a memory array of the TLC memory device according to the mapping rule. Step S208 may include writing a write command to a page buffer of the TLC memory device and writing data from the page buffer to the memory array. In some examples, the error correction code can be calculated prior to writing an instruction to the page buffer.

[0023]

In some examples, prior to writing the data to the array of TLC memory devices (S208), the original data may be converted according to the mapping rules. After the original data is converted, the data is written to the page buffer of the TLC memory device. This conversion step can be performed by the controller. Alternatively, the conversion step can be implemented in a software management layer, such as a flash translation layer, or a flash file system.

[0024]

Here, an example of the writing process of the operation method of the TLC memory device is provided, as shown in FIGS. 5A to 5B. As shown in Figure 5A, sixteen pieces of data to be written are provided. These materials include eight codes 000, 001, 010, 011, 100, 101, 110 and 111. The data includes a first write page bit 252 to be written, a second write page bit 254 to be written, and a third write page bit 256 to be written.

[0025]

The number of eight codes 000, 001, 010, 011, 100, 101, 110, and 111 is calculated. The result is two codes 000, four codes 001, two codes 010, one code 011, one code 100, three codes 101, two codes 110, and one code 111. That is to say, the codes are sorted from the most to the least to 001, 101, 000, 010, 110, 011, 100, 111.

[0026]

Here, eight verification voltage levels are provided, including a first verification voltage level, a second verification voltage level, a third verification voltage level, a fourth verification voltage level, a fifth verification voltage level, and a sixth verification. Voltage level, seventh verification voltage level and eighth verification voltage level. In the preset mapping rule, the first verification voltage level corresponds to the code 011, the second verification voltage level corresponds to the code 010, the third verification voltage level corresponds to the code 000, and the fourth verification voltage level corresponds to the code 001, the fifth verification voltage level corresponds to the code 101, the sixth verification voltage level corresponds to the code 100, the seventh verification voltage level corresponds to the code 110, and the eighth verification voltage level corresponds to the code 111.

[0027]

In an example, since the most numbered code is code 001, the code 001 is mapped to the first verify voltage level. Codes 101, 000, 010, 110, 011, 100, and 111 are respectively mapped to a second verification voltage level, a third verification voltage level, a fourth verification voltage level, a fifth verification voltage level, and a sixth verification. Voltage level, seventh verification voltage level and eighth verification voltage level. Next, the codes 000, 001, 010, 011, 100, 101, 110, and 111 can be converted into codes 000, 011, 001, 100, 110, 010, 101, and 111, and written into the array of the TLC memory device. The result of the write is shown in Figure 5B, where the first write page bit 258, the written second write page bit 260, and the written third write page bit 262 are different from the original The first write page bit 252 to be written, the second write page bit 254 to be originally written, and the third write page bit 256 to be written originally. Users can choose the mapping rules according to their needs.

[0028]

Fig. 6 is a flow chart showing the reading process of the operation method of the TLC memory device according to an embodiment. First, in step S232, the mapping rule is read by the controller. In step S234, data is read from the memory array of the TLC memory device according to the mapping rule. In the mapping rule, the first verification voltage level, the second verification voltage level, the third verification voltage level, the fourth verification voltage level, the fifth verification voltage level, and the sixth are sequentially arranged from low to high. Verifying that the voltage level, the seventh verifying voltage level, and the eighth verifying voltage level are respectively mapped to the first code, the second code, the third code, the fourth code, the fifth code, the sixth code, the seventh code, and One of the eighth codes. Thereafter, in step S236, the material is output. In some examples, data read from the memory array of the TLC memory device may be converted by the controller, flash translation layer, or flash file system prior to outputting the data.

[0029]

In the above embodiments, the information has been determined. However, in some cases, the data may not be finalized and may change depending on the user's input. In the following, an embodiment of an operation method of the TLC memory device will be exemplarily provided.

[0030]

Fig. 7 is a flow chart showing the writing process of the operation method of the TLC memory device according to this embodiment. The write processing includes a step S302 of writing a first write page bit of the complex material to the first write page of the TLC memory device, and a second write page bit writing the data to the TLC memory device. Step S304 of writing a page, and step S306 of writing a third write page bit of the material to a third write page of the TLC memory device.

[0031]

In step S302, first, a plurality of first write page bits of the plurality of materials are provided, as by step S308. These first write page bits include code 0 and code 1. In step S310, the number of codes 0 and 1 in the first written page bit is calculated by a controller. In step S312, a first mapping rule is generated by the controller according to the respective numbers of the encoding 0 and the encoding 1 in the first written page bit. Next, in step S314, the first write page bit is written into a first write page of the TLC memory device according to the first mapping rule.

[0032]

In step S304, first, a plurality of second write page bits of the material are provided, as by step S316. These second write page bits include code 0 and code 1. In step S318, under each of the code 0 and the code 1 of the first page bit, the controller calculates the number of codes 0 and 1 in the second page bit. In step S320, a second mapping rule is generated by the controller according to the respective numbers of the encoding 0 and the encoding 1 in the second written page bit. Next, in step S322, the second write page bit is written into a second write page of the TLC memory device according to the second mapping rule.

[0033]

In step S306, first, a plurality of third write page bits of the material are provided, as by step S324. These third write page bits include code 0 and code 1. In step S326, the third write page bit is calculated by the controller under each of the code 0 and the code 1 of the first write page bit and the code 0 and the code 1 of the second write page bit. The number of codes 0 and 1 is the same. In step S328, a third mapping rule is generated by the controller according to the respective numbers of the encoding 0 and the encoding 1 in the third written page bit. Next, in step S330, the third write page bit is written into a third write page of the TLC memory device according to the third mapping rule.

[0034]

An example of the write processing of the TLC memory device operation method according to this embodiment is provided herein, as shown in FIGS. 8A to 8F. In this example, sixteen pieces of data to be written are provided. In the preset mapping rule, the first verification voltage level corresponds to the code 011, the second verification voltage level corresponds to the code 010, the third verification voltage level corresponds to the code 000, and the fourth verification voltage level corresponds to the code 001, the fifth verification voltage level corresponds to the code 101, the sixth verification voltage level corresponds to the code 100, the seventh verification voltage level corresponds to the code 110, and the eighth verification voltage level corresponds to the code 111.

[0035]

Referring to Figure 8A, a first write page bit 352 of the material to be written is first provided. The first write page bit 352 to be written includes codes 0 and 1. Calculate the number of codes 0 and 1 . The result is nine codes of 0 and seven codes of 1. Since the number of codes 0 is more than the number of codes 1, it is not necessary to convert them. Next, the code 0 is mapped to a first verify voltage level (EV), and the code 1 is mapped to a fifth verify voltage level (PV4). The first written page bit 354 written is shown in Figure 8B.

[0036]

Referring to Figure 8C, a second write page bit 356 to be written is provided. The second write page bit 356 to be written includes codes 0 and 1. The second write page bit 356 to be written is divided into two groups A1 and A2 according to the corresponding first write page bit 354. The number of codes 0 and 1 of the second write page bit of the first group A1 is calculated. The result is six codes of 0 and three codes of 1. Since the number of codes 0 is more than the number of codes 1, the code 0 and the code 1 are converted. The converted code 00 is maintained at the first verify voltage level (EV), and the converted code 01 is mapped to the third verify voltage level (PV2). The number of codes 0 and 1 of the second group A2 is calculated. The result is four codes of 0 and three codes of 1. Since the number of codes 0 is more than the number of codes 1, it is not necessary to convert the code 0 and code 1 of the second group A2. Code 10 is maintained at a fifth verify voltage level (PV4) and code 11 is mapped to a seventh verify voltage level (PV6). The written second write page bit 358 is shown in Figure 8D.

[0037]

Referring to Figure 8E, a third write page bit 360 to be written is provided. The third write page bit 360 to be written includes codes 0 and 1. The third write page bit 360 to be written is divided into four groups B1, B2, B3, and B4 according to the corresponding first write page bit 354 and corresponding second write page bit 358. The number of codes 0 and 1 of the third page of the first page B1 of the first group B1 is calculated. The result is four codes 1 and two codes 0. Since the number of codes 1 is more than the number of codes 0, they need not be converted. Code 001 is maintained at a first verify voltage level (EV) and code 000 is mapped to a second verify voltage level (PV1). The number of codes 0 and 1 of the second group B2 is calculated. The result is two codes of 0 and one code of 1. Since the number of codes 0 is more than the number of codes 1, it is not necessary to convert them. The code 010 is maintained at the third verify voltage level (PV2) and the code 011 is mapped to the fourth verify voltage level (PV3). The number of codes 0 and 1 of the third group B3 is calculated. The result is three codes of 0 and one code of 1. Since the number of codes 0 is more than the number of codes 1, the code 0 and code 1 of the third group B3 are converted. The converted code 101 is maintained at a fifth verify voltage level (PV4), and the converted code 100 is mapped to a sixth verify voltage level (PV5). The number of codes 0 and 1 of the fourth group B4 is calculated. The result is two codes 1 and one code 0. Since the number of codes 1 is more than the number of codes 0, the code 1 and code 0 of the fourth group B4 are converted. The converted code 110 is maintained at the seventh verify voltage level (PV6), and the converted code 111 is mapped to the eighth verify voltage level (PV7). The written third write page bit 362 is shown in Figure 8F.

[0038]

The mapping rules can be stored in a TLC memory device or external memory. The mapping rule of the first write page requires one bit, the mapping rule of the second write page requires two bits, and the mapping rule of the third write page requires four bits. Take it all together, just use one byte.

[0039]

Fig. 9 is a flow chart showing the reading process of the operation method of the TLC memory device according to this embodiment. In step S332, the first mapping rule, the second mapping rule, and the third mapping rule are obtained by the controller. In step S334, the first write page bit, the second write page bit, and the third write of the data are read from the TLC memory device according to the first mapping rule, the second mapping rule, and the third mapping rule. Page bit. Thereafter, in step S336, the material is output. In some examples, only the first write page bit, the second write page bit, or the third write page bit are required. At this time, the controller only obtains the corresponding first mapping rule, second mapping rule or third mapping rule, and only reads the required bits according to the corresponding mapping rule.

[0040]

In the above embodiment, the probability of writing the slow memory cell to a higher threshold voltage state (e.g., the fourth verify voltage level or the eighth verify voltage level) is reduced because of the mapping of the memory cells. Therefore, write disturbance caused by slow memory cells is reduced. In addition, the interference caused by the pass voltage _Vpass is also reduced. The operation method according to the above embodiment can be applied to a flash memory device. Although the above embodiment uses the MLC and TLC memory devices as an example, other memory devices (such as a Quad-Level-Cell (QLC) memory device) can adopt a similar operation method. Alternatively, these methods can be used with advanced memory devices such as phase change random access memory (PRAM) or phase change memory (PCM).

[0041]

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

S102, S104, S106, S108‧‧‧ steps

Claims (9)

[Item 1] A method of operating a memory device, comprising:
Write to a memory device, including:
Providing plural data to a controller, the data including a complex code;
Calculating the respective numbers of the codes by the controller;
A mapping rule is generated by the controller according to the respective numbers of the codes, wherein, in the mapping rule, the codes are respectively mapped to a complex verification voltage level sequentially arranged from low to high ( One of verifying voltage levels; and writing the data to a memory array of the memory device according to the mapping rule. [Item 2] The operation method of claim 1, wherein the codes include a first code, a second code, a third code, and a fourth code, the first code, the second code, the third code, and the The fourth code is a two-bit, and wherein in the mapping rule, the first code, the second code, the third code, and the fourth code are each mapped to a first verification that is sequentially arranged from low to high. One of a voltage level, a second verification voltage level, a third verification voltage level, and a fourth verification voltage level. [Item 3] The method of operation of claim 2, wherein in the mapping rule, one of the first number, the second code, the third code, and the fourth code is the largest one Up to the first verification voltage level. [Item 4] The method of operation of claim 2, wherein in the mapping rule, one of the first number, the second code, the third code, and the fourth code is the largest one Up to the second verification voltage level. [Item 5] The operating method of claim 1, wherein the encoding comprises a first encoding, a second encoding, a third encoding, a fourth encoding, a fifth encoding, a sixth encoding, a seventh encoding, and an eighth encoding, The first code, the second code, the third code, the fourth code, the fifth code, the sixth code, the seventh code, and the eighth code are three bits, and wherein the pair is In the rule, the first code, the second code, the third code, the fourth code, the fifth code, the sixth code, the seventh code, and the eighth code are respectively mapped to a lower order a first verification voltage level, a second verification voltage level, a third verification voltage level, a fourth verification voltage level, a fifth verification voltage level, a sixth verification voltage level, and a seventh verification voltage level One of the bit and the eighth verification voltage level. [Item 6] For example, the operation method described in claim 1 of the patent scope further includes:
Reading the memory device, including:
Obtaining the mapping rule by the controller;
And reading the data from the memory array of the memory device according to the mapping rule, wherein, in the mapping rule, the verify voltage levels sequentially arranged from low to high are respectively mapped to the codes One of them; and output the information. [Item 7] A method of operating a memory device, comprising:
Write to a memory device, including:
Providing a plurality of first write page bits of the plurality of data, wherein the first write page bits include code 0 and code 1;
Calculating, by a controller, the number of each of the code 0 and the code 1 in the first write page bit;
Generating a first mapping rule by the controller according to the number of the code 0 and the code 1 in the first write page bit;
Writing the first write page bits to a first write page of the memory device according to the first mapping rule;
Providing a plurality of second write page bits of the data, wherein the second write page bits include code 0 and code 1;
Under the code 0 and the code 1 of the first write page bit, the controller calculates the number of each of the code 0 and the code 1 in the second page write bits;
Generating a second mapping rule by the controller according to the number of the code 0 and the code 1 in the second write page bit;
Writing the second write page bits to a second write page of the memory device according to the second mapping rule;
Providing a plurality of third write page bits of the data, wherein the third write page bits include code 0 and code 1;
The controller calculates the number of the code 0 and the code 1 and the code 0 and the code 1 of the second write page bit. The number of the code 0 and the code 1 in the third write page bit;
Generating a third mapping rule by the controller according to the number of the code 0 and the code 1 in the third write page bit; and writing the third write page according to the third mapping rule The bit is in a third write page of the memory device. [Item 8] For example, the operation method described in claim 7 of the patent scope further includes:
Reading the memory device, including:
Obtaining, by the controller, the first mapping rule, the second mapping rule, and the third mapping rule;
Reading the first write page bits and the second write page bits of the data from the memory device according to the first mapping rule, the second mapping rule, and the third mapping rule And the third write page bit; and outputting the data. [Item 9] For example, the operation method described in claim 7 of the patent scope further includes:
Reading the memory device, including:
Obtaining, by the controller, the first mapping rule, the second mapping rule, or the third mapping rule;
Reading the first write page bits, the second write pages of the corresponding materials from the memory device according to the first mapping rule, the second mapping rule, or the third mapping rule a bit or the third write page bit; and the first write page bit, the second write page bit or the third write page bit that output the data.