JP6710298B2 - Memory system - Google Patents

Description

Embodiments of the present invention relate to memory systems .

In a NAND flash memory (hereinafter referred to as a NAND memory), information is stored by the amount of electric charge stored in the floating gate of a memory cell. Each memory cell has a threshold voltage according to the amount of charge. A plurality of data values stored in the memory cell are made to correspond to a plurality of threshold voltage regions, respectively, and charges are injected so that the threshold voltage of the memory cell becomes a region corresponding to the stored data value. Then, at the time of reading, the data value stored in the memory cell can be obtained by determining in which region the threshold voltage of the memory cell exists.

In a 3 bit/cell NAND memory capable of storing 3 bits in one memory cell, a threshold is compared with a 1 bit/cell capable of storing 1 bit in one memory cell or a 2 bit/cell NAND memory capable of storing 2 bit in one memory cell. There are many value voltage regions. Therefore, the 3-bit/Cell NAND memory requires a higher threshold voltage adjustment accuracy than the 1-bit/Cell or 2-bit/Cell NAND memory, and the mutual interference between cells becomes large.

In recent generations of miniaturized NAND memories, generally, a method of simultaneously writing (programming) all bits stored in one memory cell is taken in order to avoid mutual interference between cells.

On the other hand, if the mutual interference between cells is not so great, the bits to be stored in one memory cell may be programmed one by one. The 1-2-4 coding is known as a method for programming the memory cells of 3 bits/Cell by 1 bit in this way. This method is a coding method in which 7 bits between 8 threshold voltage regions of 3 bits/Cell are divided into 1 bit, 2 bits and 4 bits, respectively.

US Pat. No. 8054684 U.S. Patent No. 8472280

When the bits stored in one memory cell are sequentially programmed one by one, the degree of freedom at the time of programming increases, but in the above-mentioned conventional 1-2-4 coding, the deviation of the number of boundaries between bits is significant. Therefore, there is a high possibility that an error will occur in a bit having a large number of boundaries.

According to one embodiment of the present invention, a memory system includes a word line and a plurality of memories , each of which is connected to the word line and can store 3-bit data, corresponding to a first page to a third page. A non-volatile memory including a cell, and a memory controller that controls writing to the non-volatile memory. The non-volatile memory controls to write the data requested to be written from the memory controller to the memory cell, and when writing the first page to the erased memory cell, when the written data has the first value, When the threshold voltage is programmed to be in the second threshold region and the second page is written after the first page is written, the value corresponding to the first page is set to the second value. And the data to be written to the second page is the first value, the threshold voltage is programmed to be in the fourth threshold region, and the value corresponding to the first page is set to the first value. And the data to be written in the second page is the first value, the threshold voltage is programmed to be in the third threshold region, and the memory in which the second page is written is written. When writing the third page to the cell, the value corresponding to the first page is the second value, the value corresponding to the second page is the second value, and the data to be written to the third page is In the case of the first value, the threshold voltage of the memory cell is programmed to be in the sixth threshold region, and the value corresponding to the first page is the first value and corresponds to the second page. If the value is the second value and the data to be written to the third page is the first value, the threshold voltage is programmed to be in the seventh threshold region, and the value corresponding to the first page is set. Is the first value, the value corresponding to the second page is the first value, and the data to be written to the third page is the first value, the threshold voltage becomes the eighth threshold region. And the value corresponding to the first page is the second value, the value corresponding to the second page is the first value, and the data to be written to the third page is the first value. The threshold voltage is programmed to be the fifth threshold region, and the n-th threshold region (n is an integer of 2 or more and 8 or less) from the voltage value of the (n-1)th threshold region. a controller is large voltage value).

FIG. 1 is a block diagram showing a configuration example of a storage device according to the first embodiment. FIG. 2 is a block diagram showing a configuration example of the non-volatile memory according to the first embodiment. FIG. 3 is a diagram showing an example of the threshold region according to the first embodiment. FIG. 4 is a diagram showing data coding according to the first embodiment. FIG. 5 is a diagram showing the threshold voltage distribution after programming for the memory cell in the first embodiment. FIG. 6 is a diagram showing a method of reading a Lower page according to the first embodiment. FIG. 7 is a diagram showing a method of reading a Middle page according to the first embodiment. FIG. 8 is a diagram showing a method of reading the Upper page according to the first embodiment. FIG. 9 is a flowchart showing an example of the writing procedure of the first embodiment. FIG. 10 is a flowchart showing an example of the reading procedure according to the first embodiment. FIG. 11 is a diagram showing data coding according to the second embodiment. FIG. 12 is a diagram showing a threshold distribution after programming of the memory cell according to the second embodiment. FIG. 13 is a diagram showing a method of reading a Lower page according to the second embodiment. FIG. 14 is a diagram showing a method of reading a Middle page according to the second embodiment. FIG. 15 is a diagram showing a method of reading an Upper page according to the second embodiment. FIG. 16 is a flowchart showing an example of the reading procedure according to the second embodiment. FIG. 17 is a diagram showing data coding according to the third embodiment. FIG. 18 is a diagram showing a threshold distribution after programming of the memory cell according to the third embodiment. FIG. 19 is a diagram showing data coding according to the fourth embodiment. FIG. 20 is a diagram showing a threshold distribution after programming of the memory cell according to the fourth embodiment. FIG. 21 is a diagram showing data coding according to the fifth embodiment. FIG. 22 is a diagram showing the threshold voltage distribution after programming for the memory cell in the fifth embodiment. FIG. 23 is a diagram showing data coding according to the sixth embodiment. FIG. 24 is a diagram showing the threshold voltage distribution after programming for the memory cell in the sixth embodiment. FIG. 25 is a diagram showing an example of variations in the threshold distribution. FIG. 26 is a diagram showing an example of the read procedure of the seventh embodiment when the read voltage is changed. FIG. 27 is a diagram showing an example of a state of soft bits. FIG. 28 is a diagram showing an example of the threshold distribution after programming of each page in the ninth embodiment. FIG. 29 is a diagram showing an example of the threshold distribution after programming of each page in the tenth embodiment. FIG. 30 is a diagram showing an example of the threshold distribution after programming of each page in the eleventh embodiment.

Hereinafter, a nonvolatile memory and a writing method according to embodiments will be described in detail with reference to the accompanying drawings. The present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a block diagram showing a configuration example of a storage device according to the first embodiment. The storage device of this embodiment includes a memory controller 1 and a non-volatile memory 2. The storage device can be connected to the host. The host is, for example, an electronic device such as a personal computer or a mobile terminal.

The nonvolatile memory 2 is a memory that stores data in a nonvolatile manner, and is, for example, a NAND memory. In the present embodiment, the nonvolatile memory 2 will be described as a NAND memory having memory cells capable of storing 3 bits per memory cell, that is, a 3 bit/Cell NAND memory.

The memory controller 1 controls writing to the nonvolatile memory 2 according to a write command from the host. Further, the memory controller 1 controls reading from the non-volatile memory 2 according to a read command from the host. The memory controller 1 includes a RAM 11, a processor 12, a host interface 13, an ECC circuit 14 and a memory interface 15. A RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC circuit 14, and a memory interface 15 are connected to each other by an internal bus 16.

The host interface 13 outputs commands, user data (write data), etc. received from the host to the internal bus 16. Further, the host interface 13 transmits user data read from the non-volatile memory 2 and a response from the processor 12 to the host.

The memory interface 15 controls a process of writing user data and the like to the non-volatile memory 2 and a process of reading from the non-volatile memory 2 based on an instruction from the processor 12.

The processor 12 centrally controls the memory controller 1. The processor 12 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), or the like. When the processor 12 receives a command from the host via the host interface 13, the processor 12 performs control according to the command. For example, the processor 12 instructs the memory interface 15 to write user data and parity in the nonvolatile memory 2 according to a command from the host. Further, the processor 12 instructs the memory interface 15 to read the user data and the parity from the non-volatile memory 2 according to the command from the host.

The processor 12 determines a storage area (memory area) on the nonvolatile memory 2 for the user data accumulated in the RAM 11. User data is stored in the RAM 11 via the internal bus 16. The processor 12 determines the memory area for page-based data (page data) that is a writing unit. In this specification, user data stored in one page of the non-volatile memory 2 is defined as unit data. The unit data is generally encoded and stored in the non-volatile memory 2 as a code word. In the present embodiment, the encoding is not essential, and the unit data may be stored in the non-volatile memory 2 without being encoded, but FIG. 1 shows a configuration in which the encoding is performed as one configuration example. .. When not encoded, the page data matches the unit data. Further, one codeword may be generated based on one unit data, or one codeword may be generated based on divided data obtained by dividing the unit data. Moreover, one codeword may be generated using a plurality of unit data.

The processor 12 determines the memory area of the nonvolatile memory 2 of the writing destination for each unit data. A physical address is assigned to the memory area of the nonvolatile memory 2. The processor 12 manages the memory area of the unit data write destination by using the physical address. The processor 12 instructs the memory interface 15 to write the user data in the nonvolatile memory 2 by designating the determined memory area (physical address). The processor 12 manages the correspondence between the logical address of the user data (logical address managed by the host) and the physical address. When the read command including the logical address is received from the host, the physical address corresponding to the logical address is specified, and the physical address is specified to instruct the memory interface 15 to read the user data.

In this specification, memory cells commonly connected to one word line are defined as a memory cell group. In the present embodiment, the nonvolatile memory 2 is a 3-bit/Cell NAND memory, and one memory cell group corresponds to three pages. The 3 bits of each memory cell correspond to these 3 pages, respectively. In the present embodiment, these three pages are called Lower page (first page), Middle page (second page), Upper page (third page).

The ECC circuit 14 encodes the user data stored in the RAM 11 to generate a code word. The ECC circuit 14 also decodes the codeword read from the nonvolatile memory 2.

The RAM 11 temporarily stores the user data received from the host until it is stored in the non-volatile memory 2 or the data read from the non-volatile memory 2 before being transmitted to the host. The RAM 11 is a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

FIG. 1 shows a configuration example in which the memory controller 1 includes the ECC circuit 14 and the memory interface 15, respectively. However, the ECC circuit 14 may be built in the memory interface 15. Further, the ECC circuit 14 may be built in the nonvolatile memory 2.

FIG. 2 is a block diagram showing a configuration example of the nonvolatile memory 2 of the present embodiment. The nonvolatile memory 2 includes a NAND I/O Interface 21, a control unit 22, a NAND memory cell array (memory cell unit) 23, and a page buffer 24. The nonvolatile memory 2 is composed of, for example, a one-chip semiconductor substrate (for example, a silicon substrate).

The control unit 22 controls the operation of the nonvolatile memory 2 based on a command or the like input from the memory controller 1 via the NAND I/O Interface 21. Specifically, when a write request is input, the data requested to be written is controlled to be written to a specified address on the NAND memory cell array 23. Further, when a read request is input, the control unit 22 controls the read requested data to be read from the NAND memory cell array 23 and output to the memory controller 1 via the NAND I/O interface 21. The page buffer 24 is a buffer for temporarily storing the data input from the memory controller 1 when writing to the NAND memory cell array 23 and temporarily storing the data read from the NAND memory cell array 23.

FIG. 3 is a diagram showing an example of the threshold region of this embodiment. In the NAND memory, information is stored by the amount of electric charge stored in the floating gate of the memory cell. Each memory cell has a threshold voltage according to the amount of charge. Then, the plurality of data values stored in the memory cell are made to correspond to the plurality of threshold voltage regions (threshold regions), respectively. Eight distributions (mountain type) described as Er, A, B, C, D, E, F, G in FIG. 3 indicate respective threshold distributions within the eight threshold regions. The horizontal axis of FIG. 3 represents the threshold voltage, and the vertical axis represents the distribution of the number of memory cells (the number of cells). In the present embodiment, a region where the threshold voltage is Vr1 or lower is called region Er, a region where the threshold voltage is higher than Vr1 and Vr2 is lower than region A, and the threshold voltage is higher than Vr2 and Vr3. The region having the following voltage is referred to as region B, the region having the threshold voltage higher than Vr3 and not higher than Vr4 is referred to as region C, and the region having the threshold voltage higher than Vr4 and not higher than Vr5 is referred to as region D. A region where the value voltage is higher than Vr5 and lower than Vr6 is called region E, a region where the threshold voltage is higher than Vr6 and lower than Vr7 is called region F, and a region where the threshold voltage is higher than Vr7 is called region G. .. Further, the threshold distributions corresponding to the regions Er, A, B, C, D, E, F, and G are distributed to Er, A, B, C, D, E, F, and G (first to eighth). Distribution). Vr1 to Vr7 are threshold voltages that serve as boundaries between regions.

In the NAND memory, a plurality of data values are associated with a plurality of threshold regions (that is, threshold distributions) of memory cells. This correspondence is called data coding. This data coding is determined in advance, and at the time of writing (programming) data, charges are injected into the memory cell so as to be within the threshold region according to the data value stored according to the data coding. Then, at the time of reading, a read voltage is applied to the memory cell, and the data is determined depending on whether the threshold voltage of the memory cell is lower or higher than the read voltage. When the threshold voltage is lower than the read voltage, the data value in the “erased” state is defined as “1”. If the threshold voltage is greater than or equal to the read voltage, it is in the "programmed" state and the data is defined as "0".

FIG. 4 is a diagram showing data coding according to the present embodiment. In the present embodiment, the eight threshold distributions (threshold regions) shown in FIG. 3 are made to correspond to eight 3-bit data values, respectively. As shown in FIG. 4, the memory cell whose threshold voltage is within the Er region is in a state where “111” is stored as the data value of the bit corresponding to the Upper, Middle, and Lower pages. A memory cell whose threshold voltage is within the area A is in a state of storing "110". A memory cell whose threshold voltage is within the B region is in a state of storing "100". A memory cell whose threshold voltage is within the C region is in a state of storing "101". A memory cell whose threshold voltage is within the D region is in a state of storing "001". A memory cell whose threshold voltage is within the E region is in a state of storing "011". A memory cell whose threshold voltage is within the F region is in a state of storing "010". A memory cell whose threshold voltage is within the G region is in a state of storing "000". When the memory cell is in the unwritten state (“erased” state), the threshold voltage of the memory cell is within the Er region. As described above, the coding shown in FIG. 4 is a Gray code in which data changes only by 1 bit between any two adjacent regions.

In the coding of the present embodiment shown in FIG. 4, the threshold voltage serving as a boundary for determining the bit value of the Upper page is Vr4. The threshold voltages serving as boundaries for determining the bit value of the Middle page are Vr2, Vr5, and Vr7. The threshold voltages that are boundaries for determining the bit value of the Lower page are Vr1, Vr3, and Vr6. The number of threshold voltages (hereinafter, referred to as a boundary number) serving as a boundary for determining a bit value is 1, 3, and 3 in Upper page, Middle page, and Lower page, respectively. Hereinafter, such coding is referred to as 1-3-3 coding by using the boundary numbers of the Upper page, Middle page, and Lower page. What should be noted here is that the maximum number of boundaries that change between adjacent data for each page is three. The control unit 22 of the non-volatile memory 2 controls the program to the NAND memory cell array 23 and the read from the NAND memory cell array 23 based on the coding shown in FIG.

As a programming method for a 3-bit/Cell NAND memory, there is known a method of simultaneously writing data of three pages stored in one memory cell group. However, with this method, data cannot be written page by page, and data cannot be written until data for three pages has been prepared. In order to perform writing efficiently, it is desirable that writing can be performed page by page. As an example of sequentially programming one page at a time, 1-2-4 coding is known in which the numbers of boundaries of Upper page, Middle page, and Lower page are 1, 2, and 4, respectively. In this method, since the maximum number of boundaries is 4, the error occurrence rate becomes high in a page having many boundaries. The error correction capability when encoding user data will be implemented so as to be able to handle pages with a high error occurrence probability. Therefore, the cost and power consumption of the storage device for increasing the error correction capability are increased, and the writing and reading speeds are reduced. Therefore, it is desired that the error occurrence probabilities be as biased as possible among the pages.

In this embodiment, writing can be performed page by page as described later. Furthermore, as described above, the 1-3-3 coding is performed, and the number of boundaries between pages is less biased. As a result, the cost and power consumption of the storage device can be suppressed and the writing and reading speeds can be increased as compared with the 1-2-4 coding. Further, as will be described later, a correct read result can be obtained even if any of the Upper page, the Middle page, and the Lower page is read without managing the information up to which page has been written.

FIG. 5 is a diagram showing a threshold distribution after programming of the memory cell according to the present embodiment. 5A shows the threshold distribution after programming of the Lower page, FIG. 5B shows the threshold distribution after programming of the Middle page, and FIG. 5C shows that of the Upper page. The threshold distribution after programming is shown. In this embodiment, it is possible to program one page at a time, but the order of programming is fixed, and the lower page, the middle page, and the upper page are written in that order. However, it is not necessary to continuously write the Lower page, Middle page, and Upper page of one memory cell group. For example, the lower page of the first memory cell group is written, the lower page of the second memory cell group is written,..., And then, the Middle page of the first memory cell group is written. Writing can be performed.

All the memory cells of the NAND memory cell array 23 are in a state of distribution Er which is an unwritten state (“erased” state). As shown in FIG. 5A, the control unit 22 of the nonvolatile memory 2 keeps the distribution Er for each memory cell according to the bit value written (stored) in the Lower page in the program of the Lower page. , Or injecting charge to move it to the next higher distribution A. Specifically, when the bit value written to the Lower page is “1”, no charge is injected, and when the bit value written to the Lower page is “0”, the charge is injected to distribute the threshold voltage. Program to move to A.

When writing to the memory cell group for which writing of the Lower page has been performed, the control unit 22 executes the programming of the Middle page, as shown in FIG. Specifically, for the memory cells that were in the distribution Er state due to the programming of the Lower page, if the bit value written to the Middle page is “1”, the distribution Er remains unchanged and the bit value written to the Middle page remains unchanged. If it is "0", the program is moved to the distribution C. For the memory cells that were in the distribution A state due to the programming of the Lower page, if the bit value written to the Middle page is “1”, the distribution A remains as it is, and the bit value written to the Middle page is “0”. If, then program to move to distribution B.

When writing is performed to the memory cell group in which the Middle page has been written, the control unit 22 executes the Upper page program, as shown in FIG. Specifically, for the memory cells that have been in the distribution Er state by programming the Middle page, if the bit value to be written in the Upper page is “1”, the distribution Er is left unchanged, and the bit value to be written in the Upper page is In the case of "0", the program is moved to the distribution E. For the memory cells that were in the distribution A state due to the programming of the Middle page, if the bit value written to the Upper page is “1”, the distribution A remains as it is, and the bit value written to the Upper page is “0”. If, then program to move to distribution F. For the memory cells that were in the distribution B state due to the programming of the Middle page, if the bit value written to the Upper page is “1”, the distribution B remains as it is and the bit value written to the Upper page is “0”. If, then program to move to distribution G. For the memory cells that were in the distribution C state due to the programming of the Middle page, if the bit value written to the Upper page is “1”, the distribution C remains as it is and the bit value written to the Upper page is “0”. If, then program to move to distribution D.

As described above, in the present embodiment, the control unit 22 does not inject charges when the bit value to be written is “1” and the bit value to be written is “0” in any page program. In the first step, charges are injected to move to a distribution with a higher threshold voltage than before programming.

Note that the programming is typically performed by applying the programming voltage pulse once or a plurality of times. After each program voltage pulse, a read is performed to see if the cell has moved above the threshold boundary level. By repeating this, the threshold value of the memory cell is moved within the range of the predetermined threshold distribution (threshold region). The specific procedure of the program is not limited to this example.

Next, reading according to this embodiment will be described. FIG. 6 is a diagram showing a method of reading a Lower page according to the present embodiment. In this embodiment, the bit value of the Lower page can be read by applying three read voltages, Vr1, Vr3, and Vr6, regardless of which page is being written.

FIG. 6A shows a state in which the Lower page is written and the Middle page and the Upper page are not written by the programming method of the present embodiment shown in FIG. In this state, when three of Vr1, Vr3, and Vr6 are applied as the read voltage, the memory cell storing the bit value “1” is determined to have the threshold voltage less than Vr1, and the bit of the Lower page is determined. The value read result is "1". On the other hand, the memory cell storing the bit value “0” is determined to have the threshold voltage of Vr1 or more and less than Vr3, and the result of reading the bit value of the Lower page is “0”.

FIG. 6B shows a state in which the Middle page is written and the Upper page is not written by the programming method of the present embodiment shown in FIG. In this state, when three of Vr1, Vr3, and Vr6 are applied as the read voltage, the memory cell storing the bit value “11” is determined to have the threshold voltage less than Vr1, and the bit of the Lower page is determined. The value read result is "1". The memory cell storing the bit value “10” and the memory cell storing the bit value “00” are determined to have the threshold voltage of Vr1 or more and less than Vr3, and the read result of the bit value of the Lower page Becomes "0". The memory cell storing the bit value “01” is determined to have the threshold voltage of Vr3 or more and less than Vr6, and the read result of the bit value of the Lower page becomes “1”.

FIG. 6C shows a state where the Upper page is written by the programming method of the present embodiment shown in FIG. When three voltages Vr1, Vr3, and Vr6 are applied as read voltages in this state, the memory cell storing the bit value “111” is determined to have a threshold voltage less than Vr1, and the bits of the Lower page are The value read result is "1". The memory cell storing the bit value “110” and the memory cell storing the bit value “100” are determined to have the threshold voltage of Vr1 or more and less than Vr3, and the read result of the bit value of the Lower page Becomes "0". The memory cell storing the bit value “101”, the memory cell storing the bit value “001”, and the memory cell storing the bit value “011” have threshold voltages of Vr3 or more and less than Vr6. It is determined that there is, and the result of reading the bit value of the Lower page is “1”. The memory cell storing the bit value “010” and the memory cell storing the bit value “000” are determined to have a threshold voltage of Vr6 or higher, and the read result of the bit value of the Lower page is “ It becomes 0".

As described above, the bit value of the Lower page can be correctly read by applying the three read voltages Vr1, Vr3, and Vr6 regardless of which page is being written.

FIG. 7 is a diagram showing a method of reading the Middle page according to the present embodiment. In the present embodiment, the bit value of the Middle page can be read by applying three voltages Vr2, Vr5, and Vr7 as the read voltage regardless of which page is being written.

FIG. 7A shows a state in which the Lower page is written and the Middle page and the Upper page are not written by the programming method of the present embodiment shown in FIG. In this state, when three of Vr2, Vr5, and Vr7 are applied as the read voltage, the memory cell storing the bit value “1” and the memory cell storing the bit value “0” are less than Vr2. It is determined to be the threshold voltage, and the result of reading the bit value of the Middle page is “1”. In this state, since the Middle page is not written, the bit value of the Middle page is "1" which indicates unwritten and is a correct value.

FIG. 7B shows a state in which the Middle page is written and the Upper page is not written by the programming method of the present embodiment shown in FIG. In this state, if three of Vr2, Vr5, and Vr7 are applied as the read voltage, the memory cell storing the bit value “11” and the memory cell storing the bit value “10” are less than Vr2. It is determined to be the threshold voltage, and the result of reading the bit value of the Middle page is “1”. The memory cell storing the bit value “00” and the memory cell storing the bit value “01” are determined to have the threshold voltage of Vr2 or more and less than Vr5, and the read result of the bit value of the Middle page Becomes "0".

FIG. 7C shows a state where the Upper page is written by the programming method of the present embodiment shown in FIG. In this state, if three voltages Vr2, Vr5, and Vr7 are applied as the read voltages, the memory cells storing the bit value “111” and the memory cells storing the bit value “110” are less than Vr2. It is determined to be the threshold voltage, and the result of reading the bit value of the Middle page is “1”. The memory cell storing the bit value “100”, the memory cell storing the bit value “101”, and the memory cell storing the bit value “001” have a threshold voltage of Vr2 or more and less than Vr5. It is determined that there is, and the result of reading the bit value of the Middle page is “0”. The memory cell storing the bit value “011” and the memory cell storing the bit value “010” are determined to have the threshold voltage of Vr5 or more and less than Vr7, and the read result of the bit value of the Middle page Becomes "1". The memory cell storing the bit value “000” is determined to have a threshold voltage of Vr7 or higher, and the result of reading the bit value of the Middle page is “0”.

As described above, the bit value of the Middle page can be correctly read by applying three of Vr2, Vr5, and Vr7 as the read voltage regardless of which page is being written.

FIG. 8 is a diagram showing a method of reading the Upper page according to the present embodiment. In the present embodiment, the bit value of the Upper page can be read by applying Vr4 as the read voltage regardless of which page is being written.

FIG. 8A shows a state where the Lower page is written and the Middle page and the Upper page are not written by the programming method of the present embodiment shown in FIG. In this state, when Vr4 is applied as the read voltage, it is determined that the memory cell storing the bit value “1” and the memory cell storing the bit value “0” have the threshold voltage lower than Vr4. Then, the reading result of the bit value of the Upper page becomes “1”. In this state, since the Upper page is not written, the bit value of the Upper page is “1”, which indicates unwritten, is a correct value.

FIG. 8B shows a state in which the Middle page is written and the Upper page is not written by the programming method of the present embodiment shown in FIG. When Vr4 is applied as the read voltage in this state, the memory cell storing the bit value “11”, the memory cell storing the bit value “10”, and the memory cell storing the bit value “00”. The memory cell storing the bit value “01” is determined to have a threshold voltage lower than Vr4, and the read result of the bit value of the Upper page is “1”. In this state, since the Upper page is not written, the bit value of the Upper page is “1”, which indicates unwritten, is a correct value.

FIG. 8C shows a state where the Upper page is written by the programming method of the present embodiment shown in FIG. When Vr4 is applied as a read voltage in this state, a memory cell storing a bit value “111”, a memory cell storing a bit value “110”, and a memory cell storing a bit value “100”. The memory cell storing the bit value “101” is determined to have a threshold voltage less than Vr4, and the read result of the bit value of the Upper page is “1”. Memory cell storing bit value "001", memory cell storing bit value "011", memory cell storing bit value "010", and memory storing bit value "000" The cell is determined to have a threshold voltage of Vr4 or higher, and the read result of the bit value of the Upper page becomes “0”.

As described above, the bit value of the Upper page can be correctly read by applying Vr4 as the read voltage regardless of which page is written. As described above, since the bit value of each page can be correctly read regardless of which page is being written, in this embodiment, information about which page is being written can be obtained. No need to manage.

FIG. 9 is a flowchart showing an example of the writing procedure of this embodiment. FIG. 9 shows an example of the procedure from the unwritten state to the writing of the Upper page for one memory cell group. First, in the unwritten state, the control unit 22 determines whether the bit value to be written for each memory cell is "0" (step S1). In the case of the memory cell whose bit value to be written is “0” (Yes in step S1), the control unit 22 injects charges to change the threshold voltage from the distribution Er (first region) to the distribution A (second region). ) (Step S2). If the bit value to be written is not “0” (“1”) (No in step S1), the threshold voltage is not changed.

When the above steps S1 and S2 are performed on all the memory cells in the memory cell group, the writing of the Lower page is completed (step S3), and the writing of the other memory cell groups is performed (step S4). Note that the process may proceed to the next step S5 without writing to another memory cell group.

After writing the Lower page, the control unit 22 determines whether the bit value to be written is 0 for each memory cell when writing to this memory cell group (step S5). In the case of the memory cell whose write bit value is "0" (Yes in step S5), the control unit 22 determines whether or not the threshold voltage of the memory cell has the distribution Er (step S6). When the threshold voltage of the memory cell is the distribution Er (Yes in step S6), charges are injected to increase the threshold voltage from the distribution Er to the distribution C (fourth region) (step S7). When the threshold voltage of the memory cell is not distribution Er (No in step S6), charges are injected to increase the threshold voltage from distribution A to distribution B (third region) (step S8). When the bit value to be written is not "0" ("1") (No in step S5), the threshold voltage is not changed.

When the above steps S5 to S8 are carried out for all the memory cells of the memory cell group, the writing of the Middle page is finished (step S9), and the writing of the other memory cell groups is carried out (step S10). Note that the process may proceed to the next step S11 without writing to another memory cell group.

After writing the Middle page, the control unit 22 determines whether the bit value to be written is "0" for each memory cell when writing to this memory cell group (step S11). When the bit value to be written is “0” (Yes in step S11), the control unit 22 injects charges into the memory cell to raise the threshold voltage (step S12). Specifically, memory cells of distribution Er are in distribution E (sixth region), memory cells of distribution A are in distribution F (seventh region), and memory cells of distribution B are in distribution G (eighth region). ), the memory cells of distribution C are moved to distribution D (fifth region). If the bit value to be written is not "0" in the memory cell (No in step S11), the process ends. With the above processing, writing to the Upper page is completed.

FIG. 10 is a flowchart showing an example of the reading procedure of the present embodiment. As described above, in the present embodiment, reading can be performed regardless of which page of Upper, Middle, and Lower has been written. First, the control unit 22 selects which of Upper, Middle, and Lower pages is to be read (step S21). When the Upper page is selected (Step S21 Upper), reading is performed with Vr4 (Step S22). The control unit 22 determines data (bit value of each memory cell) based on the read result at Vr4 (step S23), and ends the process.

When the Middle page is selected (step S21 Middle), reading is performed with Vr2 (step S24). Next, the control unit 22 performs reading with Vr5 (step S25). Next, the control unit 22 performs reading with Vr7 (step S26). Data is determined based on the read results of Vr2, Vr5, and Vr7 (step S27), and the process ends.

When the Lower page is selected (step S21 Lower), reading is performed with Vr1 (step S28). Next, the control unit 22 performs reading with Vr3 (step S29). Next, the control unit 22 performs reading with Vr6 (step S30). Data is determined based on the read results of Vr1, Vr3, and Vr6 (step S31), and the process ends.

As described above, in the present embodiment, the writing for each page is performed by using the 1-3-3 coding shown in FIG. Therefore, the number of boundaries between pages is less biased, the error occurrence probability can be smoothed between pages, the cost and power consumption of the storage device can be suppressed, and the writing and reading speeds can be increased. Further, regardless of which page has been written, the Upper page, the Middle page, and the Lower page can be read in the same procedure, so there is no need to manage information about which page has been written.

(Second embodiment)
FIG. 11 is a diagram showing data coding according to the second embodiment. The configuration of the storage device and the configuration of the non-volatile memory 2 of this embodiment are the same as those of the first embodiment. Hereinafter, the points different from the first embodiment will be described.

11A shows data coding in writing the Lower page, FIG. 11B shows data coding in writing the Middle page, and FIG. 11C shows data coding in writing the Upper page. .. As shown in FIG. 11, the same data coding (upper part of FIG. 11) is used for writing the Upper page and the Middle page, but different data coding is used for writing the Lower page (Fig. 11). (Lower part of 11) is used.

As described above, in the present embodiment, although the data coding differs depending on the page, if the information about which page has been written is managed, writing can be performed page by page in order. The number of boundaries for each page in the present embodiment is 1-3-3 as in the first embodiment, and the probability of error occurrence between pages can be smoothed.

In the present embodiment, the control unit 22 manages, as a write page flag (write page information), information indicating to which page the upper page, the middle page and the lower page are written for each memory cell group. ..

Comparing the data coding in the upper part of FIG. 11 with the data coding in the lower part of FIG. 11, the bit value corresponding to distribution B on the Middle page of the lower data coding is changed. The data coding in the lower part of FIG. 11 is the data coding in writing the Lower page, and at this time, the Middle page and the Upper page are not written. The distribution hatched as the nonexistent threshold distribution in the lower part of FIG. 11 indicates a threshold distribution that is not used for writing the Lower page. In the first embodiment, the threshold distribution which is not used for writing the Lower page is a continuous region of distribution B or more. On the other hand, in the present embodiment, in addition to the continuous region of distribution C and above, there is a distribution A that is not used between the distribution Er and the distribution B that are used for writing the Lower page. As a result, when reading an unwritten Middle page after writing the Lower page, it is necessary to perform reading with data allocation different from the data allocation after the Middle page is written.

FIG. 12 is a diagram showing the threshold distribution after programming of the memory cell in the present embodiment. 12A shows the threshold distribution after programming of the Lower page, FIG. 12B shows the threshold distribution after programming of the Middle page, and FIG. 12C shows that of the Upper page. The threshold distribution after programming is shown. In this embodiment, it is possible to program one page at a time, but the order of programming is fixed, and the lower page, the middle page, and the upper page are written in that order.

As shown in FIG. 12A, the control unit 22 of the nonvolatile memory 2 keeps the distribution Er in each memory cell or keeps the charge in the Lower page program according to the bit value to be written in the Lower page. Inject and move to distribution B one above. Specifically, when the bit value written to the Lower page is “1”, no charge is injected, and when the bit value written to the Lower page is “0”, the charge is injected to distribute the threshold voltage. Program to move to B.

When writing to the memory cell group that has already been written to the Lower page, the control unit 22 executes the program for the Middle page, as shown in FIG. Specifically, for the memory cells that were in the distribution Er state due to the programming of the Lower page, if the bit value written to the Middle page is “1”, the distribution Er remains unchanged and the bit value written to the Middle page remains unchanged. If it is “0”, the program is moved to the distribution A. For the memory cells that were in the distribution B state due to the programming of the Lower page, if the bit value written to the Middle page is “0”, the distribution B remains as it is and the bit value written to the Middle page is “1”. If, then program to move to distribution C. In the first embodiment, when the bit value to be written is "1", the charge is not injected, and when the bit value is "0", the charge is injected to move the threshold distribution. In the embodiment, in the writing of the Middle page, there is a case where the charge is not injected when the bit value to be written is “0” and the charge is injected when the bit value is “1”.

When writing to the memory cell group for which writing of the Middle page has been performed, the control unit 22 performs programming of the Upper page, as shown in FIG. Specifically, for the memory cells that have been in the distribution Er state by programming the Middle page, if the bit value to be written in the Upper page is “1”, the distribution Er is left unchanged, and the bit value to be written in the Upper page is In the case of "0", the program is moved to the distribution E. For the memory cells that were in the distribution A state due to the programming of the Middle page, if the bit value written to the Upper page is “1”, the distribution A remains as it is, and the bit value written to the Upper page is “0”. If, then program to move to distribution F. For the memory cells that were in the distribution B state due to the programming of the Middle page, if the bit value written to the Upper page is “1”, the distribution B remains as it is and the bit value written to the Upper page is “0”. If, then program to move to distribution G. For the memory cells that were in the distribution C state due to the programming of the Middle page, if the bit value written to the Upper page is “1”, the distribution C remains as it is and the bit value written to the Upper page is “0”. If, then program to move to distribution D.

Next, reading according to this embodiment will be described. FIG. 13 is a diagram showing a method of reading a Lower page according to the present embodiment. In this embodiment, the bit value of the Lower page can be read by applying three voltages Vr2, Vr5, and Vr7 as the read voltages regardless of which page is being written.

FIG. 14 is a diagram showing a method of reading the Middle page according to the present embodiment. In the present embodiment, when reading the Middle page, three of Vr1, Vr3, and Vr6 are applied as the read voltage. However, the data coding used for reading differs depending on whether or not the writing of the Middle page is completed. Therefore, the control unit 22 refers to the page write flag and, in the case where the lower page is written, as shown in FIG. 14A, according to the data coding of FIG. When the value voltage is Vr3 or more, the bit value is determined as "0", and when the threshold voltage is less than Vr3, the bit value is determined as "1". When writing is performed up to the Middle page and the Upper page, as shown in FIG. 12(B) or FIG. 12(C), according to the data coding of FIG. 11(B), (C), Vr1, Vr3 , Vr6 are read out to determine the bit value.

FIG. 15 is a diagram showing a method of reading the Upper page according to the present embodiment. In the present embodiment, the bit value of the Upper page can be read by applying Vr4 as the read voltage regardless of which page is being written.

In the writing procedure of this embodiment, as shown in FIG. 12, the threshold distribution is moved according to the bit value to be written. The specific procedure is the same as that of the first embodiment except that the data coding is different.

FIG. 16 is a flowchart showing an example of the reading procedure of this embodiment. FIG. 16 shows an example of the procedure from the unwritten state to the writing of the Upper page for one memory cell group. First, the control unit 22 reads the write page flag of the memory cell group to be read (step S41). Steps S42 and S43 are the same as steps S21 and S22 of the first embodiment. After step S43, the control unit 22 determines data based on the write page flag and the read result at Vr4 (step S44).

When the Middle page is selected in step S42 (step S42 Middle), the control unit 22 performs reading with Vr1 (step S45). Next, the control unit 22 performs reading with Vr3 (step S46). Next, the control unit 22 performs reading with Vr6 (step S47). Next, the control unit 22 determines the data based on the write page flag and the read result of Vr1, Vr3, and Vr6 (step S48), and ends the process. Specifically, when the write page flag has a value indicating the state in which the Lower page is written, according to the data coding of FIG. 11A, if the threshold voltage is Vr3 or more, the bit value is changed. If the threshold voltage is less than Vr3, the bit value is determined to be "1". When the write page flag has a value indicating a state in which the Upper page or the Middle page has been written, the bits are read based on the read results of Vr1, Vr3, and Vr6 according to the data coding of FIGS. 11B and 11C. Determine the value.

When the Lower page is selected (step S21 Lower), the control unit 22 performs reading with Vr2 (step S49). Next, the control unit 22 performs reading with Vr5 (step S50). Next, the control unit 22 performs reading with Vr7 (step S51). Next, the control unit 22 determines the data based on the write page flag and the read result at Vr2, Vr5, and Vr7 (step S52), and ends the process.

As described above, the same data coding can be used for reading the Lower page and the Upper page regardless of the write page flag. Therefore, in steps S48 and S52, it is not necessary to consider the write page flag.

In the present embodiment, as described above, in order to determine the extent of the programmed pages, the information is held as a write page flag at the time of page programming. The write page flag may be held in, for example, a memory cell different from the memory cell storing the user data in the memory group storing the user data in the NAND memory cell array 23. Alternatively, the NAND memory cell array 23 may be stored in a memory cell group different from the memory group for storing user data, or may be held in a storage area of a memory in the nonvolatile memory 2 or the memory controller 1. As described above, there is no limitation on the method of managing the write page flag. Further, the timing of reading the write page flag may not be the timing shown in FIG. 16 as long as the data is determined, and may be the same timing as the data reading, for example. Especially, when the write page flag is held in the memory cell group in which the user data is stored, this read timing is appropriate.

As described above, in the present embodiment, the 1-3-3 coding shown in FIG. 11 is used to manage which page has been written by using the write page flag. Writing was carried out. Therefore, the number of boundaries between pages is less biased, the error occurrence probability can be smoothed between pages, the cost and power consumption of the storage device can be suppressed, and the writing and reading speeds can be increased.

(Third Embodiment)
FIG. 17 is a diagram showing data coding according to the third embodiment. The configuration of the storage device and the configuration of the non-volatile memory 2 of this embodiment are the same as those of the first embodiment. Hereinafter, the points different from the first embodiment will be described.

17A shows data coding in writing the Lower page, FIG. 17B shows data coding in writing the Middle page, and FIG. 17C shows data coding in writing the Upper page. ..

The threshold value distribution (area) surrounded by a square in FIG. 17 shows the threshold value distribution in which the allocation of data values is changed depending on how much writing is performed. The hatched portion shows the threshold distribution which is not used for writing the corresponding page. Also in the present embodiment, as in the second embodiment, the write page flag is used to manage up to which page has been written.

FIG. 18 is a diagram showing the threshold distribution after programming of the memory cell in the present embodiment. 18A shows the threshold distribution after programming of the Lower page, FIG. 18B shows the threshold distribution after programming of the Middle page, and FIG. 18C shows that of the Upper page. The threshold distribution after programming is shown. In this embodiment, it is possible to program one page at a time, but the order of programming is fixed, and the lower page, the middle page, and the upper page are written in that order.

As shown in FIG. 18A, the control unit 22 of the nonvolatile memory 2 does not inject charges when the bit value written in the Lower page is “1” and the bit value written in the Lower page is “0”. In the case of, the charge is injected and the threshold voltage is programmed to move to the distribution D.

When writing to the memory cell group that has already been written to the Lower page, the control unit 22 controls the memory cells in the distribution Er state by programming the Lower page as shown in FIG. 18B. , If the bit value to be written in the Middle page is “1”, the distribution Er is left unchanged, and if the bit value to be written in the Middle page is “0”, the distribution B is programmed. For the memory cells that were in the distribution D state due to the programming of the Lower page, if the bit value written to the Middle page is “0”, the distribution D remains as it is and the bit value written to the Middle page is “1”. If, then program to move to distribution E.

When writing to the memory cell group in which the Middle page has been written, the control unit 22 writes the memory cells in the state of distribution Er by the program of the Middle page, as shown in FIG. 18C. , If the bit value to be written in the Upper page is “1”, the distribution Er is left unchanged, and if the bit value to be written in the Upper page is “0”, the program is moved to the distribution A. For the memory cells that have been in the distribution B state due to the programming of the Middle page, if the bit value written to the Upper page is “0”, the distribution B remains as it is and the bit value written to the Upper page is “1”. If, then program to move to distribution C. For the memory cells that were in the distribution D state due to the programming of the Middle page, if the bit value written to the Upper page is “1”, the distribution D remains unchanged and the bit value written to the Upper page is “0”. If, then program to move to distribution G. For the memory cells that have been in the distribution E state due to the programming of the Middle page, if the bit value written to the Upper page is “1”, the distribution E remains as it is and the bit value written to the Upper page is “0”. If, then program to move to distribution F.

In the first embodiment, when the bit value to be written is "1", the charge is not injected, and when the bit value is "0", the charge is injected to move the threshold distribution. In the embodiment, in the writing of the Middle page and the Upper page, there is a case where the charge is not injected when the bit value to be written is “0” and the charge is injected when the bit value is “1”. Therefore, in the data coding of FIG. 17, there is one distribution in which the allocation of data values is changed depending on the written page, one in the Middle page and one in the Upper page.

In the writing procedure of the present embodiment, as shown in FIG. 18, the threshold distribution is moved according to the bit value to be written. The specific procedure is the same as that of the first embodiment except that the data coding is different.

The read procedure of this embodiment is similar to that of the second embodiment except that the data coding is different, and the data value is determined using the write page flag and the read result at the read voltage at the boundary of each page. To do. Specifically, in the present embodiment, Vr1, Vr3, and Vr6 are used for reading the Upper page, Vr2, Vr5, Vr7 are used for reading the Middle page, and Vr4 is used for reading the Lower page. When writing is performed up to the Upper page, the bit value is determined according to the data coding in FIG. When writing is performed up to the Middle page, the bit value is determined according to the data coding in FIG. When writing is performed up to the Middle page, the data values for the Lower page and Middle page are determined in the same way as when writing is performed up to the Upper page, but the threshold is used when reading the Upper page. When it is determined that the value voltage is Vr1 or more and less than Vr3, the bit value is determined to be “1”. When writing is performed up to the Lower page, the bit value is determined according to the data coding in FIG. When data is written up to the Lower page, the method of determining the data values of the Lower page and Upper page is the same as when writing is written up to the Upper page, but the threshold is set when reading the Middle page. When it is determined that the value voltage is Vr2 or more and less than Vr5, the bit value is determined to be "1".

As described above, in the present embodiment, by using the 3-3-1 coding shown in FIG. 17 and managing up to which page has been written using the write page flag, it is possible to Writing was carried out. Therefore, the number of boundaries between pages is less biased, the error occurrence probability can be smoothed between pages, the cost and power consumption of the storage device can be suppressed, and the writing and reading speeds can be increased.

(Fourth Embodiment)
FIG. 19 is a diagram showing data coding according to the fourth embodiment. The configuration of the storage device and the configuration of the non-volatile memory 2 of this embodiment are the same as those of the first embodiment. Hereinafter, the points different from the first embodiment will be described.

FIG. 19(A) shows data coding in writing the Lower page, FIG. 19(B) shows data coding in writing the Middle page, and FIG. 19(C) shows data coding in writing the Upper page. ..

The threshold distribution (area) surrounded by a square in FIG. 19 shows the threshold distribution in which the allocation of data values is changed depending on how much writing has been performed. The hatched portion shows the threshold distribution which is not used for writing the corresponding page. Also in the present embodiment, as in the second embodiment, the write page flag is used to manage up to which page has been written.

FIG. 20 is a diagram showing the threshold distribution after programming of the memory cell in the present embodiment. 20A shows the threshold distribution after programming of the Lower page, FIG. 20B shows the threshold distribution after programming of the Middle page, and FIG. 20C shows that of the Upper page. The threshold distribution after programming is shown. In this embodiment, it is possible to program one page at a time, but the order of programming is fixed, and the lower page, the middle page, and the upper page are written in that order.

As shown in FIG. 20A, when the bit value written in the Lower page is “1”, the control unit 22 of the nonvolatile memory 2 does not inject charges and the bit value written in the Lower page is “0”. In the case of, the charge is injected and the threshold voltage is programmed to move to the distribution D.

When writing to the memory cell group that has already been written to the Lower page, the control unit 22 controls the memory cells in the distribution Er state by the programming of the Lower page as shown in FIG. , If the bit value to be written in the Middle page is “1”, the distribution Er is left unchanged, and if the bit value to be written in the Middle page is “0”, the program is moved to the distribution A. For the memory cells that were in the distribution D state due to the programming of the Lower page, if the bit value written to the Middle page is “1”, the distribution D remains as it is and the bit value written to the Middle page is “0”. If, then program to move to distribution F.

When writing is performed to the memory cell group in which the Middle page has been written, the control unit 22 writes the memory cells in the distribution Er state by the program of the Middle page, as shown in FIG. , If the bit value to be written in the Upper page is "1", the distribution Er is left unchanged, and if the bit value to be written in the Upper page is "0", the distribution C is moved. For the memory cells that were in the distribution A state due to the programming of the Middle page, if the bit value written to the Upper page is “1”, the distribution A remains as it is, and the bit value written to the Upper page is “0”. If, then program to move to distribution B. For the memory cells that were in the distribution D state due to the programming of the Middle page, if the bit value written to the Upper page is “0”, the distribution D remains as it is and the bit value written to the Upper page is “1”. If, then program to move to distribution E. For the memory cells that were in the distribution F state due to the programming of the Middle page, if the bit value written to the Upper page is “1”, the distribution F is left unchanged and the bit value written to the Upper page is “0”. If, then program to move to distribution G.

In the first embodiment, when the bit value to be written is "1", the charge is not injected, and when the bit value is "0", the charge is injected to move the threshold distribution. In the embodiment, in the writing of the Upper page, there is a case where the charges are not injected when the bit value to be written is “0” and the charges are injected when the bit value is “1”. Therefore, in the data coding of FIG. 19, there is one distribution in which the allocation of data values is changed depending on the written page in the Upper page.

In the writing procedure of this embodiment, as shown in FIG. 20, the threshold distribution is moved according to the bit value to be written. The specific procedure is the same as that of the first embodiment except that the data coding is different.

The read procedure of this embodiment is similar to that of the second embodiment except that the data coding is different, and the data value is determined using the write page flag and the read result at the read voltage at the boundary of each page. To do. Specifically, in the present embodiment, Vr2, Vr5, and Vr7 are used for reading the Upper page, Vr1, Vr3, Vr6 are used for reading the Middle page, and Vr4 is used for reading the Lower page. When writing is performed up to the Upper page, the bit value is determined according to the data coding in FIG. When writing is performed up to the Middle page, the bit value is determined according to the data coding in FIG. When writing is performed up to the Middle page, the data values for the Lower page and Middle page are determined in the same way as when writing is performed up to the Upper page, but the threshold is used when reading the Upper page. When it is determined that the value voltage is Vr2 or more and less than Vr5, the bit value is determined to be "1". When writing is performed up to the Lower page, the bit value is determined according to the data coding in FIG. When writing is done up to the Lower page, the data values for the Lower page and Middle page are determined in the same way as when writing is done up to the Upper page, but when reading the Upper page, the threshold is set. When it is determined that the value voltage is Vr2 or more and less than Vr5, the bit value is determined to be "1".

As described above, in the present embodiment, by using the 3-3-1 coding shown in FIG. 19 and managing up to which page has been written using the write page flag, it is possible to Writing was carried out. Therefore, the number of boundaries between pages is less biased, the error occurrence probability can be smoothed between pages, the cost and power consumption of the storage device can be suppressed, and the writing and reading speeds can be increased.

(Fifth Embodiment)
FIG. 21 is a diagram showing data coding according to the fifth embodiment. The configuration of the storage device and the configuration of the non-volatile memory 2 of this embodiment are the same as those of the first embodiment. Hereinafter, the points different from the first embodiment will be described.

21A shows data coding in writing the Lower page, FIG. 21B shows data coding in writing the Middle page, and FIG. 21C shows data coding in writing the Upper page. ..

The threshold distribution (area) surrounded by a square in FIG. 21 shows the threshold distribution in which the allocation of data values is changed depending on how much writing has been performed. The hatched portion shows the threshold distribution which is not used for writing the corresponding page. Also in the present embodiment, as in the second embodiment, the write page flag is used to manage up to which page has been written.

FIG. 22 is a diagram showing the threshold distribution after programming of the memory cell in the present embodiment. 22A shows the threshold distribution after programming of the Lower page, FIG. 22B shows the threshold distribution after programming of the Middle page, and FIG. 22C shows that of the Upper page. The threshold distribution after programming is shown. In this embodiment, it is possible to program one page at a time, but the order of programming is fixed, and the lower page, the middle page, and the upper page are written in that order.

As shown in FIG. 22A, the control unit 22 of the nonvolatile memory 2 does not inject charges when the bit value written to the Lower page is “1” and the bit value written to the Lower page is “0”. In the case of 2, the charge is injected and the threshold voltage is programmed to move to the distribution B.

When writing to the memory cell group that has already been written to the Lower page, the control unit 22 controls the memory cells that have been in the distribution Er state by programming the Lower page, as shown in FIG. , If the bit value to be written in the Middle page is “1”, the distribution Er is left unchanged, and if the bit value to be written in the Middle page is “0”, the program is moved to the distribution E. For the memory cells that were in the distribution B state due to the programming of the Lower page, if the bit value written to the Middle page is “1”, the distribution B remains as it is and the bit value written to the Middle page is “0”. If, then program to move to distribution D.

When writing to the memory cell group in which the Middle page has been written, the control unit 22 writes the memory cells that have been in the distribution Er state by programming the Middle page, as shown in FIG. , If the bit value to be written in the Upper page is “1”, the distribution Er is left unchanged, and if the bit value to be written in the Upper page is “0”, the program is moved to the distribution A. For the memory cells that have been in the distribution B state due to the programming of the Middle page, if the bit value written to the Upper page is “0”, the distribution B remains as it is and the bit value written to the Upper page is “1”. If, then program to move to distribution C. For the memory cells that were in the distribution D state due to the programming of the Middle page, if the bit value written to the Upper page is “1”, the distribution D remains unchanged and the bit value written to the Upper page is “0”. If, then program to move to distribution G. For the memory cells that have been in the distribution E state due to the programming of the Middle page, if the bit value written to the Upper page is “1”, the distribution E remains as it is and the bit value written to the Upper page is “0”. If, then program to move to distribution F.

In the first embodiment, when the bit value to be written is "1", the charge is not injected, and when the bit value is "0", the charge is injected to move the threshold distribution. In the embodiment, in the writing of the Upper page, there is a case where the charges are not injected when the bit value to be written is “0” and the charges are injected when the bit value is “1”. Therefore, in the data coding of FIG. 21, there is one distribution in the Upper page in which the allocation of data values is changed depending on the written page.

In the writing procedure of this embodiment, as shown in FIG. 22, the threshold distribution is moved according to the bit value to be written. The specific procedure is the same as that of the first embodiment except that the data coding is different.

The read procedure of this embodiment is similar to that of the second embodiment except that the data coding is different, and the data value is determined using the write page flag and the read result at the read voltage at the boundary of each page. To do. Specifically, in the present embodiment, Vr1, Vr3, and Vr6 are used for reading the Upper page, Vr4 is used for reading the Middle page, and Vr2, Vr5, Vr7 are used for reading the Lower page. When writing is performed up to the Upper page, the bit value is determined according to the data coding in FIG. When writing is performed up to the Middle page, the bit value is determined according to the data coding in FIG. When writing is performed up to the Middle page, the data values for the Lower page and Middle page are determined in the same way as when writing is performed up to the Upper page, but the threshold is used when reading the Upper page. When it is determined that the value voltage is Vr1 or more and less than Vr3, the bit value is determined to be “1”. When writing is performed up to the Lower page, the bit value is determined according to the data coding in FIG. When writing is done up to the Lower page, the data values for the Lower page and Middle page are determined in the same way as when writing is done up to the Upper page, but when reading the Upper page, the threshold is set. When it is determined that the value voltage is Vr1 or more and less than Vr3, the bit value is determined to be “1”.

As described above, in the present embodiment, by using the 3-1-3 coding shown in FIG. 21 and managing up to which page has been written using the write page flag, each page is written. Writing was carried out. Therefore, the number of boundaries between pages is less biased, the error occurrence probability can be smoothed between pages, the cost and power consumption of the storage device can be suppressed, and the writing and reading speeds can be increased.

(Sixth Embodiment)
FIG. 23 is a diagram showing data coding according to the sixth embodiment. The configuration of the storage device and the configuration of the non-volatile memory 2 of this embodiment are the same as those of the first embodiment. Hereinafter, the points different from the first embodiment will be described.

23A shows the data coding in writing the Lower page, FIG. 23B shows the data coding in writing the Middle page, and FIG. 23C shows the data coding in writing the Upper page. ..

The threshold value distribution (area) surrounded by a square in FIG. 23 shows the threshold value distribution in which the allocation of data values is changed depending on how much writing is performed. The hatched portion shows the threshold distribution which is not used for writing the corresponding page. Also in the present embodiment, as in the second embodiment, the write page flag is used to manage up to which page has been written.

FIG. 24 is a diagram showing the threshold distribution after programming of the memory cell according to the present embodiment. 24A shows the threshold distribution after programming of the Lower page, FIG. 24B shows the threshold distribution after programming of the Middle page, and FIG. 24C shows that of the Upper page. The threshold distribution after programming is shown. In this embodiment, it is possible to program one page at a time, but the order of programming is fixed, and the lower page, the middle page, and the upper page are written in that order.

As shown in FIG. 24A, the control unit 22 of the non-volatile memory 2 does not inject charges when the bit value to be written in the Lower page is “1” and the bit value to be written in the Lower page is “0”. In the case of 2, the charge is injected and the threshold voltage is programmed to move to the distribution A.

When writing to the memory cell group that has already been written to the Lower page, the control unit 22 controls the memory cells in the distribution Er state by programming the Lower page as shown in FIG. 24B. , If the bit value to be written in the Middle page is “1”, the distribution Er is left unchanged, and if the bit value to be written in the Middle page is “0”, the program is moved to the distribution D. For the memory cells that were in the distribution A state due to the programming of the Lower page, if the bit value written to the Middle page is “1”, the distribution A remains as it is, and the bit value written to the Middle page is “0”. If, then program to move to distribution F.

When writing to the memory cell group in which the Middle page has been written, the control unit 22 writes the memory cells that have been in the distribution Er state by programming the Middle page, as shown in FIG. , If the bit value to be written in the Upper page is "1", the distribution Er is left unchanged, and if the bit value to be written in the Upper page is "0", the distribution C is moved. For the memory cells that were in the distribution A state due to the programming of the Middle page, if the bit value written to the Upper page is “1”, the distribution A remains as it is, and the bit value written to the Upper page is “0”. If, then program to move to distribution B. For the memory cells that were in the distribution D state due to the programming of the Middle page, if the bit value written to the Upper page is “0”, the distribution D remains as it is and the bit value written to the Upper page is “1”. If, then program to move to distribution E. For the memory cells that were in the distribution F state due to the programming of the Middle page, if the bit value written to the Upper page is “1”, the distribution F is left unchanged and the bit value written to the Upper page is “0”. If, then program to move to distribution G.

In the first embodiment, when the bit value to be written is "1", the charge is not injected, and when the bit value is "0", the charge is injected to move the threshold distribution. In the embodiment, in the writing of the Upper page, there is a case where the charges are not injected when the bit value to be written is “0” and the charges are injected when the bit value is “1”. Therefore, in the data coding of FIG. 23, there is one distribution in which the allocation of data values is changed depending on the written page in the Upper page.

In the writing procedure of this embodiment, as shown in FIG. 24, the threshold distribution is moved according to the bit value to be written. The specific procedure is the same as that of the first embodiment except that the data coding is different.

The read procedure of this embodiment is similar to that of the second embodiment except that the data coding is different, and the data value is determined using the write page flag and the read result at the read voltage at the boundary of each page. To do. Specifically, in the present embodiment, Vr2, Vr5, and Vr7 are used for reading the Upper page, Vr4 is used for reading the Middle page, and Vr1, Vr3, and Vr6 are used for reading the Lower page. If writing has been performed up to the Upper page, the bit value is determined according to the data coding in FIG. When writing is performed up to the Middle page, the bit value is determined according to the data coding in FIG. When writing is performed up to the Middle page, the data values for the Lower page and Middle page are determined in the same way as when writing is performed up to the Upper page, but the threshold is used when reading the Upper page. When it is determined that the value voltage is Vr2 or more and less than Vr5, the bit value is determined to be "1". When writing is performed up to the Lower page, the bit value is determined according to the data coding in FIG. When writing is done up to the Lower page, the data values for the Lower page and Middle page are determined in the same way as when writing is done up to the Upper page, but when reading the Upper page, the threshold is set. When it is determined that the value voltage is Vr2 or more and less than Vr5, the bit value is determined to be "1".

As described above, in the present embodiment, by using the 3-1-3 coding shown in FIG. 23 and managing up to which page has been written using the write page flag, it is possible to Writing was carried out. Therefore, the number of boundaries between pages is less biased, the error occurrence probability can be smoothed between pages, the cost and power consumption of the storage device can be suppressed, and the writing and reading speeds can be increased.

(Seventh embodiment)
Next, a reading method in the storage device according to the seventh embodiment will be described. The configuration of the storage device and the configuration of the non-volatile memory 2 of this embodiment are the same as those of the first embodiment. The data coding of this embodiment is the same as that of the first embodiment. Hereinafter, the points different from the first embodiment will be described.

Generally, the threshold value of each memory cell of a NAND memory fluctuates (changes) due to some factor. There are various factors such as program disturb, read disturb, and data retention. A memory cell having a changed threshold value is determined to be in a state corresponding to a threshold value distribution (region) different from the threshold value distribution (region) corresponding to the written data value at the time of reading. May occur, resulting in an error in read data. As a measure against this problem, there is a method of correcting the threshold value fluctuation and reading the data.

FIG. 25 is a diagram showing an example of variations in the threshold distribution. FIG. 25 shows an example of the threshold fluctuation when the Lower page is read after the programming is performed in the state of FIG. 6C of the first embodiment. The threshold distribution 100 shown by the solid line shows the threshold distribution before change, that is, at the time of writing. The threshold value distribution 101 shown by the dotted line shows the threshold value distribution after fluctuation. Although the reference numerals are assigned to the respective ones, the solid lines also show the pre-variation threshold values and the dotted lines show the post-variation threshold value distributions without reference numerals. In the example of FIG. 25, due to the data retention, the distribution Er and the distribution A are in the positive direction (the direction toward the right in FIG. 25), and the distributions BG are in the negative direction (the direction toward the left in FIG. 25). It shows how the threshold value fluctuates. When the memory cells after the threshold value change are read using the original read voltages Vr1, Vr3, and Vr6, for example, a part of the memory cells belonging to the distribution F (a part on the low voltage side) is between Vr3 and Vr6. It is determined to be within the range. As described above, the threshold value variation causes the data in many memory cells to be erroneously read.

Therefore, in the present embodiment, instead of Vr1, Vr3, and Vr6, a read voltage in which variations such as Vr1', Vr3', and Vr6' are corrected is used. Any method may be used to determine Vr1′, Vr3′, and Vr6′. For example, the read voltage is changed to perform error correction processing, and the read voltages that can be corrected are Vr1′ and Vr3. A method of using as “, Vr6” can be considered. The method for determining Vr1', Vr3', Vr6' is not limited to this method.

FIG. 26 is a flowchart showing an example of the read procedure of the present embodiment when the read voltage is changed. The reading may be always performed in the procedure shown in FIG. 26, or the reading of the reading voltage is not changed normally and the reading of FIG. You may make it implement a procedure. Although there is no particular restriction on this constant condition, for example, when the ratio at which error correction becomes impossible due to the error correction processing at the time of reading exceeds a certain ratio, the reading is performed by changing the read voltage shown in FIG. As shown in FIG. 26, the processor 12 inputs a page read command (command for requesting reading in page units) to the nonvolatile memory 2 via the memory interface 15 (step S61). The nonvolatile memory 2 reads data according to the page read command (step S62), and transmits the read data to the ECC circuit 14 via the memory interface 15 (step S63). The read voltage used for reading in step S62 is an initial value (Vr1, Vr3, Vr6 in the example of FIG. 25) when the read level change command described later has not been received. However, this initial value may be changeable based on an instruction from the memory controller 1.

The ECC circuit 14 performs error correction processing using the input data (step S64). The ECC circuit 14 notifies the processor 12 whether or not error correction was possible in this error correction processing. Based on this notification, the processor 12 determines whether or not the error correction is possible (step S65), and when the error correction is possible (step S65 Yes), the process ends. If the error cannot be corrected (No in step S65), the processor 12 determines the read level (read voltage) of the nonvolatile memory 2 to be a value different from the read voltage used in step S62 (step S67). Then, the processor 12 inputs the read level change command to the nonvolatile memory 2 via the memory interface 15 based on the determined value (step S66), and returns to step S61. The nonvolatile memory 2 changes the read voltage according to the read level change command.

With the above procedure, it is possible to search for a read voltage that enables error correction. The read voltages when error correction is possible correspond to Vr1', Vr3', and Vr6' in FIG.

In the above description, an example in which the data coding of the first embodiment is used has been described. However, when the data coding of the second to sixth embodiments is used, the read voltage may be similarly changed. ..

In the present embodiment, the read voltage is changed when the threshold value fluctuates when writing and reading are performed using the data coding of the first to sixth embodiments. For this reason, the effects of the first to sixth embodiments can be obtained, and data read errors can be reduced even when the threshold value changes.

(Eighth Embodiment)
Next, a reading method in the memory device according to the eighth embodiment will be described. The configuration of the storage device and the configuration of the non-volatile memory 2 of this embodiment are the same as those of the first embodiment. The data coding of this embodiment is the same as that of the first embodiment. Hereinafter, the points different from the first embodiment will be described.

Any error correction code may be used when performing error correction coding to protect the data stored in the non-volatile memory 2, but soft-decision decoding may be performed at the time of decoding. When performing soft-decision decoding, coding is generally performed using a code that performs soft-decision decoding, such as LDPC (Low Density Parity Check) code, but a code that can perform hard-decision decoding ( It is also possible to perform coding using a BCH code or the like) and perform soft decision decoding at the time of decoding.

In the present embodiment, an example of performing soft decision decoding at the time of decoding will be described. The encoding method is not particularly limited, but as described above, for example, the LDPC code is used for encoding. When performing soft-decision decoding, so-called soft bit information is read from the nonvolatile memory 2 in addition to the hard decision value similar to normal reading, and decoding is performed using the read hard decision value and soft bit information. The soft bit information is probability information about how close the true value is. When a NAND memory is used as the non-volatile memory 2, it can be considered that the closer the threshold voltage of each memory cell is to the threshold voltage of the memory cell, the closer to the true value.

Hereinafter, the reading method for reading the soft bit information is called a soft bit read, and the normal read is called a hard bit read (HB read) on the premise of the first embodiment and the like. The hard bit read determines whether or not the threshold voltage of the memory cell is higher than the boundary by applying one read voltage corresponding to the boundary dividing the threshold distribution. On the other hand, in soft bit read, reading is performed with a plurality of read voltages for one boundary to be determined. Although the hardware configuration for performing the soft bit read may be any configuration, for example, the nonvolatile memory 2 can support both read methods of the soft bit read and the normal read (hard bit read), and the memory controller It is assumed that reading is performed based on the instruction from 1. Further, the amount of shift of the read voltage and the number of types of shift when performing the soft bit read may be set in advance in the non-volatile memory 2 or may be instructed from the memory controller 1. Good.

FIG. 27 is a diagram showing an example of a state of soft bits. FIG. 27 shows a state in which the Lower page is read by soft bit reading after programming is performed in the state of FIG. 6C of the first embodiment. In the example of this figure, two types of soft bit information are read. The soft bit read is basically a read using the data read value when the read voltage is shifted from the hard bit read (whether or not the threshold voltage of the memory cell is equal to or higher than the shifted read voltage). It is a combination with. In the example of FIG. 27, first, the nonvolatile memory 2 reads three hard bit read data (threshold voltage is read based on the read results of three times using the normal read voltages Vr1, Vr3, and Vr6). Whether the voltage is equal to or higher than the voltage) is determined (FIG. 27A). The data value is “0” when the threshold voltage is equal to or higher than the read voltage, and the data value is “1” when the threshold voltage is lower than the read voltage.

Next, the nonvolatile memory 2 performs the soft bit read #1 (S1 read) with the read voltage lower than the voltages Vr1, Vr3, Vr6 by the predetermined amount ΔR. Then, the data of S1 read is determined based on the results of reading three times using Vr1-ΔR, Vr3-ΔR, and Vr6-ΔR (FIG. 27(B)). Next, the non-volatile memory 2 performs soft bit read #2 (S2 read) with a read voltage higher than the voltages Vr1, Vr3, and Vr6 by ΔR. Then, the data of S2 read is determined based on the read result of three times using Vr1+ΔR, Vr3+ΔR, and Vr6+ΔR (FIG. 27(C)).

Next, the non-volatile memory 2 performs soft bit read #3 (S3 read) at a read voltage that is lower than the voltages Vr1, Vr3, and Vr6 by twice the ΔR. Then, the data of S3 read is determined based on the results of reading three times using the voltages Vr1-2ΔR, Vr3-2ΔR, and Vr6-2ΔR (FIG. 27D). Next, the nonvolatile memory 2 performs the soft bit read #4 (S4 read) with the read voltage higher than the voltages Vr1, Vr3, and Vr6 by twice the ΔR. Then, the data of S4 read is determined based on the results of reading three times using the voltages Vr1+2ΔR, Vr3+2ΔR, and Vr6+2ΔR (FIG. 27(E)).

Further, by calculating the exclusive-NOR of the data of S1 read and the data of S2 read, the range between Vr1-ΔR and Vr1+ΔR, the range between Vr3-ΔR and Vr3+ΔR, and the range between Vr6-ΔR and Vr6+ΔR It is possible to specify the memory cells having the threshold voltage in the range of (FIG. 27(F)). Similarly, by operating the exclusive-NOR of the data of S3 read and the data of S4 read, the range between Vr1-2ΔR and Vr1+2ΔR, the range between Vr3-2ΔR and Vr3+2ΔR, and the range of Vr6-2ΔR and Vr6+2ΔR. A memory cell having a threshold voltage in the range between the memory cells can be specified (FIG. 27G). The results of FIGS. 27F and 27G are two types of soft bit information.

Then, the ECC circuit 14 can perform error correction by performing soft-decision decoding using the hard bit read result and the soft bit information. In the present embodiment, an example in which the data coding of the first embodiment is used has been described. However, when the data coding of the second to sixth embodiments is used, soft bit read is similarly performed. Good. Further, when the soft bit read according to the present embodiment is performed, the read voltage described in the seventh embodiment may be changed.

(Ninth Embodiment)
Next, the threshold distribution in the memory device of the ninth embodiment will be described. The configuration of the storage device and the configuration of the non-volatile memory 2 of this embodiment are the same as those of the first embodiment. The data coding of this embodiment is the same as that of the first embodiment. Hereinafter, the points different from the first embodiment will be described.

In each of the first to sixth embodiments, the width of the threshold distribution (area) is the same as the width finally required for the program of the Upper page in the program of the Lower page and the Middle page. The example of forming the width has been described.

In the present embodiment, as a modification of the data coding described in the third embodiment, the width of the threshold distribution of the Lower page and the Middle page is widened, and the interval of the threshold distribution of the Middle page is widened. To do. This will speed up the writing of the Lower page and reduce the probability of data error in the Middle page.

FIG. 28 is a diagram showing an example of the threshold distribution after programming of each page in the present embodiment. The threshold value distribution corresponding to the data value “0” after the Lower page program of the present embodiment is the distribution corresponding to the data value “0” after the Lower page program shown in FIG. 18 of the third embodiment. Compared with 102, the width is wider and the center voltage is lower. As a result, the interval between the threshold value distribution corresponding to the data value “00” and the threshold value distribution corresponding to the data value “10” after programming the Middle page is also widened.

As described above, by increasing the width of the threshold distribution, the increase width of the program voltage applied to the word line at the time of programming the Lower page per program pulse is made larger than that of the Middle page or Upper page. be able to. That is, since the distribution width can be roughly adjusted, the program time can be shortened. In addition, since the threshold distribution of the Middle page is widened, the probability of data error is reduced, and more accurate data can be read. By utilizing this, it is also possible for the program to use only the Lower page as high-speed and reliable binary data.

As a result, in the third embodiment, the threshold distribution of the data value “100” in the Upper page program is the same as the threshold distribution of the data value “00” in the Middle page after programming. , When writing the Upper page, it was not necessary to execute the program when the data value was “100”. On the other hand, in the present embodiment, the program is executed so that the threshold value distribution of the data value “100” shown in FIG. 28C is obtained when the data value is “100” when writing the Upper page. To do.

Although the modification of the third embodiment has been described here, the width of at least a part of the threshold distribution after programming of the Lower page and the Middle page is widened similarly in the other embodiments. The interval of the threshold distribution of the Middle page can be widened.

As described above, in the present embodiment, the width of at least a part of the threshold distribution of the Lower page and the Middle page after programming is widened, and the interval of the threshold distribution of the Middle page is widened. As a result, the programming time can be shortened. In addition, it is possible to reduce errors in reading Middle pages.

(Tenth Embodiment)
Next, the threshold distribution in the storage device of the tenth embodiment will be described. The configuration of the storage device and the configuration of the non-volatile memory 2 of this embodiment are the same as those of the first embodiment. The data coding of this embodiment is the same as that of the first embodiment. Hereinafter, the points different from the first embodiment will be described.

In the present embodiment, as in the ninth embodiment, as a modified example of the data coding described in the third embodiment, the width of the threshold distribution of the Lower page and the Middle page is widened, and the Middle page is widened. Increase the page threshold distribution interval.

FIG. 29 is a diagram showing an example of the threshold distribution after programming of each page in the present embodiment. The threshold value distribution corresponding to the data value “0” after the Lower page program of the present embodiment is moved to the lower voltage side as compared with the ninth embodiment. In FIG. 29, distribution 102 shows the threshold distribution of the third embodiment. Note that in FIG. 29, the reference numeral is assigned to one distribution, but the threshold distribution shown by the dotted line shows the threshold distribution of the third embodiment similarly to the distribution assigned with the reference numeral. . The threshold distribution corresponding to the data value “01” and the threshold distribution corresponding to the data value “10” after programming the Middle page are respectively wider than those in the third embodiment. The center voltage is also decreasing.

As a result, the interval between the threshold value distribution of the data value “00” and the threshold value distribution of the data value “10” after the middle page programming is widened. Therefore, the increase width of the program voltage applied to the word line at the time of programming of the Lower page and the Middle page for each program pulse can be made larger than that of the Upper page. That is, since the distribution width can be roughly adjusted, the programming time can be shortened. Also, since the distribution interval of the Middle page is widened, the probability of data error is reduced, and more accurate data can be read. By utilizing this, it is also possible for the program to use only the Lower page as high-speed and reliable binary data.

In the third embodiment, regarding the threshold distribution of the data values “001”, “100”, and “110” in the program of the Upper page, the data values “01”, “00”, after the Middle page program, Since it was the same as the threshold distribution of "10", it was not necessary to execute the program. In this embodiment, the program is executed so that the threshold distribution of the data values "001", "100", "110" in the program of the Upper page becomes the threshold distribution shown in FIG. 29(C). To do.

Although the modification of the third embodiment has been described here, the width of at least a part of the threshold distribution after programming of the Lower page and the Middle page is widened similarly in the other embodiments. The interval of the threshold distribution of the Middle page can be widened.

As described above, in the present embodiment, the width of at least a part of the threshold distribution of the Lower page and the Middle page after programming is widened, and the interval of the threshold distribution of the Middle page is widened. As a result, the programming time can be shortened. In addition, it is possible to reduce errors in reading Middle pages.

(Eleventh Embodiment)
Next, the threshold distribution in the storage device of the eleventh embodiment will be described. The configuration of the storage device and the configuration of the non-volatile memory 2 of this embodiment are the same as those of the first embodiment. The data coding of this embodiment is the same as that of the fourth embodiment. Hereinafter, the points different from the fourth embodiment will be described.

For example, in the data coding of the fourth embodiment, the threshold distribution of the data value “11” and the threshold distribution of the data value “01” after the Middle page programming are the final distribution after the programming of the Upper page. The distribution is adjacent to. Therefore, although the number of distributions used in the Middle page is small, the data error probability is the same as that after the Upper page program when reading using the read voltage at the boundary between adjacent distributions. In particular, in the erase distribution (distribution Er), there is no voltage correction by programming thereafter, and stress (program disturb, read disturb, data retention) that causes a data error is accumulated. For this reason, the probability of data error is generally higher than that of other data distributions, and the error occurrence probability becomes higher when the erase distribution and the distribution adjacent to the erase distribution are used. Therefore, in the present embodiment, the probability of data error in the Middle page is reduced by making the distribution interval between the erased distribution and the adjacent distribution wider than the interval between other distributions.

FIG. 30 is a diagram showing an example of the threshold distribution after programming of each page in the present embodiment. In FIG. 30, the distribution 103 indicated by the dotted line shows the threshold distribution of the fourth embodiment. FIG. 30 shows that, when the same data coding as that of the fourth embodiment is performed, the central voltage of the data distribution other than the erase distribution is made higher than that of the threshold distribution 103 of the fourth embodiment. The interval between the erased distribution and its adjacent distribution is widened. As a result, the probability of data error in reading using the read voltage between the erase distribution and its adjacent distribution is reduced, and more accurate data can be read.

Although the modification of the fourth embodiment has been described here, another embodiment in which the data distribution after programming of the Middle page is the adjacent distribution of the final distribution after programming of the Upper page is described. Similarly, in the first embodiment, the second embodiment, and the sixth embodiment, the center voltage of the data distribution other than the erase distribution can be increased.

As described above, when the data distribution after programming the Middle page is the adjacent distribution in the final distribution after programming the Upper page, the center voltage of the data distribution other than the erase distribution is increased, that is, the erase distribution and The interval between the adjacent distributions is made wider than the interval between other distributions. As a result, the probability of data error in reading using the read voltage between the erase distribution and its adjacent distribution is reduced, and more accurate data can be read.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the scope equivalent thereto.

1 memory controller, 2 non-volatile memory, 14 ECC circuit, 22 control part, 23 NAND memory cell array.

Claims (8)

A word line, each is capable store connected 3-bit data to the word lines, and a nonvolatile memory having a plurality of memory cells corresponding the first page to the third page, and
A memory controller for controlling writing to the nonvolatile memory,
Equipped with
The nonvolatile memory is
Control to write data requested to be written from the memory controller to the memory cell,
When writing the first page to the erased memory cell, when the data written to the first page has a first value, the threshold voltage of the memory cell has a second threshold region. Program to
When the second page is written in the memory cell in which the first page is written, the value corresponding to the first page in the memory cell is the second value and the second value is the second value. If the data to be written to the page is at the first value, the threshold voltage of the memory cell is programmed to be in the fourth threshold region, and the value corresponding to the first page of the memory cell is set. Is the first value and the data to be written to the second page is the first value, the threshold voltage of the memory cell is programmed to be the third threshold region,
When the third page is written to the memory cell in which the second page is written, the value corresponding to the first page of the memory cell is the second value and the second value is the second value. When the value corresponding to the page is the second value and the data to be written to the third page is the first value, the threshold voltage of the memory cell becomes the sixth threshold region. Data written to the third page when the value corresponding to the first page of the memory cell is the first value and the value corresponding to the second page is the second value. Is the first value, the threshold voltage of the memory cell is programmed to be a seventh threshold region, and the value corresponding to the first page of the memory cell is the first value. When the value corresponding to the second page is the first value and the data to be written to the third page is the first value, the threshold voltage of the memory cell is set to the eighth threshold value. A region corresponding to the first page, the value corresponding to the first page is the second value, and the value corresponding to the second page is the first value, and the third value is the third value. If the data to be written to the page is the first value, the threshold voltage of the memory cell is programmed to be the fifth threshold region ,
A control unit in which the voltage value of the nth threshold region (n is an integer of 2 or more and 8 or less) is larger than the voltage value of the (n-1)th threshold region.
A memory system having . The number of boundaries of the threshold region for determining the value of the first page is three, and the number of boundaries of the threshold region for determining the value of the second page is three. And the number of boundaries of the threshold region for determining the value of the third page is one,
The memory system according to claim 1. A word line, each is capable store connected 3-bit data to the word lines, and a nonvolatile memory having a plurality of memory cells corresponding the first page to the third page, and
A memory controller for controlling writing to the nonvolatile memory,
Equipped with
The nonvolatile memory is
Control to write data requested to be written from the memory controller to the memory cell,
When writing the first page to the erased memory cell, when the data written to the first page has a first value, the threshold voltage of the memory cell is the fifth threshold region. Program to
When the second page is written in the memory cell in which the first page is written, the value corresponding to the first page in the memory cell is the second value and the second value is the second value. If the data to be written to the page is the first value, the threshold voltage of the memory cell is programmed to be the third threshold region, and the value corresponding to the first page of the memory cell is set. Is the first value and the data to be written to the second page is the second value, programming is performed such that the threshold voltage of the memory cell is in the sixth threshold region,
When the third page is written to the memory cell in which the second page is written, the value corresponding to the first page of the memory cell is the second value and the second value is the second value. When the value corresponding to the page is the second value and the data to be written in the third page is the first value, the threshold voltage of the memory cell is set to the second threshold region. Data to be written to the third page, wherein the value corresponding to the first page of the memory cell is the second value and the value corresponding to the second page is the first value. Is the second value, the threshold voltage of the memory cell is programmed to be in the fourth threshold region, and the value corresponding to the first page of the memory cell is the first value. When the value corresponding to the second page is the first value and the data to be written to the third page is the first value, the threshold voltage of the memory cell is the eighth threshold value. A region corresponding to the first page, the value corresponding to the first page is the first value and the value corresponding to the second page is the second value, and the third value is the third value. When the data to be written to the page has the first value, the threshold voltage of the memory cell is programmed to be the seventh threshold region ,
A control unit in which the voltage value of the nth threshold region (n is an integer of 2 or more and 8 or less) is larger than the voltage value of the (n-1)th threshold region.
A memory system having . A word line, each is capable store connected 3-bit data to the word lines, and a nonvolatile memory having a plurality of memory cells corresponding the first page to the third page, and
A memory controller for controlling writing to the nonvolatile memory,
Equipped with
The nonvolatile memory is
Control to write data requested to be written from the memory controller to the memory cell,
When writing the first page to the erased memory cell, when the data written to the first page has a first value, the threshold voltage of the memory cell is the fifth threshold region. Program to
When the second page is written in the memory cell in which the first page is written, the value corresponding to the first page in the memory cell is the second value and the second value is the second value. If the data to be written to the page is the first value, the threshold voltage of the memory cell is programmed to be in the second threshold region, and the value corresponding to the first page of the memory cell is set. Is the first value and the data to be written to the second page is the first value, the threshold voltage of the memory cell is programmed to be the seventh threshold region,
When the third page is written to the memory cell in which the second page is written, the value corresponding to the first page of the memory cell is the second value and the second value is the second value. When the value corresponding to the page is the second value and the data to be written in the third page is the first value, the threshold voltage of the memory cell is set to the fourth threshold region. Data to be written to the third page, wherein the value corresponding to the first page of the memory cell is the second value and the value corresponding to the second page is the first value. Is the first value, programming is performed such that the threshold voltage of the memory cell is in the third threshold region, and the value corresponding to the first page of the memory cell is the first value. When the value corresponding to the second page is the second value and the data written to the third page is the second value, the threshold voltage of the memory cell is the sixth threshold value. A region corresponding to the first page, the value corresponding to the first page is the first value, and the value corresponding to the second page is the first value, and the third value is the third value. When the data to be written to the page has the first value, the threshold voltage of the memory cell is programmed to be the eighth threshold region ,
A control unit in which the voltage value of the nth threshold region (n is an integer of 2 or more and 8 or less) is larger than the voltage value of the (n-1)th threshold region.
A memory system having . A word line, each is capable store connected 3-bit data to the word lines, and a nonvolatile memory having a plurality of memory cells corresponding the first page to the third page, and
A memory controller for controlling writing to the nonvolatile memory,
Equipped with
The nonvolatile memory is
Control to write data requested to be written from the memory controller to the memory cell,
When writing the first page to the erased memory cell, when the data written to the first page has a first value, the threshold voltage of the memory cell is the third threshold region. Program to
When the second page is written in the memory cell in which the first page is written, the value corresponding to the first page in the memory cell is the second value and the second value is the second value. If the data to be written to the page is the first value, the threshold voltage of the memory cell is programmed to be the sixth threshold region, and a value corresponding to the first page of the memory cell is programmed. Is the first value and the data to be written to the second page is the first value, the threshold voltage of the memory cell is programmed to be the fifth threshold region.
When the third page is written to the memory cell in which the second page is written, the value corresponding to the first page of the memory cell is the second value and the second value is the second value. When the value corresponding to the page is the second value and the data to be written in the third page is the first value, the threshold voltage of the memory cell is set to the second threshold region. Data written to the third page when the value corresponding to the first page of the memory cell is the first value and the value corresponding to the second page is the second value. Is the second value, the threshold voltage of the memory cell is programmed to be in the fourth threshold region, and the value corresponding to the first page of the memory cell is the first value. When the value corresponding to the second page is the first value and the data to be written to the third page is the first value, the threshold voltage of the memory cell is the eighth threshold value. A region corresponding to the first page, the value corresponding to the first page is the second value, and the value corresponding to the second page is the first value, and the third value is the third value. When the data to be written to the page has the first value, the threshold voltage of the memory cell is programmed to be the seventh threshold region ,
A control unit in which the voltage value of the nth threshold region (n is an integer of 2 or more and 8 or less) is larger than the voltage value of the (n-1)th threshold region.
A memory system having . A word line, each is capable store connected 3-bit data to the word lines, and a nonvolatile memory having a plurality of memory cells corresponding the first page to the third page, and
A memory controller for controlling writing to the nonvolatile memory,
Equipped with
The nonvolatile memory is
Control to write data requested to be written from the memory controller to the memory cell,
When writing the first page to the erased memory cell, when the data written to the first page has a first value, the threshold voltage of the memory cell has a second threshold region. Program to
When the second page is written in the memory cell in which the first page is written, the value corresponding to the first page in the memory cell is the second value and the second value is the second value. If the data to be written to the page is at the first value, the threshold voltage of the memory cell is programmed to be in the fifth threshold region, and the value corresponding to the first page of the memory cell is set. Is the first value and the data to be written to the second page is the first value, the threshold voltage of the memory cell is programmed to be the seventh threshold region,
When the third page is written to the memory cell in which the second page is written, the value corresponding to the first page of the memory cell is the second value and the second value is the second value. When the value corresponding to the page is the second value and the data to be written to the third page is the first value, the threshold voltage of the memory cell becomes the fourth threshold region. Data written to the third page when the value corresponding to the first page of the memory cell is the first value and the value corresponding to the second page is the second value. Is the first value, programming is performed such that the threshold voltage of the memory cell is in the third threshold region, and the value corresponding to the first page of the memory cell is the second value. When the value corresponding to the second page is the first value and the data to be written to the third page is the second value, the threshold voltage of the memory cell is the sixth threshold value. A region corresponding to the first page, the value corresponding to the first page is the first value, and the value corresponding to the second page is the first value, and the third value is the third value. When the data to be written to the page has the first value, the threshold voltage of the memory cell is programmed to be the eighth threshold region ,
A control unit in which the voltage value of the nth threshold region (n is an integer of 2 or more and 8 or less) is larger than the voltage value of the (n-1)th threshold region.
A memory system having . 7. The memory system according to claim 1, wherein the first value is 0 and the second value is 1. The number of boundaries of the threshold region for determining the value of the first page, the number of boundaries of the threshold region for determining the value of the second page, the value of the third page 8. The memory system according to claim 1, wherein the maximum number of boundaries of the threshold region for determination is three.

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