TWI542010B - Method of forming integrated circuit - Google Patents

Description

Method of forming integrated circuit

The present invention relates to integrated circuits, and more particularly to a method of forming an integrated circuit with a modified isolation structure and a gate dielectric structure.

A gold oxide half field effect transistor (MOSFET) has a gate, a substrate, and a gate dielectric layer between the gate and the substrate. By controlling the gate voltage, conductive channels in the substrate under the gate dielectric layer can be created or adjusted. Increasing the thickness of the gate dielectric layer in some applications increases the gate-to-source breakdown voltage of the MOSFET. In some applications, the diffusion drain region is used to increase the breakdown voltage of the MOSFET from the drain to the source. For example, various MOSFETs are configured to have an increased breakdown voltage, and the MOSFET includes a laterally diffused gold oxide half (LDMOS) transistor and a double diffused gated metal oxide half (DDDMOS) transistor.

A method for forming an integrated circuit according to an embodiment of the present invention includes: forming an isolation structure partially buried in a substrate, and a part of the isolation structure is convex from an upper surface of the substrate; partially removing the isolation Structure to form a modified isolation structure, and the upper surface of the improved isolation structure is lower than the upper surface of the substrate; and the gate dielectric structure is formed, the gate dielectric structure is partially located on the substrate, and is partially improved The isolation structure is on the surface.

A method for forming an integrated circuit according to an embodiment of the present invention includes: forming a first isolation structure partially buried in a first well region of a substrate, first The well region has a first doping profile, and the upper surface of the first isolation structure is convex from the upper surface of the substrate; the first isolation structure is partially removed to form an improved isolation structure, and the upper surface of the improved isolation structure Lower than the upper surface of the substrate; and forming a gate dielectric structure, the gate dielectric structure is partially located on the second well region of the substrate, partially on the first well region of the substrate, and partially Located on the upper surface of the modified isolation structure, wherein the second well region has a second doping profile.

A method for forming an integrated circuit according to an embodiment of the present invention includes: forming a first isolation structure partially buried in a first well region of a substrate, the first well region having a first doping type, and first The upper surface of the isolation structure is convex from the upper surface of the substrate; the first isolation structure is partially removed to form an improved isolation structure, and the upper surface of the improved isolation structure is lower than the upper surface of the substrate; forming a gate dielectric structure The gate dielectric structure is partially located on the second well region of the substrate, partially on the first well region of the substrate, and partially on the upper surface of the modified isolation structure, wherein the second well region Having a second doping type; and forming a gate structure on the gate dielectric structure, the upper surface of the gate structure having a first portion and a second portion, wherein the first portion is directly on the modified isolation structure The second portion is directly on the second well region, and the first portion is lower than the second portion or is equal to the second portion.

100‧‧‧ integrated circuit

110‧‧‧Substrate

110a, 122a, 134b‧‧‧ upper surface

112‧‧‧First Well Area

114‧‧‧Second well area

122‧‧‧ Improved isolation structure

124‧‧‧Second isolation structure

126‧‧‧ third isolation structure

132‧‧‧ gate dielectric structure

134‧‧‧ gate structure

134a, 136a, 138a‧‧‧ metal deuteration

134b-1‧‧‧ first part

134b-2‧‧‧ Part II

135a‧‧‧First spacer

135b‧‧‧Second spacer

136‧‧ ‧ bungee area

138‧‧‧ source area

142‧‧‧etch stop layer

152‧‧‧ILD layer

154‧‧‧Electrical circuit

200‧‧‧ method

210, 220, 230, 240, 250, 260, 270, 280, 290 ‧ ‧ steps

310‧‧‧First isolation structure

320‧‧‧patterned mask

Figure 1 is a cross-sectional view of an integrated circuit in some embodiments.

Figure 2 is a flow diagram of a method of fabricating an integrated circuit in some embodiments.

3A through 3G are cross-sectional views of integrated circuits in various process stages in certain embodiments.

The various embodiments provided by the disclosure below may embody different structures of the invention. The specific components and arrangements described below are intended to simplify the invention and not to limit the invention. For example, the description of forming the first member on the second member includes direct contact between the two, or the other is spaced apart from other direct members rather than in direct contact. In addition, the repeated reference numerals and/or symbols in the various embodiments of the present invention will be simplified and clarified, but these repetitions do not represent the same correspondence between the elements of the same reference numerals in the various embodiments.

On the other hand, spatial relative terms such as "below", "below", "below", "above", "above", or similar terms may be used to simplify the illustration of one component and another component. The relative relationship in the middle. Spatial relative terms may be extended to elements used in other directions, and are not limited to the illustrated orientation. The component can also be rotated by 90° or other angles, so the directional terminology is only used to illustrate the orientation in the illustration.

In some embodiments, the LDMOS or DDDMOS has at least two or more segments of a gate dielectric layer of different thicknesses. In some embodiments, the gate dielectric layer can be formed by an isolation structure embedded in the substrate and a layer of gate dielectric material formed thereon. The upper surface of the isolation structure is lower than the upper surface of the substrate. As a result, the margin for avoiding a short circuit between the conductive line and the gate can be improved. The gate is directly on the isolation structure. In some embodiments, the improved process range reduces the thickness of the interlayer dielectric (ILD) layer and the conductive traces are formed on the ILD.

Figure 1 is a cross-sectional view of integrated circuit 100 in some embodiments. In some embodiments, the integrated circuit 100 shown in FIG. 1 is an intermediate product, which can Further one or more processes are performed to form a functional integrated circuit. Other active electronic components and passive electronic components of the integrated circuit 100 are not shown in FIG.

The integrated circuit 100 has a substrate 110 that can form a first well region 112 and a second well region 114 after one or more implant processes. The integrated circuit 100 has a modified isolation structure 122, a second isolation structure 124, and a third isolation structure 126. The integrated circuit 100 also has a gate dielectric structure 132, a gate structure 134, spacer structures such as a first spacer structure 135a and a second spacer 135b, a drain region 136, a source region 138, an etch stop layer 142, ILD layer 152, and conductive line 154. In some embodiments, the first well region 112 and the second well region 114, the modified isolation structure 122, the gate dielectric structure 132, the gate structure 134, the spacer structure such as the first spacer 135a and the second spacer The object 135b, the drain region 136, and the source region 138 together form an LDMOS (laterally diffused gold oxide half) transistor. For example, LDMOS is as disclosed in FIG. In some embodiments, the methods disclosed below can be used to fabricate other types of LDMOS transistors, or multiple DDDMOS (dual-diffused-dip MOS) transistors.

In some embodiments, substrate 110 comprises a semiconductor element such as a single crystal, polycrystalline, or amorphous germanium or germanium; a semiconductor compound such as tantalum carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, arsenic Indium, and/or indium antimonide; semiconductor alloys such as germanium (SiGe), gallium arsenide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphorus (GaInP), and/or gallium indium arsenide (GaInAsP); or a combination thereof. In at least one embodiment, the substrate 110 is a semiconductor alloy substrate and has a 渐变 structure with a gradual composition, that is, the composition ratio of 矽 and 某 gradually changes to another composition ratio of 矽 and 锗. In another embodiment, a tantalum alloy is formed on the tantalum substrate. In yet another embodiment, The substrate has stress. In certain other embodiments, substrate 110 is a semiconductor on insulator (SOI). In some examples, substrate 110 comprises an epitaxial layer or a buried layer. In other examples, substrate 110 comprises a multilayer semiconductor compound structure.

The conductivity of substrate 110 in certain embodiments is generally similar to that of an intrinsic semiconductor material or a semiconductor material having a predetermined doping profile. In some embodiments, the predetermined doping profile is p-type doping.

The substrate 110 has a first well region 112 and a second well region 114 formed between the second isolation structure 124 and the third isolation structure 126. The first well region 112 and the second well region 114 have different doping profiles. In some embodiments, if the LDMOS transistor of FIG. 1 is an n-type transistor, the first well region 112 has an n-type doping and the second well region 114 has a p-type doping. In some embodiments, if the LDMOS transistor in FIG. 1 is a p-type transistor, the first well region has p-type doping and the second well region 114 has n-type doping. In some embodiments, one or more deep well zones (not shown) are formed under the first well zone 112 and the second well zone 114 to electrically circuit the substrate 110 with the first well zone 112 / the second well zone 114 Sexual isolation.

The modified isolation structure 122 is embedded in the first well region 112 of the substrate 110. The upper surface 122a of the modified isolation structure 122 is lower than the upper surface 110a of the substrate 110. In some embodiments, the vertical distance between the upper surface 122a of the improved isolation structure 122 and the upper surface 110a of the substrate 110 is greater than or equal to 300 Å. In certain embodiments, the improved isolation structure 122 comprises ruthenium oxide.

The gate dielectric structure 132 is partially located on the second well region 114 of the substrate 110, partially on the first well region 112 of the first substrate 110, and partially on the upper surface 122a of the modified isolation structure 122. on. In some embodiments, the gate dielectric structure 132 comprises germanium oxide or a high-k dielectric material. material. In some embodiments, the gate dielectric structure 132 has a multilayer structure that includes one or more layers of different dielectric materials. In some embodiments, the gate dielectric structure 132 is configured to have a sufficient thickness to provide the transistor with a predetermined gate-to-source breakdown voltage. In some embodiments, the gate structure 134 of the LDMOS in FIG. 1 is configured to operate at a voltage of approximately 32 volts, and the gate dielectric structure 132 is configured to have a thickness of 200 Å to 1200 Å.

Gate structure 134 is located on gate dielectric structure 132. In some embodiments, the gate structure 134 comprises polysilicon, or one or more metal materials such as copper, aluminum, tungsten, titanium, or alloys of the foregoing, or combinations thereof. In some embodiments, the gate structure 134 has a multilayer structure. In FIG. 1, the upper half of the gate structure 134 includes a metal deuteration layer 134a. In some embodiments, the metal deuteration layer 134a can be omitted. The upper surface 134b of the gate structure 134 has a first portion 134b1 and a second portion 134b-2. The first portion 134b-1 is directly on the modified isolation structure 122, and the second portion is directly located in the second well region. 114 on. In some embodiments, the first portion 134b-1 of the upper surface 134b is of the same height as the second portion 134b-2. In some embodiments, the first portion 134b-1 of the upper surface 134b is lower than the second portion 134b-2.

In addition, the spacer structure includes a first spacer 135a and a second spacer 135b on the sidewalls of the gate dielectric structure 132 and the gate structure 134, respectively. In some embodiments, the material of the first spacer 135a and the second spacer 135b comprise tantalum nitride. The first spacer 135a is located on the modified isolation structure 122. The second spacer 135b is located on the second well region 114 and is located between the modified isolation structure 122 and the third isolation structure 126. The drain region 136 is located in the first well region 112 and is located between the modified isolation structure 122 and the second isolation structure 124. The source region 138 is located at the second spacer 135b and the third isolation structure 126 of the spacer structure. In the second well zone 114. In some embodiments, if the LDMOS in FIG. 1 is an n-type transistor, the drain region 136 and the source region 138 have n-type doping, and the doping concentration thereof is greater than that of the first well region 112. concentration. In some embodiments, if the LDMOS in FIG. 1 is a p-type transistor, the drain region 136 and the source region 138 have p-type doping, and the doping concentration thereof is greater than that of the first well region 112. concentration. The upper half of the drain region 136 includes a metal germanium layer 136a. The upper half of the source region 138 includes a metal deuteration layer 138a. In some embodiments, metal deuteration layers 136a and 138a may be omitted.

Further, the etch stop layer 142 in FIG. 1 covers the substrate 110 and the LDMOS transistor. The ILD layer 152 covers the etch stop layer 142 and the conductive traces 154 are formed on the ILD layer 152. In the cross-sectional view of FIG. 1, the conductive traces 154 are not physically in contact with the gate 134, the drain region 136, or the source region 138. The conductive traces 154 in some embodiments can be electrically coupled to one or more of the gate structures 134, the drain regions 136, and the source regions 138 at locations other than the cross-sectional view of FIG.

In some embodiments, since the upper surface 122a of the improved isolation structure 122 is lower than the upper surface 110a of the substrate 110, the first portion 134b-1 of the upper surface 134b is also lower than the second portion 134b-2. As such, the vertical distance between the conductive traces 154 and the gate structures 134 directly on the modified isolation structure 122 is greater than the vertical distance between the conductive traces 154 and the gate structures 134 directly on the second well region 114. . In some embodiments, a larger spacing between the conductive traces 154 and the gate structures 134 on the modified isolation structure 122 provides an additional process range to avoid conductive traces 154 and gate structures 134 due to process variations. An unexpected short circuit occurs between them.

In some embodiments, the wiring design for designing the integrated circuit 100 The rule is that the conductive traces of the same conductive layer of the conductive traces 154 should be avoided over the second portion 134b-2 of the upper surface 134 of the LDMOS transistor.

2 is a flow diagram of a method 200 of fabricating integrated circuit 100 in some embodiments. 3A through 3G are cross-sectional views of integrated circuit 100 in various process stages in certain embodiments. In the drawings 2 and 3A to 3G, the same members as those in Fig. 1 will be given the same reference numerals, and detailed description will be omitted. It will be appreciated that additional steps may be performed before, during, and/or after the method 200 of FIG. 2, and certain additional steps are only briefly described below.

As shown in Figures 2 and 1, the initial step 210 of method 200 forms an isolation structure in the substrate. The substrate has a first well region of a first doping profile and a second well region of a second doped profile. A first isolation structure is formed in the first well region, and second and third isolation structures are formed in the edges of the first well region and the second well region. In some embodiments, the first, second, and third isolation structures are formed by a local yttrium oxide (LOCOS) process or a shallow trench isolation (STI) process. In some embodiments, step 210 further includes forming a patterned mask to protect the second and third isolation structures from one or more subsequent steps.

Fig. 3A is a cross-sectional view showing the integrated circuit 100 after the step 210 is performed. The first isolation structure 310 is partially buried in the first well region 112 of the substrate 110. The upper half of the first isolation structure 310 is convex from the upper surface 110a of the substrate 110. The second isolation structure 124 is partially embedded in the edge of the first well region 112 of the substrate 110. The third isolation structure 126 is partially embedded in the edge of the second well region 114 of the substrate 110. In some embodiments, the first isolation structure 310, the second isolation structure 124, and the third isolation structure 126 have substantially the same depth from the upper surface 110a. The first well region 112, the second well region 114, and the entire first isolation structure 310 The main portions are located between the second isolation structure 124 and the third isolation structure 126. The patterned mask 320 covers the second isolation structure 124 and the third isolation structure 126.

Step 220 of method 200 is then performed to remove portions of the first isolation structure to form a modified isolation structure. The upper surface of the improved isolation structure is lower than the upper surface of the substrate. In some embodiments, step 220 includes a dry oxide etch process and/or a wet oxide etch process. In some embodiments, the dry etch process includes a non-isotropic etch that is dominated by fluorocarbon gases. In certain embodiments, the wet etch process comprises a hydrofluoric acid solution, such as a buffered oxide etchant (BOE) or a hydrofluoric acid buffer solution (BHF).

Fig. 3B is a cross-sectional view showing the integrated circuit after step 220. The first isolation structure 310 is converted to a modified isolation structure 122. The upper surface 122a of the improved isolation structure 122 is lower than the upper surface 110a of the substrate 110. In some embodiments, the vertical distance between the upper surface 122a of the improved isolation structure 122 and the upper surface 110a of the substrate 110 is greater than or equal to 300 Å. The patterned mask 320 remains to protect the second isolation structure 124 and the third isolation structure 126 from one or more subsequent steps.

Step 230 of method 200 is then performed to form a gate dielectric structure. The gate dielectric structure is partially on the second well region of the substrate, partially on the first well region of the substrate, and partially on the upper surface of the modified isolation structure. In some embodiments, the gate dielectric structure comprises ruthenium oxide and step 230 comprises a thermal oxidation process. In certain embodiments, the thermal oxidation process is carried out in a furnace having a temperature between 500 ° C and 1100 ° C. In some embodiments, after forming the gate dielectric structure, step 230 further includes removing the patterned mask formed in step 210.

3C is a cross-sectional view of the integrated circuit 100 after performing step 230. The gate dielectric structure 132 is located on the second well region 114, the first well region 112, and the upper portion of the modified isolation structure 122. The above structure has removed the patterned mask 320.

Step 240 of method 200 is then performed to form a gate structure. The gate structure is located on the gate dielectric structure. In some embodiments, the gate structure comprises polysilicon, or one or more metallic materials.

The 3D drawing is a cross-sectional view of the integrated circuit 100 after the step 240 is performed. Gate structure 134 is located on gate dielectric structure 132.

In some embodiments, steps 230 and 240 are performed by forming one or more layers of gate dielectric material on substrate 110 and modified isolation structure 122, followed by forming one or more layers of gate material in one or more layers. On the gate dielectric material. Finally, one or more layers of gate dielectric material and one or more gate materials are patterned to form gate dielectric structure 132 and gate structure 134, as shown in FIG. 3D.

Step 250 of method 200 is then performed to form a spacer structure on the sidewalls of the gate dielectric structure and the gate structure. In some embodiments, step 250 includes forming a layer of spacer material on the structure of the 3D pattern and performing an anisotropic etch process. In some embodiments, the material of the spacer structure comprises tantalum nitride.

Fig. 3E is a cross-sectional view of the integrated circuit 100 after the step 250 is performed. The spacer structure includes a first spacer 135a and a second spacer 135b on the sidewalls of the gate dielectric structure 132 and the gate structure 134, respectively. The first spacer 135a is located on the modified isolation structure 122 on the first well region 112. The second spacer 135b is located on the second well region 114 between the modified isolation structure 122 and the third isolation structure 126.

Step 260 of method 200 is then performed to form a drain region in the first well region and form a source region in the second well region. In some embodiments, step 260 includes forming a mask having an exposed portion of the first well region for forming a drain region and exposing a portion of the second well region for forming a source region for implantation. Process.

The 3F is a cross-sectional view of the integrated circuit 100 after the step 260 is performed. The drain region 136 is formed in the first well region 112 between the modified isolation structure 122 and the second isolation structure 124. The source region 138 is formed in the second well region 114 between the second spacer 135b and the third isolation structure 126.

Step 270 of method 200 is then performed to perform a metal deuteration process on the gate structure, the source region, or the drain region. In some embodiments, step 270 includes forming a metal material on the gate structure, the source region, or the drain region, and then performing a tempering process to form the metal deuterated layer, followed by removing the unreacted metal material.

The 3Gth diagram is a cross-sectional view of the integrated circuit 100 after the step 270 is performed. The upper half of the gate structure 134 is transformed into a metal deuteration layer 134a. The upper half of the drain region 136 is transformed into a metal germanium layer 136a, and the upper half of the source region 138 is transformed into a metal germanium layer 138a. In some embodiments, not all of the gate structure 134, the drain region 136, and the source region 138 are subjected to the metal deuteration process of step 270. In some embodiments, step 270 can be omitted.

Step 280 of method 200 is then performed to form an etch stop layer on the structure after completion of step 270, forming an ILD layer on the etch stop layer, and forming a conductive trace on the ILD layer. In some embodiments, the ILD layer is selectively etched to form a contact opening and one or more contacts are plugged into the contact opening prior to forming the conductive trace. In some embodiments, chemical mechanical polishing is performed (CMP) to match the formation of the contact plug.

Fig. 1 is a cross-sectional view showing the integrated circuit 100 after the step 280 is performed.

Step 290 of method 200 is then performed, based on the modified isolation structure 122 and the gate dielectric structure 132, for additional operations to form the LDMOS transistor. In some embodiments, the structures completed in steps 210 through 280 can also be used to form DDDMOS.

In an embodiment, the method includes forming an isolation structure, and the isolation structure is partially buried in the substrate. A portion of the isolation structure is raised from the upper surface of the substrate. The isolation structure is partially removed to form an improved isolation structure. The upper surface of the modified isolation structure is lower than the upper surface of the substrate. A gate dielectric structure is formed, the gate dielectric structure being partially on the substrate and partially on the upper surface of the modified isolation structure.

In another embodiment, a method includes forming a first isolation structure partially embedded in a first well region of a substrate. The first well region has a first doping profile, and the upper surface of the first isolation structure is raised from the upper surface of the substrate. The first isolation structure is partially removed to form a modified isolation structure. The upper surface of the improved isolation structure is lower than the upper surface of the substrate. Forming a gate dielectric structure, the gate dielectric structure being partially located on the second well region of the substrate, partially on the first well region of the substrate, and partially on the upper surface of the modified isolation structure . The second well region has a second doping profile.

In another embodiment, a method includes forming a first isolation structure partially embedded in a first well region of a substrate. The first well region has a first doping profile, and the upper surface of the first isolation structure is raised from the upper surface of the substrate. The first isolation structure is partially removed to form a modified isolation structure. Improved isolation structure The surface is lower than the upper surface of the substrate. The method also forms a gate dielectric structure, the gate dielectric structure being partially located on the second well region of the substrate, partially on the first well region of the substrate, and partially located in the modified isolation structure. On the upper surface. The second well region has a second doping profile. A gate structure is formed on the gate dielectric structure. The upper surface of the gate structure has a first portion and a second portion, wherein the first portion is directly on the modified isolation structure and the second portion is directly on the second well region. The first portion is lower than or equal to the second portion.

While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ integrated circuit

110‧‧‧Substrate

110a, 122a, 134b‧‧‧ upper surface

112‧‧‧First Well Area

114‧‧‧Second well area

122‧‧‧ Improved isolation structure

124‧‧‧Second isolation structure

126‧‧‧ third isolation structure

132‧‧‧ gate dielectric structure

134‧‧‧ gate structure

134a, 136a, 138a‧‧‧ metal deuteration

134b-1‧‧‧ first part

134b-2‧‧‧ Part II

135a‧‧‧First spacer

135b‧‧‧Second spacer

136‧‧ ‧ bungee area

138‧‧‧ source area

142‧‧‧etch stop layer

152‧‧‧ILD layer

154‧‧‧Electrical circuit

Claims (10)

A method for forming an integrated circuit includes: forming an isolation structure partially embedded in a well region of a substrate, the isolation structure being from an upper surface of the substrate and an upper surface of the well region Raising, and the upper surface of the substrate is flush with the upper surface of the well region; the isolation structure is partially removed to form a modified isolation structure, and the upper surface of the improved isolation structure is lower than the substrate An upper surface; and a gate dielectric structure partially located on the substrate and partially on the upper surface of the modified isolation structure. The method of forming an integrated circuit according to claim 1, wherein a vertical distance between an upper surface of the improved isolation structure and an upper surface of the substrate is greater than or equal to 300 Å. The method for forming an integrated circuit according to claim 1, further comprising: forming a source region and a drain region in the substrate after forming the improved isolation structure. The method for forming an integrated circuit according to claim 1, further comprising: forming a gate structure on the gate dielectric structure, and the upper surface of the gate structure has a first portion and a The second part, wherein the first part is different from the second part, the first part is directly located on the modified isolation structure, and the first part is lower than the second part or Two portions of the same height; forming a spacer structure on the gate dielectric structure and sidewalls of the gate structure; and forming a source region and a drain region in the substrate. A method of forming an integrated circuit, comprising: Forming a first isolation structure partially embedded in a first well region of a substrate, the first well region having a first doping type, and an upper surface of the first isolation structure from the substrate Surface embossing; partially removing the first isolation structure to form a modified isolation structure, the upper surface of the improved isolation structure being lower than the upper surface of the substrate; and forming a gate dielectric structure, the gate The pole dielectric structure is partially located on a second well region of the substrate, partially on the first well region of the substrate, and partially on an upper surface of the modified isolation structure; The second well region has a second doping profile. The method of forming an integrated circuit according to claim 5, wherein the first doping type is n-type doping, and the second doping type is p-type doping. The method of forming an integrated circuit according to claim 5, wherein a vertical distance between the upper surface of the improved isolation structure and the upper surface of the substrate is greater than or equal to 300 Å. The method for forming an integrated circuit according to claim 5, further comprising: forming a drain region in the first well region, and the drain region is located in the improved isolation structure and the second isolation structure And forming a source region in the second well region, and the source region is located between the modified isolation structure and the third isolation structure, wherein the step of forming the drain region and the drain region This includes performing a coating process corresponding to the first doping profile. The method for forming an integrated circuit according to claim 5, further comprising: forming a gate structure on the gate dielectric structure, the upper surface of the gate structure having a first portion and a first The second part, wherein the first part is directly located on the improved isolation structure, and the second part is directly located in the second well area And the first portion is lower than or equal to the second portion; forming a spacer structure on the gate dielectric structure and the sidewall of the gate structure; forming a drain The region is located in the first well region, and the drain region is located between the modified isolation structure and the second isolation structure; and a source region is formed in the second well region, and the source region is located in the Between the improved isolation structure and the third isolation structure, and between the spacer structure and the third isolation structure. A method for forming an integrated circuit includes: forming a first isolation structure partially embedded in a first well region of a substrate, the first well region having a first doping type, and the first The upper surface of the isolation structure is convex from the upper surface of the substrate; the first isolation structure is partially removed to form a modified isolation structure, the upper surface of the improved isolation structure is lower than the upper surface of the substrate; a gate dielectric structure partially located on a second well region of the substrate, partially on the first well region of the substrate, and partially located in the modified On the upper surface of the isolation structure, wherein the second well region has a second doping type; and a gate structure is formed on the gate dielectric structure, the upper surface of the gate structure has a first portion And a second portion, wherein the first portion is directly on the modified isolation structure, the second portion is directly on the second well region, and the first portion is lower than the second portion or Contrast with the second part.