TWI538061B - A method of manufacturing a transistor - Google Patents

Description

Method of making crystal

This invention relates to a transistor, and more particularly to a method of fabricating a space charge limited transistor.

The structure concept and operation principle of Space-Charge-Limited Transistor (SCLT) are similar to vacuum triodes. The emitter (Emitter) corresponds to the heated cathode in the vacuum tube as the carrier injection end; the collector corresponds to the anode metal plate, and is responsible for collecting the carriers passing through the channel; the base corresponds to the grid ( Grid), which acts as a switch that controls the current in the channel; the vacuum layer corresponds to the semiconductor transport layer of the carrier.

The SCLT is actuated by an output current of up to 50 mA/cm ² when the SCLT is turned on, and the current density can drive an active-matrix organic light-emitting diode (AMOLED). However, when the SCLT is off, it will generate a leakage current of 10 ^-3 ~ 10 ^-4 .

Therefore, the conductor layer is covered by the film to overcome the problem of leakage current of the transistor.

Nowadays, the preparation method of the nano film is quite diverse, and it can be roughly classified into a dry coating method and a wet coating method (Wet). Coating method). This wet coating method has been widely used in the transistor process in recent years because the wet coating method is characterized by high efficiency and low cost. For example, the most widely used method of the wet coating method is a spin coating method and a dip coating method.

However, the spin coating method is generally limited to coating on a flat surface. If a film is formed on an irregular surface (such as a columnar structure) by spin coating, it may fill a hole or a film floating in the irregularity. The surface condition occurs.

Further, although the dip coating method can form a film on an irregular surface, it is limited by the influence of liquid viscosity and gravity, and the film thickness is limited to have an insulating effect.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

The invention provides a method for manufacturing a transistor, comprising: providing a substrate and a carrier, forming an insulating layer on the substrate with a plurality of exposed portions of the substrate, and forming on the insulating layer a conductor layer, and a fluid coating material formed on the surface of the carrier; the substrate is disposed on the carrier such that the conductor layer contacts the fluid cladding material; moving the substrate to move the substrate away from the substrate a carrier for diffusing the fluid coating material to cover the conductor layer; and leaving the conductor layer completely away from the surface of the fluid cladding material on the carrier member to coat the fluid cladding material on the conductor layer Floor.

In the above method, the substrate has a collector layer, and the insulating layer is a nanostructure.

In the above method, the channels are connected to each other such that the insulating layer is formed into a structure having a plurality of columns.

In the above manufacturing method, the conductor layer is a base layer, and for example, the material forming the conductor layer is a metal material.

In the above preparation method, the fluid coating material is prepared by dissolving polyvinylpyrrolidone powder in deionized water, and the concentration of the fluid coating material is 1 to 5 wt%.

In the above method, the concentration of the fluid coating material and the velocity of the substrate away from the carrier are used to control the surface area of the fluid coating material covering the conductor layer.

In the above production method, the material forming the coating layer is an insulating material.

In the above method, after the conductor layer completely leaves the surface of the fluid cladding material, the coating layer is cured.

In the foregoing method, the coating layer is extended to the surface of the channel.

In the foregoing method, the method further includes forming a semiconductor layer to cover the insulating layer and the cladding layer, and further comprising forming an emitter layer on the semiconductor layer.

As can be seen from the above, the transistor of the present invention is formed by coating the conductor layer with a cladding layer to overcome the problem of leakage current in the prior art.

Furthermore, the fluid coating material diffuses and covers the conductor layer by the surface tension of the fluid coating material and the siphon phenomenon between the conductor layers to move the substrate away from the carrier. The film is formed and the problem that the film thickness is too thin can be overcome.

1‧‧‧Optoelectronics

10‧‧‧Substrate

100‧‧‧ glass plate

101‧‧‧ Collector

11‧‧‧Insulation

110‧‧‧ channel

12‧‧‧Conductor layer

13, 13'‧‧‧ coating

14‧‧‧Semiconductor layer

15‧‧ ‧ emitter layer

20, 20', 50, 50' ‧ ‧ fluid cladding materials

30‧‧‧Carrier

40‧‧‧ ultraviolet light

Figure 1 is a schematic cross-sectional view of a transistor of the present invention; 2A to 2F are schematic cross-sectional views showing a first embodiment of a method for fabricating a transistor of the present invention; and Figs. 3A to 3E are cross-sectional views showing a second embodiment of the method for fabricating the transistor of the present invention; A first SEM image of a transistor made by the method of the invention of the invention; and a fifth SEM image of the transistor produced by the method of the transistor of the invention.

The embodiments of the present invention are described in the following specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present invention by the contents disclosed in the present specification, and can also be implemented by other different embodiments. Or application. Accordingly, any component or method of any particular embodiment disclosed herein may be combined with any component or method of any other embodiment disclosed herein.

Fig. 1 is a schematic cross-sectional view showing a transistor 1 of the present invention. As shown in FIG. 1, the transistor 1 includes a substrate 10, an insulating layer 11 formed on the substrate 10, a conductor layer 12 formed on the insulating layer 11, and a conductor. A cladding layer 13 of the layer 12, a semiconductor layer 14 covering the insulating layer 11 and the cladding layer 13, and an emitter layer 15 provided on the semiconductor layer 14.

The substrate 10 has a glass plate 100 and a collector layer 101 such as an indium tin oxide material (ITO) provided on the glass plate 100.

The insulating layer 11 has a plurality of exposed substrates 10 (such as collectors) The channel 110 of the layer 101), and each of the channels 110 is of a nanometer size, so that the insulating layer 11 has a nanostructure. When the nanostructure is fabricated, if the channels 110 are in communication with each other, the insulating layer 11 will form a structure having a plurality of nano-pillars.

The conductor layer 12 is a base layer and is vapor-deposited on the top surface of the insulating layer 11, so that the conductor layer 12 has a mesh shape. In this embodiment, the material of the conductor layer 12 is a metal material such as aluminum. In addition to evaporation, it is also possible to use sputtering, E-beam and other process technologies. This case is not limited to this.

The covering layer 13 extends to a part of the surface of the channel 110 to optimize the effect of preventing leakage current of the transistor 1. In this embodiment, the material of the coating layer 13 is an insulating material, for example, polyethylene tetrahydrofuranone (PVP), fluorinated rubber (CYTOP) or polyvinyl alcohol (PVA), etc., but is not limited thereto. .

The material of the semiconductor layer 14 is an organic material, such as poly(3-hexylthiophene-2,5-diyl) (abbreviated as P3HT).

The material of the emitter layer 15 is aluminum or aluminum coated with molybdenum trioxide (MoO ₃ ).

In the transistor 1 of the present invention, when the conductor layer 12 is covered by the cladding layer 13, the energy barrier between the conductor layer 12 and the semiconductor layer 14 becomes high, that is, the leakage current can be reduced.

Therefore, the covering layer 13 covers only the top surface of the conductor layer 12 to prevent leakage current. Preferably, the cladding layer 13 covers the top surface and the side surface of the conductor layer 12 to enhance the effect of preventing leakage current. More preferably, the covering layer 13 extends to the side of the insulating layer 11 to further enhance the prevention. The effect of leakage current.

The process of the cladding layer 13 will be described below by the first to second embodiments.

2A to 2F are schematic cross-sectional views showing a first embodiment of the method of manufacturing the transistor 1 of the present invention.

As shown in FIG. 2A, a substrate 10 is provided. The substrate 10 is formed with an insulating layer 11 having a plurality of channels 110 exposing the substrate 10, and a conductor layer 12 is formed on the insulating layer 11. .

As shown in FIG. 2B, a carrier 30 such as a container is provided, and the carrier 30 is filled with a fluid covering material 20, and the substrate 10 is inverted up toward the fluid covering material 20, and the The conductor layer 12 is partially immersed in the fluid cladding material 20 perpendicularly to the insulating layer 11.

In the present embodiment, the substrate 10 and all of the conductor layer 12 may not be immersed in the fluid cladding material 20.

Furthermore, the fluid coating material 20 is prepared by dissolving polyvinylpyrrolidone (PVP) powder in deionized water at a concentration of 1 to 5 wt%. In other words, the fluid coating material 20 is a liquid prepared by mixing a large amount of solvent and a small amount of solute.

Further, the fluid coating material 20 may be formulated to a certain concentration by fluorinated rubber (CYTOP) or polyvinyl alcohol (PVA), and is not particularly limited.

As shown in FIG. 2C, the substrate 10 is slowly moved at a fixed speed, that is, the substrate 10 is slowly raised, leaving the substrate 10 away from the carrier 30 until the conductor layer 12 completely leaves the fluid cladding material 20. The surface. During the ascending process of the substrate 10, the fluid coating material 20' is diffused to the top and side surfaces of the conductor layer 12 by the surface tension of the fluid cladding material 20. The conductor layer 12 is coated and diffused onto a portion of the surface of the channel 110.

In this embodiment, due to the surface tension of the fluid covering material 20 and the siphon phenomenon between the fluid covering material 20 and the insulating layer 11, the fluid covering material 20' is caused to cause capillary phenomenon and is drilled. The conductor layer 12 is further covered in the channel 110 of the insulating layer 11.

Moreover, the concentration of the fluid cladding material 20 and the velocity (i.e., the rate of rise) of the substrate 10 away from the carrier 30 affect the layout area of the surface of the conductor layer 12 covered by the fluid cladding material 20'. Specifically, after the conductive layer 12 contacts the surface of the fluid covering material 20, a contact angle is formed between the fluid covering material 20 and the conductor layer 12. The fluid covering material 20' of the embodiment is larger. The contact angle will remain on the surface of the channel 110 near the conductor layer 12.

Moreover, the fixed speed means that the speed is maintained and the direction of movement is not changed.

As shown in Figures 2D to 2E, the carrier member 30 and the fluid cladding material 20 therein are removed such that the fluid cladding material 20' remaining on the conductor layer 12 and a portion of the surface of the channel 110 serves as the Coating layer 13. Thereafter, the cladding layer 13 is re-cured (e.g., baked).

In this embodiment, the fluid-based coating material 20 coating on the conductive layer 12 is irradiated with a light source 40 of ultraviolet light in a nitrogen (N ₂₎ Environment ', crosslinking reaction to generate light. The ultraviolet light 40 may specifically be a power of 30 mW and an ultraviolet light having a wavelength of 257.9 nm, but the present invention is not limited thereto. Therefore, the fluid coating material 20' covering the conductor layer 12 will solidify to form the cladding layer 13 after the photocrosslinking reaction is generated.

As shown in FIG. 2F, a semiconductor layer 14 is formed to cover the insulating layer 11 and the cladding layer 13, and an emitter layer 15 is formed on the semiconductor layer 14.

3A to 3E are schematic cross-sectional views showing a second embodiment of the method for fabricating the transistor of the present invention. In this embodiment, it is determined whether the coating layer formed by photocrosslinking is to be extended to the surface of the substrate or the insulating layer by controlling the concentration of the fluid coating material and the rising speed of the substrate.

As shown in FIG. 3A, a substrate 10 is provided. The substrate 10 is formed with an insulating layer 11 having a plurality of channels 110 for exposing the substrate 10, and a conductor layer 12 is formed on the insulating layer 11. .

As shown in FIG. 3B, the substrate 10 is inverted downward so that the conductor layer 12 is vertically immersed in the fluid cladding material 50 such that the conductor layer 12 is in horizontal contact with the surface of the fluid cladding material 50. It should be noted that the conductor layer 12 may not be entirely immersed in the fluid cladding material 50, and only the conductor layer 12 needs to be slightly contacted to the surface of the fluid cladding material 50.

In the present embodiment, the concentration of the fluid coating material 50 is different from the concentration of the fluid coating material 20 of the first embodiment. Specifically, the concentration of the fluid coating material 50 is such that the contact angle thereof is smaller than the contact angle of the fluid coating material 20 in the first embodiment, that is, the concentration of the fluid coating material 50 of the present embodiment is lower than that of the first embodiment. The concentration of the fluid coating material 20 is exemplified. Thus, the fluid cladding material 50 will flow into the channel 110 due to capillary action and extend to contact the surface of the insulating layer 11 within the channel 110, thereby contacting the exposed surface of the substrate 10.

As shown in FIG. 3C, the substrate 10 is raised at a fixed speed to completely separate the conductor layer 12 from the surface of the fluid cladding material 50. The fluid cladding material 50' will coat the surface of the conductor layer 12, the insulating layer 11 in the channel 110, and the substrate 10.

As shown in Figs. 3D to 3E, as shown in Figs. 2D to 2E, the fluid covering material 50' remaining on the conductor layer 12 and in the channel 110 can be used as the cladding layer 13'.

The film coating method of the coating layer 13, 13' of the present invention is not only controlled by the concentration of the fluid coating materials 20, 50 but also the coating range of the coating layer 13, 13'. The rate of rise of the material 10 is effective to control the coverage of the cladding layers 13, 13'.

The fluid coating material in the foregoing first embodiment is a low concentration solution, and the fluid coating material in the second embodiment is a high concentration solution. Specifically, as shown in FIG. 4, the fluid coating material is a low concentration solution, for example, 1 wt% to 2 wt%. When a low-concentration fluid coating material is used and the rising speed of the substrate is slow, since the adsorbed fluid coating material is small, a stepped structure such as FIG. 3C can be formed. In the case of the same concentration, when the ascending speed of the substrate is faster, there are many cases where the pores of the nano-columnar structure (such as the channel 110) are filled up due to the large amount of the fluid coating material adsorbed. 4 shows a structure with a concentration of 2 wt% and a speed of 0.20 mm/s.

As shown in Fig. 5, the fluid coating material is a high concentration solution, for example, 4 wt% to 5 wt%. When a high-concentration fluid coating material is used and the rate of rise of the substrate is slow, since the adsorbed fluid coating material is small, the tip coating structure as shown in Fig. 2C can be formed. At the same concentration, when the substrate rises faster, the adsorbed fluid coating material is more In many cases, the fluid coating material is easily suspended above the pores of the nano-columnar structure (such as the channel 110), such as the structure shown in FIG. 5 with a rising speed of 0.04 mm/s and a concentration of 4 wt% and 5 wt%. .

In other words, the increase in the rising speed causes the amount of the fluid coating material remaining on the substrate to be larger, and depending on the concentration of the fluid coating material, there is a case where the hole is suspended above the hole and the hole is filled.

In summary, the method of the present invention is modulated according to different concentrations of the fluid coating material and the rising speed of the substrate to obtain different forms of coating.

Furthermore, the technique of stopping the contact of the conductor layer with the surface of the fluid coating material can be used to effectively utilize the siphon phenomenon to uniformly form a film, and the thickness of the film can be raised from several nanometers to several tens of nanometers. Therefore, the method of the invention can complete the coating film operation on the irregular surface, and can overcome the problem that the film thickness is too thin and has no insulation effect, and has the advantages of low cost, simple and rapid production.

In addition, the film forming method of the cladding layer of the present invention can also be applied to an organic semiconductor device process for manufacturing, for example, a vertical space-limited transistor (SCLT), a gas sensing element, an IGZO transistor, and the like. element.

The above embodiments are merely illustrative of the technical principles, features and effects of the present invention, and are not intended to limit the scope of implementation of the present invention. Anyone skilled in the art can implement the above embodiments without departing from the spirit and scope of the present invention. Make modifications and changes. However, any equivalent modifications and changes made using the teachings in this case shall remain in the scope of the patent application below. cover. The scope of protection of this case shall be as listed in the scope of the patent application below.

10‧‧‧Substrate

11‧‧‧Insulation

110‧‧‧ channel

12‧‧‧Conductor layer

20‧‧‧Fluid coating materials

30‧‧‧Carrier

Claims (14)

A method for manufacturing a transistor, comprising: providing a substrate and a carrier, forming an insulating layer on the substrate having a plurality of exposed portions of the substrate, and forming a conductor layer on the insulating layer, and Forming a fluid coating material on a surface of the carrier; placing the substrate on the carrier to contact the fluid coating material; moving the substrate to move the substrate away from the carrier The fluid cladding material is allowed to diffusely coat the conductor layer; and the conductor layer is completely separated from the surface of the fluid cladding material on the carrier such that the fluid cladding material on the conductor layer acts as a cladding layer. The method for producing a transistor according to claim 1, wherein the substrate has a collector layer. The method of fabricating a transistor according to claim 1, wherein the insulating layer is a nanostructure. The method for fabricating a transistor according to claim 1, wherein the channels are connected to each other such that the insulating layer is formed into a structure having a plurality of columns. The method of fabricating a transistor according to claim 1, wherein the conductor layer is a base layer. The method for producing a transistor according to claim 1, wherein the material forming the conductor layer is a metal material. The method for manufacturing a transistor according to the first aspect of the patent application, wherein The fluid coating material is prepared by dissolving polyvinylpyrrolidone powder in deionized water. The method for producing a transistor according to claim 7, wherein the fluid coating material has a concentration of 1 to 5 wt%. The method of manufacturing a transistor according to claim 1, wherein a concentration of the fluid coating material and a velocity of the substrate away from the carrier are used to control a surface of the conductor layer covering the conductor layer. area. The method for manufacturing a transistor according to claim 1, wherein the coating layer is cured after the conductor layer completely leaves the surface of the fluid cladding material. The method for producing a transistor according to claim 1, wherein the material forming the coating layer is an insulating material. The method of fabricating a transistor according to claim 1, wherein the cladding layer extends over the surface of the channel. The method for fabricating a transistor according to claim 1, further comprising forming a semiconductor layer to cover the insulating layer and the cladding layer. The method of fabricating a transistor according to claim 13 further comprising forming an emitter layer on the semiconductor layer.