TWI531069B - Transistor and manufacturing method thereof - Google Patents

Description

Transistor and its preparation method

This invention relates to a transistor, and more particularly to a space charge limited transistor and a method of making same.

The structure concept and operation principle of Space-Charge-Limited Transistor (SCLT) are similar to vacuum triodes. The emitter (Emitter) corresponds to the heated cathode in the vacuum tube as the carrier injection end; the collector corresponds to the anode metal plate, and is responsible for collecting the carrier from the passage to the passage, and the base corresponds to the grid. (grid), acting as a switch that controls the current in the channel; the vacuum layer corresponds to the semiconductor transport layer of the carrier.

The SCLT is actuated by an output current of up to 50 mA/cm ² when the SCLT is turned on, and the current density can drive an active-matrix organic light-emitting diode (AMOLED). However, when the SCLT is off, it will generate a leakage current of 10 ^-3 ~ 10 ^-4 .

Therefore, how to overcome the above problems has become a problem that is currently being solved.

Accordingly, the present invention provides a transistor comprising: a substrate; an insulating layer formed on the substrate, the insulating layer having a plurality of recesses exposing the substrate; and a conductor layer formed on the insulating layer; A coating layer covers the conductor layer.

The invention provides a method for fabricating a crystal, comprising: providing a substrate having an insulating layer formed thereon, the insulating layer having a plurality of recesses exposing the substrate, and a conductor layer formed on the insulating layer; A cladding layer is formed on the conductor layer to coat the conductor layer.

In the above transistor and method of manufacturing the same, the substrate has a collector layer.

In the above transistor and the method of manufacturing the same, the insulating layer is a nanostructure, and the recesses are in communication with each other such that the insulating layer forms a structure having a plurality of pillars.

In the above-described transistor and its manufacturing method, the conductor layer is a base layer, and for example, the material of the conductor layer is a metal material.

In the above-mentioned transistor and its manufacturing method, the material of the coating layer is an insulating material, and the coating layer is extended to the surface of the concave portion.

In the foregoing transistor and method of fabricating the same, the semiconductor layer is covered to cover the insulating layer and the cladding layer, and includes forming an emitter layer on the semiconductor layer.

It can be seen from the above that the transistor of the present invention and the method for fabricating the same are coated with a cladding layer to overcome the problem of leakage current in the prior art.

1‧‧‧Optoelectronics

10‧‧‧Substrate

100‧‧‧ glass plate

101‧‧‧ Collector

11‧‧‧Insulation

11’‧‧‧Cylinder

110‧‧‧ recess

12‧‧‧Conductor layer

120‧‧‧opening

13‧‧‧Cladding

14‧‧‧Semiconductor layer

15‧‧ ‧ emitter layer

23, 33, 53‧‧‧ Covering materials

25‧‧‧ UV

30, 40‧‧‧ Carrying parts

300‧‧‧ bonding layer

43‧‧‧Fluid coating materials

50‧‧‧Barrier

1a is a schematic cross-sectional view of a transistor of the present invention; FIG. 1b is a partial cross-sectional perspective view of the transistor of the present invention; and FIGS. 2a to 2d are first embodiment of a method for fabricating the transistor of the present invention; A cross-sectional view of an example; wherein, the 2c' figure is another mode of the 2c figure; and the 3a to 3c are a schematic cross-sectional view of the second embodiment of the method for fabricating the transistor of the present invention; 4a to 4d are diagrams A cross-sectional view showing a third embodiment of the method for fabricating the transistor of the present invention; and Figs. 5a to 5c are schematic cross-sectional views showing a fourth embodiment of the method for fabricating the transistor of the present invention.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "lower", "inside", "top" and "one" are used in this description for convenience of description and are not intended to limit the invention. The scope, the change or adjustment of the relative relationship, is also considered to be within the scope of the invention.

Figures 1a and 1b are schematic views of the transistor of the present invention. As shown in Figures 1a and 1b, the transistor 1 comprises a substrate 10 formed on An insulating layer 11 on the substrate 10, a conductor layer 12 formed on the insulating layer 11, a cladding layer 13 covering the conductor layer 12, and a semiconductor layer covering the insulating layer 11 and the cladding layer 13. 14. An emitter layer 15 disposed on the semiconductor layer 14.

The substrate 10 has a glass plate 100 and a collector layer 101 such as an indium tin oxide material (ITO) provided on the glass plate 100.

The insulating layer 11 has a plurality of recesses 110 exposing the substrate (such as the collector layer 101), and each of the recesses 110 has a nanometer size, so that the insulating layer 11 has a nanostructure. When the nanostructure is fabricated, if the recesses 110 are in communication with each other, the insulating layer 11 will form a structure having a plurality of nano-pillars 11', as shown in FIG. 1a; if the recesses 110 are not connected, the insulation Layer 11 will form the structure as shown in Figure 1b.

The conductor layer 12 is a base layer and is applied to the top surface of the insulating layer 11, and has a plurality of openings 120 corresponding to the recesses 110, so that the conductor layer 12 has a mesh shape. In this embodiment, the material of the conductor layer 12 is a metal material such as aluminum.

The cladding layer 13 extends to a portion of the surface of the recess 110 to optimize the effect of preventing leakage current of the transistor 1, but does not extend to the surface of the substrate 10. In this embodiment, the material of the coating layer 13 is an insulating material, for example, polyethylene tetrahydrofuranone (PVP), fluorinated rubber (CYTOP), polyvinyl alcohol (PVA), cerium oxide (SiO). Or aluminum oxide (Al ₂ O ₃ ) or the like, but is not limited thereto.

The material of the semiconductor layer 14 is an organic material, such as poly(3-hexylthiophene-2,5-diyl) (abbreviated as P3HT).

The material of the emitter layer 15 is aluminum or aluminum coated with molybdenum trioxide (MoO ₃ ).

In the transistor 1 of the present invention, when the conductor layer 12 is covered by the insulating material, the energy barrier between the conductor layer 12 and the semiconductor layer 14 becomes high, that is, the leakage current can be reduced.

Therefore, the covering layer 13 covers only the top surface of the conductor layer 12 to prevent leakage current. Preferably, the cladding layer 13 covers the top surface and the side surface of the conductor layer 12 to enhance the effect of preventing leakage current. More preferably, the cladding layer 13 extends to the side of the insulating layer 11, and the effect of preventing leakage current is further enhanced.

The process of the cladding layer 13 will be described below by the first to fourth embodiments.

2a to 2d are schematic cross-sectional views showing a first embodiment of the method for fabricating the transistor 1 of the present invention. In this embodiment, the cladding layer 13 is formed by a light process.

As shown in FIG. 2a, a substrate 10 is provided. The substrate 10 is formed with an insulating layer 11 having a plurality of recesses 110 for exposing the substrate 10, and a conductor layer 12 is formed on the insulating layer 11. .

As shown in FIG. 2b, a cladding material 23 is formed on the surface of the conductor layer 12 and the recess 110 of the insulating layer 11.

In the embodiment, the coating material 23 may be formed by spin coating, embossing, dip coating or blade coating.

Furthermore, during the coating process, a portion of the cladding material 23 is deposited on the surface of the substrate 10 along the recess 110.

As shown in Figure 2c, using a light source such as ultraviolet (UV) 25 from the top to the top The cladding material 23 on the upper portion (i.e., on and around the conductor layer 12) is irradiated to generate a photocrosslinking reaction.

As shown in Fig. 2d, since the coating material 23 of the lower portion (i.e., located inside the concave portion 110) is not exposed to the ultraviolet rays 25, the photocrosslinking reaction cannot be caused, so after the completion of the ultraviolet ray 25 irradiation, the concave portion is treated with a solvent. The coating material 23 in which no photocrosslinking reaction is formed in 110 is removed, and the coating material 23 deposited on the surface of the substrate 10 can be removed together, so that the upper cladding material 23 is used as the cladding layer 13 .

Furthermore, in another embodiment, as shown in FIG. 2c', the ultraviolet light 25 may be irradiated from the bottom to the top, that is, irradiated from the bottom of the substrate 10 so as to be deposited on the surface of the substrate 10 and located in the recess 110. The photocracking reaction is produced by the inner cladding material 23. Thereafter, a solvent is injected into the recess 110 to remove the photo-cracking cladding material 23, and the cladding material 23 on and around the conductor layer 12 is used as the cladding layer 13.

3a to 3c are schematic cross-sectional views showing a second embodiment of the method for fabricating the transistor 1 of the present invention. In this embodiment, the cladding layer 13 is formed by a press-bonding process.

As shown in Fig. 3a, a carrier member 30 is provided, on the surface of which a cladding material 33 is formed. In this embodiment, the carrier 30 is a glass plate and has a bonding layer 300 having a thickness of 120 nm and a concentration of 1:1, such as a silicone film (such as PDMS) or a fluorinated rubber (such as CYTOP). The coating material 33 is spin-coated on the bonding layer 300.

As shown in FIG. 3b, the carrier 30 is uniformly applied with a pressure of 50 to 100 kPa for 1000 seconds, so that the carrier 30 is pressed by the covering material 33. On the substrate 10, the covering material 33 is coated with the conductor layer 12.

As shown in FIG. 3c, the carrier 30, the bonding layer 300 and a portion of the cladding material 33 are removed, so that a portion of the cladding material 33 remains on the conductor layer 12 as the cladding layer 13. Thereafter, the coating layer 13 may be baked at a temperature of 200 ° C for 1 hour. The thickness and concentration ratio of the bonding layer 300, the applied pressure, and the baking temperature and time can be adjusted according to requirements, and are not limited thereto.

4a to 4d are schematic cross-sectional views showing a third embodiment of the method for fabricating the transistor 1 of the present invention. In this embodiment, the cladding layer 13 is formed by a wet film process.

As shown in FIG. 4a, a carrier 40 such as a glass plate is provided, and a surface such as polyethylene tetrahydrofuran (PVP), polystyrene (PS), or fluorinated rubber (CYTOP) is formed on the surface of the carrier 40. Or a wet film having a thickness of about 10 ^-6 m (i.e., the fluid covering material 43) is prepared as a mixture of polyethylene tetrahydrofuranone and polymethyl methacrylate (PVP co PMMA).

As shown in FIG. 4b, the substrate 10 is located above the fluid cladding material 43 and the conductor layer 12 is embedded in the fluid cladding material 43 such that the conductor layer 12 and the insulating layer 11 are located in the fluid cladding material. 43.

As shown in FIG. 4c, the carrier 40 is heated (eg, baked) to dry the fluid cladding material 43 such that the fluid coating material 43 gradually decreases in height due to heat, and only the conductor layer is removed. The fluid covering material 43 having a thickness of about 50 nm is formed on a portion of the surface of the concave portion 110.

As shown in FIG. 4d, the carrier member 40 and the fluid covering material 43 thereon are removed to leave a portion of the conductor layer 12 and the recess 110 The fluid coating material 43 on the surface serves as the cladding layer 13. Thereafter, the cladding layer 13 is re-cured (e.g., baked).

5a to 5c are schematic cross-sectional views showing a fifth embodiment of the method for fabricating the transistor 1 of the present invention. In this embodiment, the cladding layer 13 is formed by a resist layer process.

As shown in FIG. 5a, a cladding material 53 is formed on the surface of the conductor layer 12 and the recess 110 of the insulating layer 11.

In the embodiment, the coating material 53 may be formed by spin coating, embossing, dip coating or blade coating.

Further, during the coating process, a portion of the cladding material 53 is deposited on the surface of the substrate 10 along the recess 110.

As shown in Fig. 5b, a barrier 50 is formed on a portion of the cladding material 53.

In the present embodiment, the covering material 53 such as a cerium oxide (SiO) material is coated on the upper portion (i.e., on and around the conductor layer 12) by oblique vapor deposition.

As shown in Fig. 5c, the covering material 53 on which the barrier 50 is not formed is removed.

In the present embodiment, the coating material 53 located on the surface of the substrate 10 and located inside the recess 110 is removed by plasma dry etching. The plasma dry etching process utilizes particles in the plasma to collide with the cladding material 53 to achieve the purpose of removing the cladding material 53. Again, the barrier 50 can be selectively removed or removed.

In each of the above embodiments, the coating material is formed by coating or dip coating. The material is not only simple in process, but also low in production cost, so that it is not necessary to use an atomic layer deposition process with high production cost.

The above embodiments are merely illustrative of the effects of the present invention and are not intended to limit the present invention, and those skilled in the art can practice the above embodiments without departing from the spirit and scope of the present invention. Make modifications and changes. In addition, the number of elements in the above-described embodiments is merely illustrative and is not intended to limit the present invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

1‧‧‧Optoelectronics

10‧‧‧Substrate

100‧‧‧ glass plate

101‧‧‧ Collector

11‧‧‧Insulation

11’‧‧‧Cylinder

110‧‧‧ recess

12‧‧‧Conductor layer

120‧‧‧opening

13‧‧‧Cladding

14‧‧‧Semiconductor layer

15‧‧ ‧ emitter layer

Claims (24)

An electro-crystal comprising: a substrate; an insulating layer formed on the substrate, wherein the insulating layer has a plurality of recesses exposing the substrate; a conductor layer formed on the insulating layer; and a cladding layer The conductor layer, wherein the cladding layer extends onto a surface of the recess. The transistor of claim 1, wherein the substrate has a collector layer. The transistor of claim 1, wherein the insulating layer is a nanostructure. The transistor of claim 1, wherein the recesses are in communication with each other such that the insulating layer forms a structure having a plurality of columns. The transistor of claim 1, wherein the conductor layer is a base layer. The transistor according to claim 1, wherein the material of the conductor layer is a metal material. The transistor according to claim 1, wherein the material of the coating layer is an insulating material. The transistor according to claim 1, further comprising a semiconductor layer covering the insulating layer and the cladding layer. The transistor of claim 8, wherein the transistor comprises an emitter layer disposed on the semiconductor layer. A method for fabricating a crystal, comprising: providing a substrate having an insulating layer formed thereon, the insulating layer having a plurality of recesses exposing the substrate, and a conductor layer formed on the insulating layer; and forming a cladding layer The conductor layer is coated on the conductor layer, wherein the cladding layer extends onto the surface of the recess. The method for producing a transistor according to claim 10, wherein the substrate has a collector layer. The method of fabricating a transistor according to claim 10, wherein the insulating layer is a nanostructure. The method of fabricating a transistor according to claim 10, wherein the recesses are in communication with each other such that the insulating layer forms a structure having a plurality of columns. The method of fabricating a transistor according to claim 10, wherein the conductor layer is a base layer. The method for fabricating a transistor according to claim 10, wherein the material of the conductor layer is a metal material. The method for producing a transistor according to claim 10, wherein the material of the coating layer is an insulating material. The method of fabricating a transistor according to claim 10, further comprising forming a semiconductor layer to cover the insulating layer and the cladding layer. The method of fabricating a transistor according to claim 17, further comprising forming an emitter layer on the semiconductor layer. The method for manufacturing a transistor according to claim 10, wherein The process of the cladding layer includes: forming a cladding material on the conductor layer and the insulating layer; illuminating the cladding material; and removing a portion of the cladding material to leave the cladding material as the cladding layer . The method of producing a transistor according to claim 19, wherein the coating material on and around the conductor layer generates a photocrosslinking reaction when the cladding material is illuminated. The method of fabricating a transistor according to claim 19, wherein the coating material on the surface of the recess generates a photocleavage reaction when the coating is illuminated. The method for manufacturing a transistor according to claim 10, wherein the process of the cladding layer comprises: providing a carrier member, the surface of the carrier member is formed with a coating material; the carrier member is coated with the coating material A material is pressed against the substrate such that the cladding material coats the conductor layer; and the carrier is removed such that the cladding material acts as the cladding layer. The method for manufacturing a transistor according to claim 10, wherein the process of the cladding layer comprises: providing a carrier member having a fluid coating material formed on a surface thereof; the substrate is a conductor The layer is embedded in the liquid insulating material such that the conductor layer and the insulating layer are located in the fluid cladding material; The carrier is heated to reduce the height of the fluid cladding material; and the carrier is removed such that the retained fluid cladding material remains as the coating. The method for manufacturing a transistor according to claim 10, wherein the process of the cladding layer comprises: forming a cladding material on the conductor layer and the insulating layer; forming a barrier body on a portion of the cladding material And removing the covering material on which the barrier body is not formed.