TWI537730B - Methods and systems for managing synonyms in virtually indexed physically tagged caches - Google Patents

Description

Method and system for managing synonym in virtual index entity tag cache

The present invention is generally directed to a method and system for managing synonyms in a virtual index entity tag cache.

The cache in the central processing unit is a data storage structure that is used by the central processing unit of the computer to reduce the average time it takes to access the memory. The cache is a memory that stores a copy of the data, which is located at the most commonly used main memory location. In addition, the cache memory is smaller than the main memory and the access is faster. There are several different types of caches, including Entity Index Entity Tags (PIPTs), Virtual Index Virtual Tags (VIVTs), and Virtual Index Entity Tags (VIPTs).

VIPT caches are typically used in modern processing applications. These caches use a virtual address (VA) for the index (which identifies a unique location in the cache) and a physical location in the tag (which contains the primary memory index of the cached data). It is related to the cache line. With this type of cache, the cache line can be identified in parallel using TLB translation, as shown in Figure 1. Referring to Figure 1, the VIPT cache uses a virtual address bit 101 (e.g., untranslated virtual address bit) to begin a tag read to index to the cache 103, while the memory management unit (MMU) 105 will place the virtual address. Some higher order bits are translated into physical address bits 107. Next, the physical address bit 107 is compared to the tag value of the VIPT associated with the cache line. Therefore, the VIPT cache can hide its access time by overlapping its tag reader with the MMU translator.

Consider a 64KB, 8-way correlation level 1 VIPT cache. In addition, assume a minimum MMU page size of 4 KB, a virtual address (VA) of 32 b long, and a physical address (PA) of 40 b long. Based on the foregoing procedure, the VIPT cache is indexed to the tag SRAM (not shown) using VA[12:6] (bits of the virtual address [12:6]). The 8-way generates TagPA[39:12] (associated with the physical address of the untranslated virtual address presented to the Tag SRAM). Although the VIPT cache is busy accessing its Tag SRAM, the MMU translates VA[31:12] (bit twelve) to produce the MMU PA[39:12] (the physical address generated by the translation). MMU PA [39:12] is compared to TagPA [39:12] to generate TagHit[7:0], which identifies the way in the 8-way with the VIPT cache of the cache line. In the above, VA[12] is used to index to tag dynamic random access memory (Tag DRAM), and VA[12] is translated to generate PA [12]. A virtual address bit index cache that is translated into a physical address can generate a synonym.

Consider the following results:

VA0[31:13]=0×0, VA0[12]=0×0, VA0[11:0]=0×0-->(translation)-->PA[39:0]=0×0

VA1[31:13]=0×1, VA1[12]=0×1, VA1[11:0]=0×0-->(translation)-->PA[39:0]=0×0

In the above, VA0 and VA1 (which differ in the 12th bit) produce the same PA[39:0] when translated by the MMU. When VA0 accesses the VIPT cache using VA[12:6] (VA[12:6]=0000000), it accesses the index 0 of the Tag SRAM (not shown). In addition, when VA1 accesses the VIPT cache using VA[12:6] (VA[12:6]=0000001), it accesses the index 64 of the Tag SRAM. Thus, the same physical address is associated with VA1 and VA2, and it resides in both index 0 and index 64 of the VIPT cache. The two virtual addresses VA1 and VA2 mapped to the same physical address of the main memory are referred to as "synonyms". The same physical address associated with two (or more) items in a VIPT cache is called "aliasing."

Confusion occurs when the size of the "a way" of the VIPT cache exceeds the minimum memory page size. The unresolved issue is that confusion can lead to inconsistencies in the data. When a level 1 (or L1) cache is included in a level 2 (or L2) cache (the rest of the L1 cache is maintained in the L2 cache), the conventional method of handling confusion is to store synonyms. The word VA bit (VA[12] in the above example) is in the L2 cached tag. A disadvantage of this approach is that each L2 tag index requires a storage bit (such as VA[12]) and additional bits are needed to identify each synonym. Thus, a disadvantage of the conventional method is that it results in a two-dimensional growth of the storage in the L2 cache, which corresponds to an increase in the size of the L2 cache and an increase in the number of synonyms included therein. Moreover, in the conventional system, when the material related to the physical address mapped to the virtual address synonym is updated, only one of the caches can be updated. In order to avoid inconsistencies in data that may result in such incomplete updates, many conventional systems perform time consuming searches of cached content to ensure the invalidation of all virtual address synonym associated with updated physical addresses. Therefore, the conventional method of managing synonyms has considerable disadvantages due to its complicated data storage and cache search operations.

Many of the well-known methods for handling synonyms in the VIPT cache feature cumbersome data storage and cache search operations. Disclosed is a directory-based approach that uses partitioning into one of the different parts of the directory to handle these shortcomings. However, the specific embodiments claimed are not limited to the implementation of any or all of the disadvantages described above. Part of the disclosed method is to use a directory to track a replica cache line; to check a particular bit associated with a virtual address of a load request and determine its status; and based on the particular bit of the virtual address being examined The state of the meta-form forms one of a plurality of parts of the catalog. Upon receiving a request to update an entity address associated with one of the virtual addresses, a cache line associated with the virtual address stored in the first index of the copy cache, and stored in the copy One of the cache lines associated with a synonym of the virtual address in the second index of the cache is invalidated. Because of the single directory involved, updates and failures of the cache line corresponding to the synonym (which is stored in the replica cache and related to the directory entry) can be effectively executed in a single clock cycle without time-consuming cache search.

The foregoing is a summary of the invention, and thus is inclusive of Therefore, it is to be understood that the invention may be Other aspects, features, and advantages of the invention will be set forth in the description of the appended claims.

Although the present invention has been described in terms of a specific embodiment, the invention is not intended to be limited to the specific forms disclosed herein. On the contrary, the invention is intended to cover such alternatives, modifications and equivalents

In the following detailed description, numerous specific details are set forth, such as the particular method of the embodiments, It should be understood, however, that the specific embodiments of the invention may be practiced In other instances, well-known structures, components, or connections are omitted or not described in detail to avoid unnecessarily obscuring the description.

The phrase "one embodiment" or "an embodiment" is used in the specification to mean that a particular feature, structure, or characteristic described in connection with a particular embodiment is included in the present invention. A specific embodiment of at least one embodiment of the invention. The word "in a particular embodiment" is used in many places in the specification and is not intended to refer to the specific embodiments. In addition, many of the features described may be presented in some specific embodiments and not in other specific embodiments. Similarly, many of the needs described may be desirable for certain embodiments, but are not required by other specific embodiments.

Portions of the detailed description are set forth below in terms of procedures, steps, logic blocks, processing, and other symbols that operate on the data bits in the computer memory. These descriptions and representations are the means used by those skilled in the art to best convey the substance of their work to those skilled in the art. Programs, computer-executed steps, logic blocks, processes, and the like are here and in general are contemplated as steps or instructions that result in a consistent sequence of desired results. These steps are operations for entities that require a physical quantity. Typically, but not necessarily, these quantities are in the form of electrical or magnetic signals of a computer readable storage medium and can be stored, transferred, combined, compared, or manipulated in a computer system. It has been proven that sometimes (primarily for normal use) such signals are referred to as bits, values, elements, symbols, characters, terms, numbers or the like.

However, it should be noted that all of these or similar terms are related to the appropriate amount of the entity and are merely convenient symbols applied to these quantities. In the following discussion, unless otherwise specified, it is to be understood that terms such as "tracking", "examining", "making", "updating", or the like are used in the present invention. Discussion refers to the actions and procedures of a computer system or similar electronic computing device that manipulates and converts data in a computer system register and memory and other computer readable media into physical (electronic) quantities into a computer system. Memory or scratchpad or other such information storage, transmission, or display device is similarly represented as other quantities of material.

<Example Operating Environment for a System for Managing Synonyms in Virtual Index Entity Tag Cache in accordance with a Specific Embodiment>

2A shows an example operating environment 200 of a system 201 for managing synonyms in a virtual index entity tag (VIPT) cache, in accordance with an embodiment. System 201 enables individual updates and invalidation of individual cache line items associated with a physical address and corresponding synonym in a single clock cycle. 2A shows system 201, L1 cache 203, replica cache 205 (and directory 206), L2 cache 207, central processing unit (CPU) 209, main memory 211, and system interface 213.

Referring to FIG. 2A, the system 201 manages synonym growth in the cache memory by effectively updating and invalidating the cache line item corresponding to the synonym, wherein the synonym is corresponding to one of the physical addresses associated with an update request. In one embodiment, the system 201 supported by the catalog 206 is capable of directly identifying synonyms, which correspond to one of the physical addresses associated with the update request, without exhaustive and time consuming searching of the cached content. In a specific embodiment, system 201 can be located in L2 cache 207, such as L2 cache controller 207b. In other embodiments, system 201 can be separate from the L2 cached component (e.g., L2 cache controller 207b), but operates in conjunction therewith. In an exemplary embodiment, system 201 indicates an expiration failure of one or more cache line items corresponding to a synonym, which is by a line of one of the equivalent words in the update associated with the selection for updating The project indicates its failure in the same clock cycle. In a specific embodiment, this is assisted by the configuration of the directory 206, which tracks the copy content (replica cache 205) of the L1 cache 203 maintained by the L2 cache 207. In one embodiment, as shown in FIG. 1, the L1 cache 203 is located in the central processing unit 209 and the directory 206 is located in the L2 cache 207.

Directory 206 is configured to maintain items stored in each cache line of replica cache 205 (e.g., replica L1 data and/or instruction cache). The project is maintained in a manner that facilitates direct identification of synonyms, which is related to the cache line corresponding to the physical address associated with an update request. To this end, as shown in FIG. 2B, the directory 206 is divided into a first board 0 206a and a second board 1 206b based on a "synonym VA" bit associated with the access request. Referring to Figure 2B, the individual boards (206a and 206b) correspond to individual virtual address ranges. In a specific embodiment, the synonym VA bit identifies the virtual address range to which the virtual address of a synonym belongs. Therefore, the synonym VA bit determines the directory in which the directory entry corresponding to the cache line stored in the replica cache 205 is maintained. Since both boards are part of the same directory, the update and invalidation of the cache line stored in the replica cache 205 associated with the directory 206 item can be performed in a single clock cycle without having to exhaust and exhaust the cache. Time to search.

In the particular embodiment of FIG. 2B, the catalog 206 is configured to include 128 lines (shown as 0-127 of FIG. 2B) that track the lines stored in the replica cache 205. In this particular embodiment, lines 0-63 are included in board 0 206a and correspond to a first range of virtual addresses VA[12] = 0, lines 64-127 are included in board 1 206b and corresponding virtual addresses The second range of VA[12]=1. In addition, each line includes a location 206c (e.g., indicated by a one-bit) that can indicate the validity or non-validity of the line.

Referring again to FIG. 2A, in one embodiment, a load request containing a synonym to the L2 cache 207 is via the L2 cache 207 pipeline (the pipeline of requests received by the L2 cache 207, eg, for a request One of the L1 caches 203 missed) and received. Then, when the load request is executed and the cache line included in the load request is stored in the replica cache 205, the synonym VA bit associated with the request is used to update the appropriate directory panel to Indicates that the cache line has been stored in the replica cache 205. For example, in one embodiment, if a load request for a physical address (PA) is received at L2 cache 207 with VA = VA0 = 0, then board 0 206a is updated (see Figure 2B). However, if the load request for the physical address (PA) is received by the L2 cache 207 with VA = VA1 = 1, the board 1 206b is updated (refer to Figure 2B).

It should be understood that after performing the above operations, since VA0 and VA1 are synonymous, both VA0 and VA1 are associated with the same physical address (PA). Furthermore, the data associated with this physical address (PA) is then resident in two different indices, 0 and 64, in the replica cache 205. Then, when an update request (such as storage) to update the physical address (PA) is received via the L2 cache, the system 201 randomly selects one of the two cache line items associated with the physical address (PA). For updates, and one of them for failure. Thus, in one embodiment, a cache line associated with a physical address (PA) (which is associated with VA0 and VA1) is allowed to reside in two different indexes in the replica cache 205 until one includes Update the storage request for this specific entity address (PA). Similarly, the performance advantages obtained by maintaining two copies of the cache line in the Replica 205 can be achieved.

The L1 cache 203 is a level 1 cache, and the L2 cache 207 is a level 2 cache. In one embodiment, the size of the L2 cache 207 is much larger than the L1 cache 203. In one embodiment, when there is a level 1 cache miss, a request will be provided to level 2 cache L2, which checks directory 206 to determine if the requested information resides in replica cache 205.

The main memory 211 includes a physical address that stores information copied to the cache memory. When the information contained in the physical address of the cached main memory changes, the corresponding cache information is updated to reflect the changes made to the information stored in the main memory. Thus, as discussed above, this may involve the system 201 randomly selecting a cache line item associated with the physical address of the update request to update, and another cache line item associated with the physical address to expire. . Other structures shown in FIG. 2A include a system interface 211, a tag random access memory (tag RAM) 207c, and an L2 cache static random access memory (SRAM) 207a.

2C shows a schematic diagram of the relationship between selected cache system blocks in accordance with an embodiment. Referring to FIG. 2C, the request received via the L2 pipeline 213 to update the cache line in the replica cache 205 (which corresponds to a synonym associated with one of the physical addresses) facilitates review of the directory 206. The review of the catalog 206 identifies the cache line items stored in the replica cache 205 associated with the physical address. As discussed above, system 201 then randomly selects one of the cache line items for update and the other for failure. Thus, after an update request associated with the physical address, only a single cache line of one of the corresponding physical addresses remains in the replica cache 205. Moreover, there is no synonym associated with the physical address in the replica cache 205 just after the above update and invalidation operations.

<operation>

2D and 2E depict an operational aspect of system 201 for managing synonyms in a VIPT, in accordance with an embodiment. These operations on managing synonyms are described in a clear and concise manner. It should be appreciated that other operations not illustrated in Figures 2D and 2E may also be performed in accordance with a particular embodiment. In FIG. 2D, the operation will be described with reference to a diagram of a series of states of the replica cache 205 corresponding to the L2 cache 207 (refer to FIG. 2A).

<implicit processing of synonymous words>

Referring to FIG. 2D, at A, index 0 and index 64 of replica cache 205 are shown as invalid. This can happen, for example, after resetting.

At B, the cache line item is stored in index 0 of the replica cache 205 based on the data storage request. In a specific embodiment, the cache line item includes a valid bit, a tag (such as a virtual address and a physical address), and a data block.

At C, the cache line stored at index 0 is loaded into index 64. In a specific embodiment, this may occur when a subsequent request to store data related to a physical address (which is related to a cache line stored at index 0) is related to being stored in the index. 0 is the synonym of the virtual address of the line. The result is that the physical address is associated with the cache line stored in both index 0 and index 64.

At D, the cache line item at index 0 is updated with a new data value, and the cache line item at index 64 is invalidated. In a specific embodiment, when one of the items is selected to update it, the other will fail. As described herein, when a request is made to update one of the items, one of the two items will be randomly selected for update and the other will be invalid.

In a specific embodiment, the implicit processing of the synonym described above uses a directory structure (which is used to ensure that the replica cache 205 is included in the L2 cache 207) to resolve the replica cache 205 (FIG. 2A). Confusing the problem. This is depicted in Figure 2D. This solution allows the replica cache 205 (Fig. 2A) to have the same physical address associated with the two entries in the replica cache 205 (Fig. 2A) as long as the physical address does not need to be updated with the new value. When it is time to update the physical address with a new value, the cache line item associated with the physical address in an index will be invalidated (which randomly selects between two possible items in the replica cache 205). ).

<predictor type processing of synonymous words>

Figure 2E depicts an operation performed in accordance with an embodiment as part of a predictive processing of synonyms. Consider two virtual addresses VA0 and VA1 from different programs that meet the following conditions: VA0[12:6] is the same as VA1[12:6], and PA0[12] is not the same as PA1[12]. In addition, VA1[12] is not the same as PA1[12] after translation. If the cache involved is physically indexed and physically tagged (PIPT), or is 32 KB with 8-way association, the two entity addresses will be stored in indices 0 and 64, respectively. However, if a virtual address (which is a VIPT cache) with the same synonym VA (such as 12:6) is used to access the cache, the two entity addresses will end at the same index (such as index 0), which Occupying two different roads here is not desirable for optimal performance. The operation described in Figure 2E will solve this problem.

Referring to FIG. 2E, at A, a virtual address having a bit VA1[12:6] having the same value as the bit VA0[12:6] of the virtual address VA0 previously accessed by the cache is used. VA1 accesses the VIPT cache.

At B, the physical address bit PA[12] for the physical address of the virtual address VA1 is predicted. In a specific embodiment, the prediction can be random. In other embodiments, the prediction may be non-random. For example, in one embodiment, when a cache is accessed, the system (such as system 201 of FIG. 2A) can be randomly selected between logical values 0 and 1 of PA[12].

At C, if the decision is made to be incorrect (if the predicted PA[12] is not the same as the actual PA[12]), then a miss is indicated and the system (201 in Figure 2A) is updated. Including the correct value of PA[12] allows the system to correctly make predictive predictions based on updated information.

At D, the request is retried using the correct value of PA[12].

In a specific embodiment, the predictive processing of the synonym is used to ensure that if the VA[12] access cache is used, the two virtual addresses VA0 and VA1 (which have the above characteristics) do not end in the same index.

<Members of a system for managing synonyms in a virtual index entity tag cache according to a specific embodiment>

Figure 3 shows the components of a system 201 (see also Figure 2A) for managing synonyms in a VIPT cache in accordance with an embodiment. In one embodiment, system 201 performs operations to manage synonyms in a virtual index entity tag (VIPT) cache. In the specific embodiment of FIG. 3, the components of system 201 include a cache line tracker 301, a synonym VA bit checker 303, a directory item former 305, a cache line updater/deasserter 307, and virtual address receiving. The 309, the physical address predictor 311, the prediction correctness determiner 313, and the request retry component 315.

<implicit synonym processing component>

Referring to FIG. 3, the cache line tracker 310 tracks the line in the copy of the level 1 cache, which is maintained in the level 2 cache. In one embodiment, the cache line tracker 310 is a directory configured to maintain an item of each cache line stored in a copy of the level 1 cache, which is adapted to facilitate correspondence of synonyms (This is a way to validate and invalidate the cache line item corresponding to one of the entity addresses of an update request). In a specific embodiment, the directory is divided into a first board and a second board, which correspond to a synonym VA bit associated with one of the requests.

The synonym VA bit checker 303 checks a synonym VA bit associated with the virtual address of the load request and determines its state.

The directory item former 305 forms one of a plurality of parts of the directory based on the state of the synonym VA bit of the checked virtual address. In a specific embodiment, at an index in the replica L1 cache, the directory entry corresponds to the storage of a cache line having an associated physical address.

When receiving an update request to update one of the physical addresses associated with the two virtual addresses, the cache line updater/deasserter 307 updates one of the following and invalidates one of the other: stored in the aforementioned copy cache a cache line in the first index (which is related to the first virtual address) and a cache line stored in the second index of the copy cache (which is related to the second virtual address, where The second virtual address is a synonym for the first virtual address). In a specific embodiment, the cache line for selection is selected and the cache line selected for failure is randomly selected.

<predictor synonym processing component>

The virtual address receiver 309 receives a virtual address as part of an access request to the VIPT, which has a synonym VA bit value that is the same as the virtual address of the previously accessed VIPT cache. In a specific embodiment, the first and second virtual address locations are associated with the first and second programs, respectively.

The physical address bit predictor 311 predicts one of the physical address physical address bits associated with the received virtual address (which is part of the VIPT cache access request). In a specific embodiment, as discussed above, the prediction can be random. In other embodiments, the prediction may be non-random. For example, in one embodiment, as discussed above, when accessing a cache, the system (such as system 201 of FIG. 2A) can be randomly selected between logical values 0 and 1 of PA[12].

The prediction correctness decider 313 determines whether the prediction made by the physical address predictor 311 is correct.

The request retry component 315 causes the correct retry of the request to be made using the correct value of the physical address bit. For example, if the incorrect prediction is logic "0", the request is retried using logic "1".

It will be appreciated that the components of system 201 described above can be implemented as a hardware, a soft body, or a combination of both. In one embodiment, the components and operations of system 201 may be included in the components and operations of one or more computer components or programs. In another embodiment, the components and operations of system 201 can be separate from one or more of the aforementioned computer components or programs but can operate in conjunction with its components and operations.

< A program for managing synonyms in a virtual index entity tag cache according to a specific embodiment >

4 and 5 show flowcharts 400 and 500 of steps performed in a method for managing synonyms in a virtual index entity tag (VIPT) cache, in accordance with an embodiment. In one embodiment, the flowchart includes a program that can be implemented by a processor and an electronic component under the control of computer readable and computer executable instructions. Although specific steps are disclosed in the flowcharts, these steps are illustrative. That is, the present embodiments are suitable for implementing various other steps or variations of the steps recited in the flowcharts.

<implicit synonym management method>

Referring to FIG. 4, at 401, the cache line maintained in the level 1 cache of the level 2 cache is tracked. In a specific embodiment, the lines are tracked in a directory, wherein the directory is configured to maintain an item of each cache line stored in the copy of the level 1 cache, which is adapted to facilitate the corresponding synonym (which A manner of valid update and invalidation of a cache line item corresponding to one of the physical addresses of an update request. In a specific embodiment, the catalog is divided into a first panel and a second panel, as described above.

At 403, a particular bit associated with the virtual address of the load request is checked and its status is determined.

At 405, an item is generated in one of a plurality of portions of the directory based on the status of the particular bit of the virtual address being examined. In a specific embodiment, the directory entry corresponds to the storage of one of the indices in the replica L1 cache.

At 407, when an update request is received to update the physical address associated with the virtual address, one of the following and one of the other are updated and invalidated: one of the first indexes stored in the first cache cache A cache line item of the address and a cache line item associated with its synonym stored in the second index of the copy cache.

<predictor synonym management method>

Referring to FIG. 5, at 501, a virtual address is received as part of an access request to a VIPT having a synonym VA bit value (such as VA) that is the same as the virtual address of the previously accessed VIPT cache. [12]). In a specific embodiment, the foregoing address is associated with the first and second programs, respectively. At 503, a physical address bit (e.g., PA[12]) of the physical address associated with the virtual address (which is part of the VIPT cache access request) is predicted. At 505, it is determined whether the prediction is correct (correctness decision). At 507, if the prediction is incorrect, the request is retried using the correct physical address bit value.

Methods and systems for managing synonyms in a VIPT cache are disclosed with respect to specific examples thereof. The method includes using a directory to track a replica cache line, checking a particular bit associated with a virtual address of a load request and determining its status, and based on the status of the particular bit of the virtual address being examined. Forming an item in one of a plurality of parts of the catalog. The method further includes: when receiving a request to update an entity address associated with one of the virtual addresses, updating one of the following and invalidating one of the following: and storing the first index stored in the copy cache A cache line associated with the virtual address in the virtual address and a cache line associated with a synonym of the virtual address stored in the second index of the copy cache.

While many of the components and procedures have been described above in the singular for convenience, it will be appreciated by those skilled in the art that the various embodiments and various procedures can be used to implement the techniques of the present invention. In addition, the present invention has been particularly shown and described with respect to the specific embodiments thereof, and it will be understood that the form and details of the disclosed embodiments can be made without departing from the spirit and scope of the invention. change. For example, a particular embodiment of the invention may use a variety of different components, and should not limit the components mentioned above. Accordingly, the invention is to be construed as being limited to all such modifications and equivalents

101. . . Virtual address bit

103. . . Cache

105. . . Memory management unit

107. . . Physical address bit

200. . . Operating environment

201. . . system

203. . . L1 cache main memory

205. . . Replica cache

206. . . table of Contents

206a. . . First board

206b. . . Second board

206c. . . position

207. . . L2 cache

207a. . . L2 cache static random access memory

207b. . . L2 cache controller

207c. . . Tag random access memory

209. . . Central processing unit

211. . . Main memory

213. . . System interface

301. . . Cache line tracker

303. . . Synonym VA bit checker

305. . . Directory item builder

307. . . Cache line updater/disabler

309. . . Virtual address receiver

311. . . Physical address predictor

313. . . Predictive correctness determiner

315. . . Request retry component

The invention and its further advantages are best understood by reference to the detailed description and the accompanying drawings in which:

Figure 1 shows components of a conventional system for accessing a virtual index entity tag (VIPT) cache;

2A shows an example operating environment of a system for managing synonyms in a VIPT cache, in accordance with an embodiment;

2B shows a directory divided into a first board and a second board based on a synonym virtual address (VA) bit associated with an access request, in accordance with an embodiment;

2C shows a schematic diagram of the relationship between selected cache system blocks in accordance with an embodiment;

2D depicts an operational aspect of a system for managing synonyms in a VIPT, in accordance with an embodiment;

2E depicts an operational aspect of a system for managing synonyms in a VIPT, in accordance with an embodiment;

3 shows components of a system for managing synonyms in a VIPT cache, in accordance with an embodiment;

4 shows a flow diagram of steps performed in a method for managing synonyms in a VIPT cache, in accordance with an embodiment;

FIG. 5 shows a flow diagram of steps performed in a method for managing synonyms in a VIPT cache, in accordance with an embodiment.

It should be noted that like elements in the drawings refer to like elements.

200. . . Operating environment

201. . . system

203. . . L1 cache main memory

205. . . Replica cache

206. . . table of Contents

207. . . L2 cache

207a. . . L2 cache static random access memory

207b. . . L2 cache controller

207c. . . Tag random access memory

209. . . Central processing unit

211. . . Main memory

213. . . System interface

Claims (20)

A method for managing a synonym in a cache system, comprising: tracking a replica cache line using a directory; checking a specific bit associated with a virtual address of a load request and determining its state; The state of the particular bit of the virtual address being inspected, forming an entry in one of a plurality of portions of the directory; and receiving an entity bit associated with the virtual address when received At the request of the address, updating one of the following and invalidating one of the following: a cache line associated with the virtual address stored in the first index of the copy cache, and stored in the A cache line is a cache line associated with a synonym of the virtual address in the second index. The method of claim 1, wherein the virtual address and the synonym are identified in the directory prior to the invalidation. The method of claim 1, wherein forming the item in the directory comprises placing the item in a first panel and a second board based on the specific bit of the virtual address One. The method of claim 1, wherein the cache line associated with the virtual address stored in the first index of the copy cache and the second index stored in the copy cache The cache line associated with the synonym is residing in the first index and the second index until formation To update a request for the physical address associated with the virtual address. The method of claim 1, wherein the cache line associated with the virtual address stored in a first index of the copy cache and the cache line associated with the synonym are The failure of one is determined randomly. The method of claim 1, further comprising receiving the load request from a level 2 cache pipeline. The method of claim 1, wherein the directory includes a first board and a second board corresponding to the first and second virtual address ranges. The method of claim 1, wherein the copy cache is a copy of a level 1 cache. The method of claim 1, wherein the cache system is a virtual index entity tag (VIPT) system. A method for managing a virtual address synonym in a VIPT, comprising: receiving an access request for the VIPT associated with a first virtual address, the first virtual address having a correlation with a previously received One of the second virtual address of the access request is the same as the VA bit of the synonym VA bit; the prediction is before the actual value of the bit of the physical address is determined a value relating to one of the bits of the physical address of the first virtual address; determining the actual value of the bit of the physical address; if the bit of the physical address is provided in advance The value is not the same as the actual value of the bit of the physical address, providing an indication of a miss and updating a predictor; and retrying the actual value of the bit using the physical address The access request. The method of claim 10, wherein the first virtual address and the second virtual address are related to different programs. The method of claim 10, wherein the different physical address locations are each associated with the first virtual address and the second virtual address. A cache memory system comprising: a memory component; and a memory controller, wherein the memory controller includes a system for managing synonyms, the system comprising: a tracking component that uses a directory tracking a line of replicas; an inspection component that checks a particular bit of a virtual address associated with a load request and determines its state; an item forming component that is based on the particular bit of the virtual address being examined The state of the meta-form forms one of a plurality of parts of the directory; and a cache line update and invalidation component that is received to update the relevant When a request for one of the physical addresses of the virtual address is requested, one of the following is updated and the other of the following is invalidated: a fast associated with the virtual address stored in the first index of one of the replica caches And fetching a line, and a cache line associated with a synonym of the virtual address stored in a second index of the copy cache. The cache memory system of claim 13, wherein the cache line update and invalidation component identifies the virtual address and the synonym in the directory prior to the update and the failure. The cache memory system of claim 13, wherein the item forming means places the item in one of a first board and a second board based on the particular bit of the virtual address. The cache memory system of claim 13, wherein the cache line update and invalidation component allows the cache line associated with the virtual address stored in the first index of the replica cache, and The cache line associated with the synonym stored in the second index of the replica cache resides in the first index and the second index until a physical bit associated with the virtual address is formed to be updated A request for the address. The cache memory system of claim 13, wherein the cache line update and invalidation component randomly determines the cache line associated with the virtual address stored in a first index of the copy cache. And the update of the one of the cache lines associated with the synonym and the failure. The cache memory system of claim 13, wherein the inspection component checks for a load request from a level 2 cache. The cache memory system of claim 13, wherein the copy cache is a copy of a level 1 cache. The cache memory system of claim 13, wherein the cache system is a virtual index entity tag (VIPT) system.