JPWO2013084315A1 - Arithmetic processing device and control method of arithmetic processing device - Google Patents

Abstract

An arithmetic processing apparatus according to one aspect of the present invention is a control target, a plurality of arithmetic processing units including a first cache memory, a second cache memory that holds data calculated by the plurality of arithmetic processing units, respectively. An acquisition unit that acquires attribute information related to the first cache memory of the access request source to be controlled, including way information indicating a way of a cache block of the first cache memory; and a holding unit that holds address information and attribute information The replacement target address included in the access request related to the replacement request issued by one of the plurality of arithmetic processing units with respect to the first cache memory and the way information indicating the way of the cache block to be replaced in the first cache memory. Based on the second address specified by the address information and attribute information to be controlled. And a control unit for controlling the access request according to the replacement request to the cache block of Shumemori, the.

Description

  The present invention relates to an arithmetic processing device and a control method for the arithmetic processing device.

  Conventionally, a cache memory is used to bridge the difference between the execution speed of the processor core and the access speed to the main storage device. Because of the trade-off relationship between access speed and memory capacity, most cache memories are hierarchized into two or more layers. The hierarchical cache memory is referred to as a primary (L1) cache memory, a secondary (L2) cache memory, or the like in order from the processor core. Hereinafter, the processor core is also simply referred to as “core”. The main storage device is also simply referred to as “memory” or “main memory”. The cache memory is also simply referred to as “cache”.

  The data in the main memory is associated with the cache memory in units of blocks. A set associative method is known as a method of associating a cache memory block with a main memory block. Hereinafter, in order to distinguish the main memory block from the cache memory block, the main memory block is particularly referred to as a “memory block”. A block of the cache memory is expressed as “cache block” or “line”.

  The set associative method is a method in which the main memory and the cache memory are divided into several sets, and the main memory and the cache memory are associated with each other in each set. A set is also called a column. In the set associative method, the number of cache blocks that can be accommodated in each set of the cache memory is determined. The number of cache blocks that can be accommodated is called the number of rows, the number of levels, or the number of ways.

  In the set associative method, a cache block is identified by an index and way information. Specifically, a set containing the corresponding cache block is identified by the index. Further, the way information identifies the corresponding cache block among the cache blocks accommodated in the set. The way information is, for example, a way number used for identifying the corresponding cache block.

  For the allocation between the memory block and the cache block, the address of the memory block to be allocated is used. In the set associative method, a memory block to be allocated is allocated to any cache block accommodated in a set indicated by an index that matches a part of the address of the memory block. That is, an index in the cache memory is specified by a part of the address.

  The address used for the assignment may be a physical address (real address) or a logical address (virtual address). A part of the address used for designating an index in the cache memory is also called a set address. These addresses are represented by bits. In the main memory, memory blocks accommodated in the same set are memory blocks having the same set address.

  The main memory has a larger capacity than the cache memory. Therefore, the number of memory blocks accommodated in the set in the main memory is larger than the number of cache blocks accommodated in the set in the cache memory. Therefore, all the memory blocks in the main memory cannot be assigned to the cache block in the cache memory. That is, the memory block accommodated in each set in the main memory can be divided into a memory block allocated to the cache block accommodated in each set in the cache memory and a memory block not allocated.

  Here, for example, consider a situation where data is acquired from a cache block assigned to a memory block instead of a memory block corresponding to an address designated by the processor core. In this case, the cache block to which the memory block corresponding to the address designated by the processor core is allocated is searched in the cache memory.

  If a cache block is hit in the search, the data specified by the processor core can be acquired from the hit cache block in the cache memory. On the other hand, if the cache block does not hit in the search, the data specified by the processor core does not exist in the cache memory. Therefore, the data specified by the processor core is acquired from the main memory. Such a scene is also called a cache miss hit.

  An index and a cache tag are used to search for a cache block to which a memory block corresponding to an address designated by the processor core is assigned. As described above, the index indicates a set that accommodates the corresponding cache block. The cache tag is a tag used to search for a cache block corresponding to a memory block in each set.

  A cache tag is provided for each cache block. When a memory block is assigned to a cache block, a part of the address of the memory block is stored in the cache tag corresponding to the cache block. Part of the address stored in the cache tag is different from the set address. Specifically, the cache tag stores an address of an appropriate bit length acquired from a portion obtained by removing the set address from the address of the memory block. The address stored in the cache tag is hereinafter referred to as a tag address.

  Using such an index and a cache tag, a cache block to which a memory block corresponding to an address designated by the processor core is allocated is searched.

  For example, first, a set that may contain a cache block to which a memory block corresponding to an address designated by the processor core is allocated is searched from the cache memory. Specifically, an index that matches the address of the set address corresponding portion of the address specified by the processor core is searched from the cache memory. The set indicated by the index searched at this time is a set that may accommodate a cache block to which a memory block corresponding to the address specified by the processor core is allocated.

  Then, the cache block to which the memory block corresponding to the address designated by the processor core is allocated is retrieved from the cache blocks contained in the set indicated by the retrieved index. Specifically, among the cache tags associated with each cache block accommodated in the retrieved set, a cache tag that stores the address of the corresponding portion of the tag address of the address specified by the processor core is retrieved. The cache block associated with the cache tag searched at this time is the cache block to which the memory block corresponding to the address designated by the processor core is assigned.

  In this search, if a cache tag storing the address corresponding to the tag address corresponding to the address specified by the processor core is not searched, a cache miss hit occurs. In this case, the cache block assigned to the memory block corresponding to the address designated by the processor core does not exist in the cache memory. Therefore, the data specified by the processor core is acquired from the main memory.

  The cache block to which the memory block corresponding to the address designated by the processor core is allocated is searched in this way. Thereby, when the data stored in the memory block is also stored in the cache memory, the data is acquired from the cache memory. On the other hand, when the data stored in the memory block is not stored in the cache memory, the data is acquired from the memory block.

  In addition to the set associative method, methods such as a direct mapping method and a full associative method are known as association methods between the cache memory block and the main memory block. The direct mapping method is a method for determining a cache memory block associated with an address of a main memory block. The direct mapping method corresponds to the association method when the number of ways in the set associative method is 1. The full associative method is a method in which an arbitrary block of the cache memory is associated with an arbitrary block of the main memory.

  On the other hand, in recent years, multi-core processor systems having a plurality of processor cores have become mainstream from the viewpoint of improving performance per chip and reducing power consumption. In this multi-core processor system, for example, a multi-core processor system is known in which each processor core has a primary cache memory and the secondary cache memory is shared by a plurality of processor cores.

  At this time, the secondary cache memory maintains cache coherency, which is the consistency between the cache memories, between the primary cache memory and the secondary cache memory of the plurality of processor cores sharing the secondary cache memory. It has a mechanism to do. In order to maintain cache coherency, when data is requested from a certain processor core, the secondary cache memory checks whether or not the data related to the request is stored in the primary cache memory included in each processor core.

  As a method of checking whether or not data requested from a certain processor core is stored in each primary cache memory, the secondary cache memory is snooped with respect to the primary cache memory of all the processor cores whenever there is a data request. A method of performing is known. However, this method requires a longer machine cycle until the inquiry result is returned from the primary cache memory, resulting in a longer latency until a response to the data request.

  Patent Document 1 discloses a method for improving this latency. Patent Document 1 discloses a method that eliminates the need for snoop processing to the primary cache memory by storing a copy of the cache tag of the primary cache memory in the cache tag of the secondary cache memory.

  When a copy of the cache tag of the primary cache memory is stored in the cache tag of the secondary cache memory, the secondary cache memory can refer to the state of the primary cache memory in its own cache tag. . Therefore, the secondary cache memory can check whether data requested from a certain processor core is stored in each primary cache memory without snooping with respect to the primary cache memory. Patent Document 1 discloses a method for improving latency by such a method. Hereinafter, the cache tag of the primary cache memory is referred to as an L1 tag. A cache tag of the secondary cache memory is called an L2 tag.

  However, the greater the difference between the capacity of the secondary cache memory and the capacity of the primary cache memory, the more data stored in the secondary cache memory is not stored in the primary cache memory. Therefore, if an area for storing a copy of the L1 tag is provided in the L2 tag, the area for storing the L1 tag copy in the L2 tag becomes a useless area that is hardly used. Since this state is not preferable from the viewpoint of physical quantity and power consumption, improvement has been demanded.

  Patent Documents 2 and 3 disclose methods for improving this useless area. In Patent Documents 2 and 3, instead of copying the L1 tag, information indicating the shared state of the corresponding line in each primary cache memory is stored in the L2 tag, and the copy of the L1 tag is stored in an area different from the L2 tag. A method of storing is disclosed.

JP 2006-40175 A Japanese Patent No. 4297968 JP 2011-65574 A JP-A-5-342101

  FIG. 14 shows a connection example of the primary cache and the secondary cache in the multi-core processor. In the connection example shown by FIG. 14, each core (700, 710,..., 7n0) includes a primary cache (701, 711,..., 7n1). Note that n is a natural number. The secondary cache 800 is shared by each core (700, 710,..., 7n0). In the connection example shown by FIG. 14, the secondary cache 800 exists between each core (700, 710,..., 7n0) and the memory 900.

  Further, L1 shared information 811 for storing information indicating the shared state of the corresponding line in each primary cache (701, 711,..., 7n1) is provided in an area in the L2 tag 810.

  Further, in the secondary cache 800, an L1 tag copy 820 for storing a copy of the L1 tag is provided in an area different from the L2 tag 810. In FIG. 14, an L1 tag copy 821 is a copy of the L1 tag 702 that is the primary cache tag of the core 700. The L1 tag copy 822 is a copy of the L1 tag 712 that is the primary cache tag of the core 710. The L1 tag copy 82n is a copy of the L1 tag 7n2, which is the primary cache tag of the core 7n0. It is assumed that the set associative method is adopted for the data storage structure of each primary cache (701, 711,..., 7n1) and secondary cache 800.

  In the secondary cache 800, in response to an access request from the core (700, 710,..., 7n0), processing requested based on the access request is executed. Since the secondary cache 800 includes one or more pipelines, it is possible to perform parallel processing of processes executed in response to access requests from the cores (700, 710,..., 7n0). The access request from the core (700, 710,..., 7n0) includes an access request based on the L1 replacement. Hereinafter, the access request from the core is also referred to as “request”.

  L1 replacement is processing that occurs when, for example, a cache miss occurs in the primary cache. When the data requested from the core is not stored in the primary cache, the data is acquired from the secondary cache or memory and stored in the primary cache. In the primary cache, the data is stored in any line in the set identified by an index that matches part of the address of the data.

  As described above, when data is written to the primary cache, data is stored in all the lines in the set to be written, and there are cases where there is no space in the lines in the set to be written. At this time, since data requested from the core is written to the primary cache, data replacement processing occurs in the line specified based on a replacement algorithm such as LRU (Least Recently Used). This replacement process is L1 replacement.

  Hereinafter, in L1 replacement, data written to a line to be replaced and an address corresponding to the data are referred to as replacement request data and replacement request address, respectively. As described above, the replacement request data is data that is the target of an access request from the core. Further, data replaced with replacement request data by L1 replacement and an address corresponding to the data are referred to as replacement target data and replacement target address, respectively.

  When L1 replacement occurs, an access request based on L1 replacement is issued. When the secondary cache 800 receives the access request, for example, in the L1 tag copy 820, the replacement request data is overwritten on the line where the replacement target data is stored, thereby erasing the replacement target data.

  In the secondary cache 800, processing required based on the access request from the core including the access request based on the L1 replacement is processed in parallel. When processing is performed in parallel in this way, depending on the content of the processing requested based on the preceding access request flowing through the pipeline, it is requested based on the subsequent access request until the processing is completed. The process is canceled and retried.

  For example, in the secondary cache 800, the L2 cache control unit 830 realizes such an operation cancellation and retry operation of the subsequent processing. In the example illustrated in FIG. 14, the L2 cache control unit 830 includes an address lock control unit 831 and a retry control unit 832.

  The address lock control unit 831 holds an address locked by a process requested based on a previous access request. Then, the address lock control unit 831 compares the address that is the target of the subsequent access request with the address held in the address holding unit. Thereby, the address lock control unit 831 determines whether or not the address to be processed based on the subsequent access request is locked. Based on the determination result (match information) of the address lock control unit 831, the retry control unit 832 identifies whether or not the processing requested based on the subsequent access request is canceled, and the subsequent processing Control undo and retry execution of. Note that the match information is, for example, 1-bit information expressing the presence or absence of the lock. Hereinafter, the determination executed by the address lock control unit 831 is referred to as “lock check”.

  Here, there are two types of addresses to be locked. The first address is the address of the data that is the target of the access request. The second address is a replacement target address when the access request from the core is an access request based on L1 replacement. When the access request from the core is an access request based on the L1 replacement, the replacement target data is processed in the processing requested based on the access request. Therefore, the replacement target address is locked in addition to or in place of the replacement request address that is the target of processing requested based on the access request. As the processing requested based on the access request from the core is executed, the address lock control unit 831 holds these two types of addresses as locked addresses.

  In addition, as a method of expressing the address held in the address lock control unit 831, that is, the locked address, there is a method of using the address to be locked, that is, the full size address as it is.

  On the other hand, Patent Documents 3 and 4 disclose a method of expressing a full-size address using an L2 index and an L2 way. If the secondary cache line corresponding to the primary cache line can be uniquely identified, the primary cache line can be searched using the cache hit information in the secondary cache. Patent Documents 3 and 4 disclose a method of associating a primary cache line with a secondary cache line.

  Specifically, a method is disclosed that uses the difference between the L2 index, the L1 index, and the L2 way instead of the comparison address used in the search process in the primary cache when searching for the corresponding line in the L1 tag copy. Yes. That is, the difference between the L2 index and the L1 index and the L2 way are registered in the L1 tag copy instead of the comparison address. Patent Documents 3 and 4 disclose that the primary cache line and the secondary cache line are associated with each other to reduce the amount of the L1 tag copy.

  According to this method, the primary cache line can be uniquely identified by the hit information (L2 index and L2 way) related to the cache hit in the secondary cache. Therefore, according to the method, the L2 index and the L2 way are information corresponding to a full-size address. Therefore, according to the method, the address to be locked can be expressed by the L2 index and the L2 way instead of the full size address.

  That is, in the conventional method, the address to be locked is expressed by using a full-size address or by using a set of L2 index and L2 way. Based on these assumptions, operations related to a conventional lock check will be described with reference to FIGS. In this operation example, the access request from the core includes the address of the data to be processed based on the access request and the L1 way of the primary cache line related to the access request. It shall be included. The primary cache line related to the access request from the core is, for example, a line that is a storage destination of the loaded data if the access request from the core is a data load request.

  FIG. 15 illustrates an operation related to a lock check in a method of expressing a locked address using a full-size address as it is.

  When the lock check is executed for the address of the data to be processed that is requested based on the access request, the address lock control unit 831 acquires the address included in the access request from the core. Note that the address (A) in FIG. 15 is an address included in the access request from the core. Then, the address lock control unit 831 compares the address acquired from the access request from the core with the held lock target address to determine whether or not the acquired processing target address is the lock target. Determine. The retry control unit 832 identifies whether or not the execution of the process requested based on the access request from the core is canceled based on the determination result of the address lock control unit 831, and cancels the execution of the process. Control retries.

  On the other hand, when the lock check is executed for the replacement target address in the access request based on the L1 replacement, the address lock control unit 831 acquires the replacement target address from the L1 tag copy 820. Note that the address (B) in FIG. 15 is the replacement target address. Specifically, the address lock control unit 831 searches the L1 tag copy 820 for a line that matches the information included in the access request based on the L1 replacement. Note that the address (A) and the L1 way (A) in FIG. 15 are information included in the access request based on the L1 replacement. Then, the address lock control unit 831 acquires the replacement target address from the line indicated by the search result.

  Then, the address lock control unit 831 determines whether or not the replacement target address is a lock target by comparing the acquired replacement target address with the held lock target address. Based on the determination result of the address lock control unit 831, the retry control unit 832 identifies whether or not the execution of the process requested based on the access request based on the L1 replacement is canceled, and cancels the execution of the process. And control retry.

  FIG. 16 illustrates the operation related to the lock check in the method of expressing the address locked using the L2 index and the L2 way.

  When performing a lock check on the address of the data to be processed that is requested based on the access request, the address lock control unit 831 reads the L2 index corresponding to the address to be processed from the L2 tag 810. And L2 way is acquired. Specifically, the address lock control unit 831 searches the L2 tag 810 for a line that hits the information included in the access request. Note that the address (A) in FIG. 16 is information included in the access request. Then, the address lock control unit 831 acquires the L2 index and the L2 way corresponding to the address to be processed from the line indicated by the search result. Note that the L2 index (A) and the L2 way (A) in FIG. 16 are the L2 index and the L2 way corresponding to the address to be processed.

  Then, the address lock control unit 831 compares the acquired L2 index and L2 way with the held L2 index and L2 way to be locked to determine whether or not the address to be processed is a lock target. Determine whether. The retry control unit 832 identifies whether or not the execution of the processing requested based on the access request from the core is canceled based on the determination result of the address lock control unit 831, and cancels the execution of the access request. And control retry.

  On the other hand, when the lock check is executed for the replacement target address in the access request based on the L1 replacement, the address lock control unit 831 acquires the L2 index and the L2 way corresponding to the replacement target address from the L1 tag copy 820. Specifically, the address lock control unit 831 searches the L1 tag copy 820 for a line that matches the information included in the access request based on the L1 replacement. Note that the address (A) and the L1 way (A) in FIG. 15 are information included in the access request based on the L1 replacement. The address lock control unit 831 acquires the L2 index and the L2 way corresponding to the replacement target address from the line indicated by the search result. Note that the L2 index (B) and the L2 way (B) in FIG. 16 are the L2 index and the L2 way corresponding to the replacement target address.

  Then, the address lock control unit 831 compares the acquired L2 index and L2 way with the held L2 index and L2 way to be locked to determine whether the replacement target address is a lock target or not. judge. Based on the determination result of the address lock control unit 831, the retry control unit 832 identifies whether or not the execution of the process requested based on the access request based on the L1 replacement is canceled, and cancels the execution of the process. And control retry.

  As described above, in the conventional method, in the lock check in the access request based on the L1 replacement, the address lock control unit 831 searches the L1 tag copy 820 in order to obtain the replacement target address. FIG. 17 is a diagram summarizing the operation of the lock check shown in FIGS. 15 and 16. FIG. 17 illustrates an operation related to an access request based on L1 replacement.

  As shown in FIG. 17, when the access request based on the L1 replacement is issued from the core, the secondary cache 800 obtains the replacement target address or the L2 index and the L2 way corresponding to the replacement target address from the L1 tag copy. To be acquired. Then, a lock check based on the replacement target address or the L2 index and the L2 way is executed. If it is not locked, the process related to the access request based on the L1 replacement is executed. When the processing related to the access request is executed, for example, in the L1 tag copy 820, the replacement request data is overwritten on the line where the replacement target data is stored. As a result, the replacement target data is deleted from the L1 tag copy 820.

  In the conventional method, when a lock check is performed in a process requested based on an access request based on L1 replacement, a search process in the L1 tag copy is executed in order to obtain a replacement target address or the like. Specifically, the second cache memory is shared by a plurality of processor cores having the first cache memory (L1). In this case, when a replace request occurs in any of the first cache memories, the second cache memory copies the tag (L1) of the first cache memory in order to identify the target address or the like of the replace request. Tag copy) is searched. Therefore, in the lock check related to the replacement target address, there is a problem that a delay corresponding to the search for the replacement target address from the copy of the tag of the first cache memory occurs.

  In one aspect, an object of the present invention is to improve a delay that occurs during a lock check of an address that is a target of a replacement request.

  One aspect of the disclosed technology can be exemplified by the following arithmetic processing device. The arithmetic processing device includes a plurality of arithmetic processing units including a first cache memory, each of which performs an arithmetic operation and outputs an access request, and the plurality of arithmetic processing units each holding data calculated by the plurality of arithmetic processing units. The second cache memory shared by the processing unit and the control target access request including way information indicating the way of the cache block of the first cache memory to be controlled in the arithmetic processing unit of the control target access request source An acquisition unit that acquires attribute information related to the original first cache memory, address information related to a control target address that specifies a cache block that is a target of the control target access request in the second cache memory, and acquired A holding unit for holding the attribute information, and the first cache memory Based on the replacement target address included in the access request related to the replacement request issued by one of the plurality of arithmetic processing units and the way information indicating the way of the cache block to be replaced in the first cache memory, the control target A control unit that controls an access request related to the replacement request for the cache block of the second cache memory specified by the address information and the attribute information.

  According to this arithmetic processing unit, it is possible to improve the delay that occurs during the lock check of the address that is the target of the replacement request.

FIG. 1 illustrates an apparatus according to an embodiment. FIG. 2 illustrates a data format of the cache tag according to the embodiment. FIG. 3A illustrates lock processing according to the embodiment in a normal order. FIG. 3B illustrates lock processing according to the embodiment in the replacement order. FIG. 4 illustrates lock processing of the address lock control unit according to the embodiment. FIG. 5 exemplifies an operation related to acquisition of a replacement target address in the embodiment. FIG. 6A illustrates a lock check according to an embodiment in a normal order. FIG. 6B illustrates the lock check according to the embodiment in the replacement order. FIG. 7 illustrates a lock check of the address lock control unit according to the embodiment. FIG. 8 illustrates lock processing and lock check according to the embodiment. FIG. 9 illustrates a circuit of the address lock control unit according to the embodiment. FIG. 10 illustrates a specific operation of the lock check according to the embodiment. FIG. 11 illustrates a specific operation of the lock check according to the embodiment. FIG. 12A illustrates the lock range in the conventional method. FIG. 12B illustrates the lock range in the embodiment. FIG. 13A illustrates the effect of a conventional lock range. FIG. 13B illustrates the effect of the lock range of the embodiment. FIG. 14 illustrates a conventional multi-core processor system. FIG. 15 illustrates the operation of the lock check when the lock target is expressed by a full-size address. FIG. 16 illustrates the operation of the lock check when the lock target is expressed by the L2 index and the L2 way. FIG. 17 illustrates the operation of a conventional multi-core processor system in response to an access request based on L1 replacement.

  Embodiments according to one aspect of the present invention will be described below with reference to the drawings. However, the embodiments described below are merely examples of the present invention in all respects, and are not intended to limit the scope thereof. It goes without saying that various improvements and modifications can be made without departing from the scope of the present invention. That is, in implementing the present invention, specific elements according to the present embodiment may be employed as appropriate. Hereinafter, an embodiment according to one aspect of the present invention is also referred to as “this embodiment”.

  Further, the present embodiment described below exemplifies a two-level cache memory. However, the present invention may be applied to cache memories other than two layers. In consideration of the case where it is applied to a cache memory having three or more layers, the primary cache in the following embodiments may be referred to as a “first cache memory”. Further, the secondary cache in the following embodiments may be referred to as a “second cache memory”.

  Note that data appearing in the present embodiment is described in a natural language (such as Japanese). However, these data are specifically designated by a pseudo language, a command, a parameter, a machine language, etc. that can be recognized by a computer.

§1 Device Example First, an example device according to the present embodiment will be described with reference to FIG. FIG. 1 illustrates a multi-core processor system according to this embodiment. As shown in FIG. 1, the multi-core processor system according to the present embodiment includes m + 1 processor cores (100, 110, 1m0), a secondary cache 200, a memory controller 300, and a main memory 400. Note that m is a natural number. In this embodiment, units other than the main memory 400 are provided on one semiconductor chip. However, the multi-core processor system according to the present embodiment does not have to be formed in this way. The relationship between the semiconductor chip and each unit is appropriately determined.

  Each processor core (100, 110,..., 1m0) includes an instruction control unit (101, 111,..., 1m1), an operation execution unit (102, 112,..., 1m2), and a primary cache. (103, 113, ..., 1m3). As shown in FIG. 1, each processor core (100, 110,..., 1m0) is also referred to as “first core”, “second core”, and “m + 1 core”, respectively. Each processor core (100, 110,..., 1m0) corresponds to an arithmetic processing unit.

  The instruction control unit (101, 111,..., 1m1) is a control unit that performs instruction decoding and processing order control in each processor core (100, 110,..., 1m0). Specifically, the instruction control unit (101, 111,..., 1m1) fetches an instruction (machine instruction) from the storage device. The storage device for storing machine instructions is, for example, the main memory 400, the secondary cache 200, and the primary cache (103, 113,..., 1m3). Then, the instruction control unit (101, 111,..., 1m1) interprets (decodes) the fetched instruction. In addition, the instruction control unit (101, 111,..., 1m1) obtains data to be processed in the instruction from the storage device and provides the data to each processor core (100, 110,..., 1m0). Stored in a designated register. Then, the instruction control unit (101, 111,..., 1m1) controls the execution of the instruction for each acquired data.

  The calculation execution unit (102, 112,..., 1m2) performs calculation processing. Specifically, each operation execution unit (102, 112,..., 1m2) interprets the data read into the register or the like by each instruction control unit (101, 111,..., 1m1). The operation corresponding to the issued instruction is executed.

  The primary cache (103, 113,..., 1m3) and the secondary cache 200 include an instruction control unit (101, 111,..., 1m1) and an operation execution unit (102, 112,..., 1m2). This is a cache memory that temporarily holds data to be processed.

  Each of the primary caches (103, 113,..., 1m3) is a cache memory dedicated to each processor core (100, 110,..., 1m0). The primary cache (103, 113,..., 1m3) is a separate cache memory in which an instruction (IF) cache and an operand (OP) cache are separated. The instruction cache stores data requested by instruction access. The operand cache stores data requested by data access. The operand cache is also called a data cache. By separating the cache according to the type of data to be stored in this way, it is possible to increase the processing speed of the cache as compared to the integrated cache that is not separated. However, the structure of the cache memory used in the present invention is not limited to the separate cache memory.

  On the other hand, the secondary cache 200 is a cache memory shared by the processor cores (100, 110,..., 1m0). The secondary cache 200 is an integrated cache memory that stores instructions and operands without distinction. Note that the cache may be divided into banks in order to improve the processing capability.

  The primary cache (103, 113,..., 1m3) can process data at a higher speed than the secondary cache 200, but has a small capacity for storing data. Each processor core (100, 110,..., 1m0) uses a primary cache (103, 113,..., 1m3) and a secondary cache 200 with different processing speeds and capacities, thereby enabling the main memory The processing speed difference from 400 is filled.

  In this embodiment, data stored in the primary cache (103, 113,..., 1m3) is also stored in the secondary cache 200. In other words, the cache used in the present embodiment is an inclusion cache in which the relationship that data stored in an upper cache memory close to the processor core is included in the lower cache memory is established.

  For example, when the secondary cache 200 acquires the data (address block) requested from the processor core from the memory, the secondary cache 200 transfers the acquired data to the primary cache and simultaneously registers the data in itself. Further, after the data registered in the primary cache is invalidated or written back to the secondary cache 200, the secondary cache 200 writes back the data registered in itself to the memory. By such an operation, data stored in the primary cache is included in the secondary cache 200.

  The inclusion cache has an advantage that the structure and control of the cache tag are simpler than other structures of the cache. However, the cache memory used in the present invention is not limited to the inclusion cache.

  Further, a set associative method is adopted for the data storage structures of the primary cache (103, 113,..., 1m3) and the secondary cache 200. As described above, the lines of the primary cache (103, 113,..., 1m3) are represented by the L1 index and the L1 way. A line of the secondary cache 200 is represented by an L2 index and an L2 way. It is assumed that the primary caches (103, 113,..., 1m3) and the secondary cache 200 have the same line size.

  As shown in FIG. 1, the primary cache 103 includes an L1 cache control unit 104, an L1 instruction cache 105, and an L1 operand cache 106. The L1 cache control unit 104 includes an address conversion unit 104a and a request processing unit 104b. The L1 instruction cache 105 and the L1 operand cache 106 include L1 tags (105a and 106a) and L1 data (105b and 106b), respectively. In the present embodiment, each primary cache (113,..., 1m3) is formed in the same manner as the primary cache 103.

  The address conversion unit 104a converts a logical address specified by an instruction fetched by the instruction control unit 101 into a physical address. For the translation of the address, a TLB (Translation Lookaside Buffer), a hash table, or the like may be used.

  Further, the request processing unit 104b processes a cache data operation based on an instruction controlled by the instruction control unit 101. For example, the request processing unit 104b searches the L1 instruction cache 105 or the L1 operand cache 106 for data corresponding to the data request from the instruction control unit 101. When the corresponding data is retrieved, the request processing unit 104b returns the retrieved data to the instruction control unit 101. If the corresponding data is not retrieved, the request processing unit 104b returns a cache miss hit result to the instruction control unit 101. The request processing unit 104b also processes data operations in the primary cache based on the L1 replacement described above. Further, in response to a request from the secondary cache 200, the request processing unit 104b also executes a process of writing back the data designated by the request to the secondary cache 200.

  The L1 instruction cache 105 and the L1 operand cache 106 are storage units that store data in the primary cache 103. The L1 instruction cache 105 stores machine instructions that are accessed at the time of instruction fetch. The L1 operand cache 106 stores data specified by the operand part of the machine instruction.

  The L1 tags (105a and 106a) store cache tags of the L1 instruction cache 105 and the L1 operand cache 106, respectively. The address of the data stored in the line is specified by the cache tag and the L1 index. The L1 data (105b, 106b) stores data corresponding to addresses specified by the L1 index and the L1 tag (105a, 106a), respectively.

  As shown in FIG. 1, the secondary cache 200 includes an L2 cache control unit 210 and an L2 cache data unit 220. The L2 cache control unit 210 includes a replacement target address included in an access request related to a replacement request issued by any one of the plurality of arithmetic processing units with respect to the first cache memory, and a way of the cache block to be replaced in the first cache memory. The access request related to the replacement request for the cache block of the second cache memory specified by the address information and the attribute information to be controlled is controlled based on the way information indicating the above. In the present embodiment, the L2 cache control unit 210 includes a request processing unit 211, a retry control unit 212, and an address lock control unit 213. The L2 cache data unit 220 includes an L2 tag 221, L2 data 222, and an L1 tag copy 223.

  The request processing unit 211 executes processing requested based on an access request from each processor core (100, 110,..., 1m0). In this embodiment, the access request from the processor core 100 is issued by the instruction control unit 101.

  The access request includes, for example, a data request issued when a cache miss hit occurs in the primary cache. For example, the instruction control unit 101 tries to acquire data from the primary cache 103 at the time of instruction fetch or data access. At this time, if the target data is not stored in the primary cache 103, a cache miss occurs. When a cache miss hit occurs, the instruction control unit 101 tries to acquire the target data from the secondary cache 200. The data request is an access request from the core to the secondary cache 200 issued at this time.

  The access request includes, for example, an access request based on L1 replacement. For example, the instruction control unit 101 acquires data that is not stored in the primary cache 103 from the secondary cache 200 or the main memory 400. At this time, the instruction control unit 101 requests the request processing unit 104 b to store the acquired data in the primary cache 103. Assume that L1 replacement occurs at this time. As described above, when an L1 replacement occurs, data processing is executed in the primary cache and the secondary cache where the L1 replacement has occurred. At this time, the access request based on the L1 replacement is an access request issued by the instruction control unit 101 in order to execute data processing in the secondary cache.

  For example, when these processes are executed at the time of instruction fetch, the acquired data is stored in the L1 instruction cache 105. Further, for example, when these processes are executed when accessing the data related to the operand part of the machine instruction, the acquired data is stored in the L1 operand cache 106.

  The request processing unit 211 executes these access requests while maintaining coherency between the primary cache (103, 113,..., 1m3) and the secondary cache 200. That is, the request processing unit 211 controls cache coherency between the primary cache (103, 113,..., 1m3) and the secondary cache 200. At this time, the request processing unit 211 performs processing for invalidating and writing back the corresponding line for the primary cache to maintain cache coherency for the processor cores (100, 110,..., 1m0). Make a request. An example will be described later.

  In addition, regarding the access request from the core, hereinafter, the processing instruction related to the access request based on the L1 replacement is also referred to as “L1 replacement order”, and the processing instruction related to the access request other than the access request based on the L1 replacement is “normally”. Of "order". Here, the access request may be referred to as a processing request including related processing such as acquisition of data that is a target of the access request.

  The retry control unit 212 cancels the execution of the access request related to the address locked by the address lock control unit 213 and tries again. In the present embodiment, the secondary cache 200 includes one or more pipelines (not shown). As described above, when the processes are processed in parallel, depending on the preceding process flowing in the pipeline, the execution of the subsequent process is canceled and retried until the preceding process is completed. The retry control unit 212 controls cancellation and retry of the subsequent processing.

  The address lock control unit 213 includes an L1 attribute information acquisition unit 214, an address holding unit 215, and a lock determination unit 216. The L1 attribute information acquisition unit 214 and the address holding unit 215 correspond to an acquisition unit and a holding unit, respectively.

  The L1 attribute information acquisition unit 214 acquires attribute information related to the primary cache (103, 113,..., 1m3). In addition, the L1 attribute information acquisition unit 214 acquires address information to be processed based on an access request from the core. The address information relates to a control target address that identifies a cache block that is a target of an access request to be controlled in the second cache memory, and is, for example, the above-described full size address or a set of L2 index and L2 way . In the present embodiment, the address information is a set of L2 cache and L2 way. The attribute information includes way information for identifying the L1 way of the primary cache line related to the access request. The way information is, for example, a way number indicating the L1 way of the corresponding line. The attribute information corresponds to attribute information related to the first cache memory of the access request source to be controlled. The way information corresponds to way information indicating the way of the cache block of the first cache memory to be controlled in the arithmetic processing unit of the access request source to be controlled.

  In the present embodiment, the L1 attribute information acquisition unit 214 further acquires attribute information including information indicating the core that issued the access request and information indicating the type of data. The information indicating the core corresponds to information indicating the arithmetic processing unit of the access request source to be controlled, and is, for example, a core number. The information indicating the type of data corresponds to information indicating the type of data that is the target of the access request, and is specified by the operand part of the machine instruction or whether the data is data related to the machine instruction. It is information indicating whether it is data. The data relating to the machine instruction is data stored in the instruction cache. The data specified by the operand part of the machine instruction is data stored in the operand cache. These pieces of information are used as information indicating a target to be locked in executing the process while the process requested based on the access request issued by the processor core is being executed. These pieces of information are also used to determine whether or not the processing target requested based on the access request from the core is locked.

  The address holding unit 215 receives the address acquired by the L1 attribute information acquisition unit 214 as information indicating a target to be locked when the processing related to the access request issued by each processor core is executed. Holds information and attribute information. Hereinafter, the information held by the address holding unit 215 is also referred to as lock target information.

  In the present embodiment, the address holding unit 215 effectively holds the lock target information corresponding to the processing while the processing requested based on the access request issued by the processor core is being executed. Then, after the execution of the process is completed, the address holding unit 215 invalidates the lock target information corresponding to the process. The invalidation of data may be realized by deleting data, or may be realized by a flag indicating that the data is invalid. In the present embodiment, the latter method is adopted (see FIG. 9 described later).

  Note that the address holding unit 215 holds the lock target information in a state in which the lock target core and the data type can be identified as the target to be locked by the processing requested based on the access request from the core. . The core to be locked and the type of data may be identified by including information for identifying them in the lock target information. Further, the core to be locked and the type of data may be identified by preparing lock target information for each of them. In the present embodiment, the latter form is adopted for the core to be locked, and the former form is adopted for the type of data to be locked (see FIG. 9 described later).

  The lock determination unit 216 determines whether the processing target requested based on the access request issued by the processor core is locked. Specifically, the lock determination unit 216 compares the address information corresponding to the access request issued by the processor core and the attribute information including the L1 way with the information held by the address holding unit 215. Thereby, the lock determination unit 216 determines whether or not the processing target requested based on the access request is locked. The access request for which it is determined whether or not it is locked includes an access request based on L1 replacement.

  The address lock control unit 213 controls processing requested by these units based on an access request issued by the processor core. In the system according to the present embodiment, the address lock control unit 213 controls the lock of the address, thereby improving the delay that occurs during the lock check of the address to be replaced. The detailed operation of the address lock control unit 213 will be described later.

  The L2 cache data unit 220 is a storage unit that stores data of the secondary cache 200. The L2 tag 221 stores the cache tag of the secondary cache 200. The address of the data stored in the line in the secondary cache 200 is specified by the cache tag and the L2 index. The L2 data 222 stores data corresponding to the address specified by the L2 index and the L2 tag 221. Further, the L1 tag copy 223 stores a cache tag copy of the primary cache (103, 113,..., 1m3). The L1 tag copy 223 stores, for example, a copy of the L1 tag (105a, 106a).

  As shown in FIG. 1, the multi-core processor system according to this embodiment includes a memory controller 300 and a main memory 400. The memory controller 300 processes writing and reading of data in the main memory 400. For example, the memory controller 300 writes the data to be written back into the main memory 400 in response to the data write back executed by the request processing unit 211. Further, in response to a data request from the request processing unit 211, the memory controller 300 reads data related to the request from the main memory 400. The main memory 400 is a main storage device used in the multi-core processor system according to the present embodiment.

§2 Data format Next, the data format of the cache tag used in this embodiment will be described with reference to FIG. FIG. 2 illustrates the data format of cache tags stored in the primary cache (103, 113,..., 1m3) and the secondary cache 200. FIG. 2 illustrates the data format of the cache tag for one line.

  In the example shown in FIG. 2, each entry of the L1 tag (105a, 106a) has an area for storing the physical address upper bits B1 and the status 500. The physical address upper bit B1 is used for searching for the corresponding line. The status 500 is information indicating whether the data stored in the line corresponding to the cache tag is valid, whether the data has been updated, and the like. With such an L1 tag, the data stored in the primary cache is searched.

  Specifically, first, the request processing unit 104b searches the L1 instruction cache 105 or the L1 operand cache 106 for a set provided with an L1 index that matches the lower bit of the logical address provided by the instruction control unit 101. . If the operation is in the instruction fetch stage, the request processing unit 104b searches the L1 instruction cache 105 for a corresponding set. If the operation is in the process of acquiring the data specified in the operand part of the machine instruction, the request processing part 104b searches the L1 operand cache 106 for the corresponding set.

  Next, the request processing unit 104b searches the corresponding set for a line storing data specified by the logical address given by the instruction control unit 101. This search is performed using the physical address. Therefore, before the search, the logical address given by the instruction control unit 101 is converted into a physical address by the address conversion unit 104a.

  That is, in the primary cache 103, an index is given by a logical address (virtual address) and a cache tag is given by a real address (physical address). Such a method is called a VIPT (Virtually Indexed Physically Tagged) method.

  The address given from the core is a logical address. For this reason, in the PIPT (Physically Indexed Physically Tagged) method in which an index is given by a physical address, the search for the corresponding line is executed after a conversion process from a logical address to a physical address. On the other hand, according to the VIPT method, it is possible to specify the index and convert the logical address to the physical address in parallel. Therefore, the VIPT method has less latency than the PIPT method.

  Further, in the VIVT (Virtually Indexed Virtually Tagged) system in which the cache tag is given by a logical address, a problem (homonym problem) occurs in which different physical addresses are assigned to the same virtual address. In the VIPT method, since the physical address is used for the cache tag, the homonym problem can be detected.

  Due to these advantages, the VIPT method is adopted for the cache used in this embodiment. However, the cache used in the present invention is not limited to the VIPT method.

  The request processing unit 104b compares the high-order bits of the physical address converted by the address conversion unit 104a with the high-order bits B1 of the physical address of each entry of the L1 tag. The line corresponding to the entry of the L1 tag including the physical address high-order bit B1 that matches the high-order bit of the physical address converted by the address conversion unit 104a stores the data designated by the logical address given by the instruction control unit 101 It is a line to do. Therefore, the request processing unit 104b searches the L1 tag entry including the physical address high-order bit B1 that matches the high-order bit of the given physical address from the L1 tags corresponding to the lines included in the searched set.

  Finally, when an entry of the corresponding L1 tag is found as a result of the search, the request processing unit 104b acquires the data stored in the line corresponding to the entry of the corresponding L1 tag, and uses the acquired data as the instruction control unit 101. On the other hand, when the corresponding L1 tag entry is not found, the request processing unit 104b determines that a cache miss hit has occurred, and notifies the instruction control unit 101 that the designated data is not stored in the primary cache 103. Notice. In the present embodiment, the data stored in the primary cache is searched in this way.

  An L1 tag entry is prepared for each core, each data type, each index, and each way. FIG. 1 shows that an entry for the L1 tag is prepared for each core, each index, and each data type. In addition, since the set associative method is adopted for the data storage structure of the primary cache (103, 113,..., 1m3) in the present embodiment, an L1 tag entry is prepared for each way ( (See FIG. 9 described later).

  In the example shown in FIG. 2, the entry of the L2 tag 221 has an area for storing the physical address upper bit B2, the status 501, the logical address lower bit A1, and the L1 shared information 502.

  The physical address upper bit B2 is used for searching for the corresponding line in the secondary cache 200. The status 501 is information indicating whether or not the data stored in the line corresponding to the cache tag is valid, whether or not the data has been updated in the secondary cache 200.

  The logical address lower bit A1 is used, for example, to solve the synonym problem. In this embodiment, the VIPT method is adopted in the primary cache. Therefore, a synonym problem in which different logical addresses are assigned to the same physical address may occur. In the present embodiment, it is possible to detect whether or not the synonym problem has occurred by referring to the logical address lower bit A1.

  The L1 shared information 502 is information indicating a shared state in the primary cache (103, 113,..., 1m3) for the data stored in the line corresponding to the cache tag (for example, Patent Documents 2 and 3). See). The area for storing the L1 shared information 502 is provided instead of storing the L1 tag copy 223 in order to reduce the amount of the L2 tag 221. The L2 tag 221 searches for data stored in the secondary cache 200.

  Data retrieval can be described in substantially the same manner as retrieval processing in the primary cache 103. Specifically, the request processing unit 211 first searches for a set to which an L2 index that matches the lower bits of the physical address included in the access request given from the core is given. Hereinafter, the processing target address included in the access request from the core is also referred to as “request address”.

  Next, the request processing unit 211 searches the corresponding set for a line in which data specified by the request address given from the core is stored. Specifically, the request processing unit 211 searches the entry of the L2 tag 221 including the physical address upper bit B2 that matches the upper bit of the request address given from the core, and the L2 tag 221 corresponding to the line included in the searched set. Search from within.

  Finally, as a result of the search, when an entry of the corresponding L2 tag 221 is found, the request processing unit 211 acquires the data stored in the line corresponding to the entry of the corresponding L2 tag 221 and issues an access request Pass the acquired data to the core. On the other hand, if the entry of the corresponding L2 tag 221 is not found, the request processing unit 211 determines that a cache miss hit. Then, the request processing unit 211 requests the memory controller 300 for data specified by the request address. In response to the request from the request processing unit 211, the memory controller 300 acquires the corresponding data from the main memory 400, and passes the acquired data to the secondary cache 200.

  In this embodiment, since the set associative method is adopted for the data storage structure of the secondary cache, the entry of the L2 tag 221 is prepared for each index and for each way (see FIG. 9 described later). ).

  Further, the data storage capacity of the secondary cache 200 is larger than the data storage capacity of the primary cache 103. In the present embodiment, the line size of the primary cache 103 and the line size of the secondary cache 200 are the same. Therefore, normally, the number of sets of the secondary cache 200 is larger than the number of sets of the primary cache 103. In this case, the bit length of the L2 index is longer than the bit length of the L1 index. Therefore, in this case, the bit length of the physical address upper bits B2 is shorter than the bit length of the physical address upper bits B1. However, depending on the cache capacity and the number of ways, the bit length of the physical address upper bit B1 may be shorter than the physical address upper bit B2, or may be the same. These relationships are appropriately selected.

  In the example shown in FIG. 2, the entry of the L1 tag copy 223 has an area for storing an index difference 503, an L2 way 504, and a status 505.

  The index difference 503 is a difference between the logical address lower bit A1 and the physical address lower bit B3. The L2 way 504 is an L2 way that represents a secondary cache line corresponding to the L1 tag copy 223. In the present embodiment, since the data stored in the primary cache is stored in the secondary cache, the L2 way 504 is specified. The index difference 503 and the L2 way 504 associate the entry of the L1 tag copy 223 and the entry of the L2 tag 221 (see Patent Documents 3 and 4). The status 505 indicates whether or not the data stored in the line corresponding to the cache tag is valid, whether or not the data is updated in the primary cache (103, 113,..., 1m3). Information.

  According to such an L1 tag copy 223, the secondary cache 200 can execute a search for the L1 tag copy 223 using the search result of the L2 tag 221.

  Specifically, the request processing unit 211 refers to the L2 tag 221 in order to search for corresponding data from the secondary cache 200. When the corresponding data exists in the secondary cache 200, the entry in the L2 tag 221 corresponding to the line storing the corresponding data is searched by searching the L2 tag 221 using the physical address of the data. By this search, the L2 index and the L2 way related to the search target data can be specified. The L1 index related to the search target data is specified by a part of the L2 index or the logical address lower bit A1 in the L2 tag 221. Therefore, the L1 index, the L2 index, and the L2 way related to the data to be searched are specified by searching the L2 tag 221.

  Here, the entry of the L1 tag copy 223 can be specified by the L1 index, the index difference 503, and the L2 way 504. The index difference 503 is a difference between the L1 index (logical address lower bit A1) and the L2 index (physical address lower bit B3). Therefore, the secondary cache 200 can specify the entry of the L1 tag copy 223 corresponding to the search target data by the L1 index, the L2 index, and the L2 way specified by the search of the L2 tag 221.

  Note that the L1 index related to the search target data may be included in the L2 index. In this case, the L1 index may be specified from the L2 index. In addition, information related to the L1 index may be included in the access request from the core. In this case, the L1 index may be specified from information included in the access request from the core. Note that the information related to the L1 index included in the access request from the core is, for example, the logical address itself.

  Note that, since the cache memory of the present embodiment is an inclusion cache, when there is no corresponding data in the secondary cache 200, the data does not exist in the primary cache. Therefore, the entry in the L1 tag copy 223 is not searched for data that does not exist in the secondary cache 200.

  Depending on the correspondence between the logical address and the physical address, the logical address lower bit A1 may be included in the physical address lower bit B3. In this case, the bit length of the index difference 503 is equal to the difference between the bit length of the physical address lower bit B3 and the logical address lower bit A1.

  In addition, when the bit length of the index difference 503 and the L2 way 504 is shorter than the bit length of the physical address upper bits B1, the amount of the L1 tag copy 223 is reduced compared to the case where the L1 tag is copied as it is. The

  The L1 tag copy 223 is mainly used to maintain coherency between the primary cache (103, 113,..., 1m3) and the secondary cache 200 (see Patent Documents 1 to 3). . The L1 tag copy 223 is prepared for each core, each data type, and each way for the same reason as the L1 tag.

§3 Address lock controller <Operation example>
Next, an operation example of the address lock control unit 213 according to the present embodiment will be described with reference to FIGS. 3A, 3B, 4, 5, 6A, 6B, 7, and 8.

<Address registration>
First, with reference to FIGS. 3A, 3B, 4 and 5, the registration processing of the address to be locked by the address lock control unit 213 according to the present embodiment will be described. FIG. 3A exemplifies a registration process in the case where a processing instruction related to an access request from the core is in a normal order. FIG. 3B exemplifies a registration process when a process command related to an access request from the core is a replacement order. FIG. 4 shows a summary of the registration process shown in FIGS. 3A and 3B. FIG. 4 illustrates the registration processing of the address to be locked by the address lock control unit 213 according to the present embodiment.

  The address lock control unit 213 uses the information specified by the access request from the core to acquire lock target information for specifying the lock target. Then, the address lock control unit 213 holds the acquired lock target information in the address holding unit 215. In this embodiment, while the lock target information is held in the address holding unit 215, the target indicated by the lock target information is registered as the lock target.

  As shown in FIGS. 3A and 3B, from the lock target information held as information indicating the lock target in the present embodiment, the lock target core, data type, L2 index, L2 way, L1 index, and Six types of information on the L1 way can be specified. Note that the lock target information may not be able to specify all six types of information. For example, the lock target information may be able to identify some types of information among these six types of information.

  In addition, the lock target information shown in FIGS. 3A and 3B includes six types of information for specifying the lock target: lock target core, data type, L2 index, L2 way, L1 index, and L1 way. Information is included. As a result, the lock target core, data type, L2 index, L2 way, L1 index, and L1 way can be specified from the lock target information shown in FIGS. 3A and 3B.

  However, even if the lock target information does not include information indicating the lock target, the lock target indicated by the information not included in the lock target information can be specified. For example, when an entry for storing lock target information is prepared for each core, the lock target core can be specified even if the lock target information does not include information indicating the core.

  Therefore, in the following description of the address registration process using FIGS. 3A and 3B, it is assumed that information for specifying the lock target is included in the lock target information. However, information for specifying the lock target is described. May not be included in the lock target information. If the lock target can be specified, the information included in the lock target information may be appropriately selected.

  First, regarding the process of registering lock target information, information that can be specified by an access request from the core will be described. As shown in FIGS. 3A and 3B, the secondary cache 200 can specify the request address, the request core, the request opcode, and the request way from the access request from the core.

  As described above, the request address is a physical address of the main memory 400 that stores data to be processed based on an access request issued by the core. The request address may include a logical address corresponding to the physical address. The request address may include not the logical address itself but the logical address lower bit A1 (L1 index) used for searching the primary cache line. The access request from the core includes such information. The secondary cache 200 can specify the request address based on information included in the access request from the core.

  The request core indicates a core that has issued an access request. The secondary cache 200 can identify the request core by identifying the core through which the access request has flowed. The request core may be specified by including information indicating the core that issued the access request in the access request from the core.

  The request opcode indicates the type of data specified by the access request from the core. As described above, there are two types of data: data relating to a machine instruction acquired by instruction fetch and data acquired from an address specified by an operand part of the machine instruction.

  In execution of a machine instruction, each core basically reads a machine instruction (instruction fetch), decodes the read machine instruction (decode), reads out operand data as a target of the machine instruction (operand fetch), Perform the operation and store the result. At this time, in the instruction fetch phase, each core requests data related to a machine instruction. In the operand fetch phase, operand data specified by the operand part of the machine instruction is requested. That is, the instruction control unit of each core requests one of these two types of data depending on the processing phase at the timing of issuing an access request (data request).

  The difference between the requests is reflected in the operation code indicating the access request issued by the instruction control unit. When the instruction control unit requests data to be stored in the instruction cache in the primary cache, an access request including an opcode such as “0x00 IF-MI-SH” is issued. On the other hand, when the instruction control unit requests data to be stored in the data cache in the primary cache, an access request including an operation code such as “0x01 OP-MI-SH” and “0x02 OP-MI-EX” is issued. The The secondary cache 200 can specify the request operation code by decoding these operation codes.

  The request way indicates the L1 way of the line in the primary cache that is the storage destination of data specified by the access request from the core. The access request from the core includes information indicating the L1 way. The secondary cache 200 can specify the request way based on the information. Since replacement is replacement of data on the same line, the line storing the data specified by the replacement request address and the line storing the data specified by the replacement target address are the same way. . Therefore, when the processing instruction related to the access request from the core is the L1 replacement order, the request way indicates the L1 way corresponding to the replacement request address and the L1 way corresponding to the replacement target address.

  Next, processing for acquiring information for specifying a lock target using information that can be specified by an access request from the core will be described. The processing differs depending on whether the processing instruction related to the access request from the core is a normal order or a replacement order. The process will be described with reference to FIGS. 3A and 3B.

  When the processing instruction related to the access request from the core is a normal order, information for specifying the lock target is acquired as shown in FIG. 3A. For example, for the L2 index and the L2 way, the corresponding entry in the L2 tag 221 is searched based on the request address specified from the information included in the access request from the core. When the data specified by the request address is stored in the secondary cache 200, an entry of the L2 tag 221 corresponding to the request address is found by the search. In this case, the L1 attribute information acquisition unit 214 acquires the L2 index and the L2 way of the line in which the data specified by the request address is stored based on the search process of the L2 tag 221.

  If no entry of the L2 tag 221 is found, the search target data is not stored in the secondary cache 200. In this case, the request processing unit 211 acquires the corresponding data from the main memory 400 and stores the acquired data in the secondary cache 200. At this time, the storage destination of the data acquired from the main memory 400 is specified before the data is acquired.

  Specifically, in a search process in the secondary cache 200 that is executed before acquiring data from the main memory 400, a set including a line in which the data is to be stored is specified. If there is a vacant line in the set, one of the vacant lines is specified as the data storage destination. Further, if there is no vacancy in the line in the set, a replacement process is executed. Then, by specifying the replacement target line, the data storage destination is specified. Hereinafter, such replacement processing is referred to as “L2 replacement”.

  The data storage location specified at this time is a target of processing requested based on the access request from the core. Therefore, the L1 attribute information acquisition unit 214 acquires an L2 index and an L2 way that specify the storage destination of the specified data as information for specifying the lock target. The acquisition may be performed at any timing before or after the data acquisition process from the main memory 400.

  In the search for the entry of the L2 tag 221, the L1 attribute information acquisition unit 214 may acquire an L1 index as information for specifying the lock target. When the L1 index is included in the L2 index, the L1 attribute information acquisition unit 214 may specify the L1 index from the acquired L2 index. Further, the L1 index may be specified from the logical address lower bits A1 included in the entry of the L2 tag 221.

  Further, as described above, the secondary cache 200 can search for an entry of the L1 tag copy 223 using the search result of the L2 tag 221. Thereby, when the corresponding entry is found in the L1 tag copy 223, the L1 attribute information acquisition unit 214 acquires the L1 way of the line corresponding to the corresponding entry as information for specifying the lock target.

  At this time, the L1 tag copy 223 is provided for each core and each data type. Therefore, the L1 attribute information acquisition unit 214 may acquire, from the L1 tag copy 223, information indicating the core that issued the access request and information indicating the type of data as information for specifying the lock target. .

  The L1 attribute information acquisition unit 214 can specify the type of data related to the access request from the request opcode that can be specified from the information included in the access request from the core. Furthermore, the L1 attribute information acquisition unit 214 can specify the L1 index from the request address that can be specified from the information included in the access request from the core. Therefore, the L1 attribute information acquisition unit 214 may acquire information indicating the type of data and an L1 index as information for specifying the lock target by specifying these.

  On the other hand, if the processing instruction related to the access request from the core is a replacement order, information for specifying the lock target is acquired as shown in FIG. 3B. For example, the L1 index of the line to be replaced is specified from the logical address lower bit A1 stored in the entry of the request address or the L2 tag 221. Further, the L1 way of the line to be replaced is specified from the request way. By specifying in this way, the L1 attribute information acquisition unit 214 can acquire an L1 index and an L1 way indicating a lock target.

  The L1 attribute information acquisition unit 214 refers to the entry of the L1 tag copy 223 indicated by the L1 index and the L1 way. The L1 attribute information acquisition unit 214 can acquire an L2 index and an L2 way indicating the line in the secondary cache 200 corresponding to the replacement target line in the primary cache from the referenced entry.

  The L1 tag copy 223 has an entry for each core and each data type. Therefore, the L1 attribute information acquisition unit 214 may acquire information indicating the lock target core and information indicating the data type as information indicating the lock target by referring to the L1 tag copy 223. Further, the L1 attribute information acquisition unit 214 may acquire an L1 index from the L1 tag copy 223 as information for specifying a lock target.

  Furthermore, the L1 attribute information acquisition unit 214 may acquire information indicating a lock target core from the request core. The L1 attribute information acquisition unit 214 may acquire information indicating the data type from the request opcode. The L1 attribute information acquisition unit 214 may acquire the L1 index from the request address.

  Finally, the lock target information including the core to be locked, the type of data, the L2 index, the L2 way, the L1 index, and the L1 way acquired in this way is held by the address holding unit 215. In this embodiment, while the lock target information is held in the address holding unit 215, the address lock control unit 213 is in a state where the target indicated by the lock target information is registered as the lock target.

  FIG. 5 is a diagram illustrating the operation at this time. As shown in FIG. 5, the data specified by the replacement request address is different from the data specified by the replacement target address. Therefore, in order to identify the line in the secondary cache that stores the data specified by the replacement target address, the corresponding entry in the L1 tag copy 223 is searched. Note that the entry on the L2 tag 221 labeled “hit” in FIG. 5 is an entry corresponding to a line storing data specified by the replacement request address. In addition, the entry on the L2 tag 221 described as “victim” in FIG. 5 is an entry corresponding to a line that stores data specified by the replacement target address.

  In the operation example shown in FIG. 3B, the L2 tag 221 is searched before the L1 tag copy 223 is searched in order to solve the synonym problem regarding the replacement request address (see Patent Document 2). Since other operations are the same as those in the normal order, the description thereof is omitted. In the present embodiment, the specification of the entry in the L1 tag copy 223 further considers the core and data type. FIG. 4 is a diagram in which the operation examples shown in FIGS. 3A and 3B are simplified and combined into one. In this way, the address to be locked is registered in the address lock control unit 213.

<Lock check>
Subsequently, a lock check by the address lock control unit 213 according to the present embodiment will be described with reference to FIGS. 6A, 6B, and 7. FIG. FIG. 6A illustrates the lock check when the processing instruction related to the access request from the core is in the normal order. FIG. 6B exemplifies the lock check when the processing instruction related to the access request from the core is a replacement order. FIG. 7 is a diagram summarizing the lock check shown in FIGS. 6A and 6B. FIG. 7 illustrates a lock check by the address lock control unit 213 according to the present embodiment.

  The address lock control unit 213 performs the lock check by determining whether or not the processing target related to the access request from the core is registered as the lock target. The lock check differs depending on whether the processing instruction related to the access request from the core is a normal order or a replacement order.

  When the processing instruction related to the access request from the core is in a normal order, a lock check is performed as shown in FIG. 6A. Specifically, the corresponding entry in the L2 tag 221 is searched based on the request address. When the data specified by the request address is stored in the secondary cache 200, an entry of the L2 tag 221 corresponding to the request address is found by the search. In this case, the lock determination unit 216 refers to the lock target information held in the address holding unit 215, and lock target information (entry) matching the L2 index and L2 way specified by the entry of the L2 tag 221. Search for. If no entry of the L2 tag 221 corresponding to the request address is found, the lock target information matching the L2 index and L2 way of the line specified as the data storage destination described above may be searched.

  When the lock target information is found as a result of the search, the lock determination unit 216 determines that the target of the access request from the core is locked. On the other hand, when the lock target information is not found, the lock determination unit 216 determines that the target of the access request from the core is not locked. Then, the lock determination unit 216 passes the determination result to the retry control unit 212. The retry control unit 212 controls the retry of the process related to the access request from the core according to the determination result.

  When the processing instruction related to the access request from the core is a replacement order, a lock check is performed as shown in FIG. 6B. Specifically, the lock determination unit 216 searches for the lock target information that matches the L1 index specified by the request address and the L1 way specified by the request way. The L1 index and L1 way used for these lock checks are the L1 index and L1 way of the line to be replaced in the primary cache, respectively. When the L1 index is not included in the request address, the L1 index specified from the entry searched from the L2 tag 221 may be used.

  As described above, in this embodiment, in the case of lock check for a replacement order, search processing in each cache tag is not required, and lock check can be performed only by information included in the access request from the core, compared to the conventional method. It is. Therefore, in this embodiment, the latency in the lock check for the replacement order is improved as compared with the conventional method.

  In the present embodiment, a lock check using a set of L2 index and L2 way or a set of L1 index and L1 way is exemplified in the lock check. These are examples of the lock check. In the lock check, any combination may be used for the lock check as long as it is information included in the lock target information. For example, information indicating a core that is not used in the present embodiment or information indicating the type of data may be used for the lock check. Information used for these lock checks may be appropriately selected depending on the nature of the instruction to be processed.

  FIG. 7 is a diagram showing the operation examples shown in FIGS. 6A and 6B in a simplified manner. In this way, the lock determination unit 216 performs a lock check. Further, FIG. 8 is a diagram in which the registration processing of the lock target address and the lock check processing described so far are simplified and combined into one. In the address lock control unit 213 according to the present embodiment, registration of lock targets and lock check are executed in this way.

<Circuit example>
Next, a circuit example of the address lock control unit 213 according to the present embodiment will be described with reference to FIG. FIG. 9 illustrates a circuit of the address lock control unit 213. As shown in FIG. 9, the address lock control unit 213 according to the present embodiment includes a match circuit 230, an entry selection circuit 231, a set / reset circuit 232, an input selection circuit 233, and a holding circuit 234. As shown in FIG. 9, the match circuit 230, the entry selection circuit 231, the set / reset circuit 232, and the holding circuit 234 are provided for each core.

  The match circuit 230 includes information indicating the lock target stored in each of four entries held by the hold circuit 234 described later, and information indicating the processing target obtained by the information flowing through the pipeline and the L2 tag 221. Determine if they match. Then, the match circuit 230 causes the determination result to flow on the pipeline. Note that the information indicating the lock target includes the information indicating the core, the information indicating the type of data, the L2 index, the L2 way, the L1 index, the L1 way, and the like described above. When the processing instruction related to the access request is a normal order, the information indicating the processing target is a set of an L2 index and an L2 way. Further, when the processing instruction related to the access request is a replacement order, the information indicating the processing target is the L1 index and the L1 way. The match circuit 230 corresponds to the lock determination unit 216 of the present embodiment.

  The entry selection circuit 231 indicates an entry in which data is registered next from among vacant entries among the entries held by the holding circuit 234. When there are a plurality of empty entries, the entry selection circuit 231 appropriately determines an entry in which data is registered next. Then, the entry selection circuit 231 outputs a signal for indicating the determined entry.

  The set / reset circuit 232 updates the status of each entry held by the holding unit 234. For example, “1” represents “valid” and “0” represents “invalid”.

  The input selection circuit 233 selects information to be stored in the holding circuit 234 described later from information flowing on the pipeline. Information stored in the holding circuit 234 is lock target information. The input selection circuit 233 selects information included in the lock target information stored in the holding circuit 234 from the information flowing on the pipeline, and passes the selected information to the holding circuit 234. Thereby, the input selection circuit 233 acquires information indicating the lock target. The input selection circuit 233 corresponds to the L1 attribute information acquisition unit 214 of the present embodiment.

  The information flowing on the pipeline includes the above-described request core, request address, request opcode, request way, L2 tag 221 search result, and L1 tag copy 223 search result. The input selection circuit 233 selects information for specifying the lock target as described with reference to FIGS. 3A and 3B from the information flowing on the pipeline, and passes the selected information to the holding circuit 234.

  As will be described later, the entry for storing the lock target information held in the holding circuit 234 shown in FIG. 9 does not have a field for storing information indicating the core to be locked. By preparing an entry for each core, the core to be locked is identified. Therefore, in the circuit example shown in FIG. 9, the input selection circuit 233 does not acquire information indicating the core to be locked, unlike the examples shown in FIGS. 3A and 3B.

  The input selection circuit 233 may be arranged at an appropriate position on the pipeline. For example, the input selection circuit 233 is arranged at an appropriate position on the pipeline where the search result of the L2 tag 221 and the search result of the L1 tag copy 223 can be acquired.

  The holding circuit 234 stores the lock target information acquired from the input selection circuit 233 in the entry. In FIG. 9, four entries are illustrated. As shown in FIG. 9, the entries held by the holding circuit 234 include a status field, an L2 index field, an IF status field, an IF way field, an OP status field, and an OP way field.

  In the status field, for example, 1-bit information indicating the validity of the corresponding entry is stored. For example, when the corresponding entry is valid, “1” is stored in the status field. On the other hand, if the corresponding entry is invalid, “0” is stored in the status field.

  In the L2 index field, for example, an 11-bit L2 index is stored. For example, a 5-bit L2 way is stored in the L2 way field. Further, in the IF way field and the OP way field, for example, a 2-bit L1 way is stored.

  In the IF status field, for example, 1-bit information indicating the validity of the IF way field in the entry is stored. When the L1 way is stored in the IF way field, “1” indicating validity is stored in the IF status field.

  In the OP status field, for example, 1-bit information indicating the validity of the OP way field in the entry is stored. When the L1 way is stored in the OP way field, “1” indicating validity is stored in the OP status field.

  The entry held in the holding circuit 234 corresponds to the address holding unit 215 of this embodiment. In addition, the holding circuit 234 acquires lock target information from the pipeline, the L2 tag 221, and the L1 tag copy 223. The circuit related to the acquisition corresponds to the L1 attribute information acquisition unit 214 of the present embodiment.

<Specific example>
Next, an operation example of the address lock control unit 213 according to the present embodiment in a specific scene will be described with reference to FIGS. 10 and 11, the step is abbreviated as “S”.

  In the specific scene illustrated in FIGS. 10 and 11, it is assumed that a cache miss does not occur in the secondary cache for the sake of simplicity. However, the application scene of this embodiment is not limited to such a scene. A cache miss hit may occur in the secondary cache. When a cache miss occurs, data acquisition processing from the main memory 400 and when replacement occurs, processing related to L2 replacement is executed.

  FIG. 10 shows an operation example when the second core holds data designated by the address (A). In the scene shown in FIG. 10, the process starts from a state in which the lock target is not registered.

  In step 1000, the first core issues a store instruction for data specified by the address (A) (ST (A)). When a store instruction is issued, the address lock control unit of the secondary cache performs a lock check to determine whether or not the issued store instruction can be executed. The lock check is illustrated by FIG. 6A. At this time, since the lock target is not registered, the store instruction issued by the first core is not locked. Therefore, in the secondary cache, the store instruction is executed.

  In step 1001, a lock target is registered based on the store instruction transferred to execution. The registration process is illustrated by FIG. 3A. At this time, at least the L2 index, the L2 way, and the L1 way are registered as information indicating the lock target.

  In step 1002, the request processing unit of the secondary cache invalidates the data specified by the address (A) with respect to the primary cache of the second core in order to maintain coherency between the primary cache and the secondary cache. Or request to write back. The request processing unit of the secondary cache detects that the second core holds corresponding data by referring to the L1 tag copy in the secondary cache. In the second core, the data specified by the address (A) is referred to by the L1 cache control unit referring to the status in the cache tag corresponding to the line storing the data specified by the address (A). It is determined whether or not is updated (dirty). When the data specified by the address (A) has been updated, the second core performs write back of the data based on the access request from the request processing unit of the secondary cache. If the data specified by the address (A) has not been updated, the second core executes invalidation of the data.

  In step 1003, the third core issues a data load instruction designated by the address (A) (LD (A)). At this point, it is assumed that the lock registered in step 1001 has not yet been released. That is, step 1003 is a process that occurs while the store instruction issued by the first core is being executed. When a load instruction is issued, the address lock control unit of the secondary cache performs a lock check to determine whether or not the issued load instruction can be executed. The lock check is illustrated by FIG. 6A. As shown in FIG. 6A, in this case, a lock check using the L2 index and the L2 way is performed.

  Here, the store instruction issued by the first core in step 1000 and the load instruction are processing for the same address (A). Therefore, the L2 index and L2 way specified by the load instruction match the L2 index and L2 way registered as lock targets. Therefore, the execution of the store instruction is canceled and retried by the retry control unit. Such retry continues until the lock registered in step 1001 is unlocked.

  FIG. 11 shows an operation example when the second core holds data designated by the address (B). In the scene shown in FIG. 11 as well, the process starts from a state in which no lock target is registered.

  In step 2000, the first core issues a data store instruction designated by the address (B) (ST (B)). When a store instruction is issued, the address lock control unit of the secondary cache performs a lock check to determine whether or not the issued store instruction can be executed. The lock check is illustrated by FIG. 6A. At this time, since the lock target is not registered, the store instruction issued by the first core is not locked. Therefore, the store instruction is executed.

  Next, in step 2001, the lock target based on the store instruction transferred to execution is registered. The registration process is illustrated by FIG. 3A. At this time, at least the L2 index, the L2 way, and the L1 way are registered as information indicating the lock target.

  In step 2002, the request processing unit of the secondary cache invalidates the data specified by the address (B) with respect to the primary cache of the second core in order to maintain coherency between the primary cache and the secondary cache. Or request to write back. Since this point is the same as the operation shown in FIG.

  In step 2003, while the store instruction (ST (B)) issued by the first core is being executed, a data load instruction specified by the address (A) is issued by the second core (LD ( A)). Here, it is assumed that the address (A) and the address (B) are the same L1 index. Further, it is assumed that there is no space in the line designated by the L1 index, L1 replacement occurs, and the line storing the data designated by the address (B) is selected as the replacement target line.

  In this case, the load instruction is a process instruction related to the access request based on the L1 replacement. When the load instruction is issued, the address lock control unit of the secondary cache performs a lock check to determine whether or not the load instruction with L1 replacement can be executed. The lock check is illustrated by FIG. 6B. As shown in FIG. 6B, in this case, a lock check is performed using the L1 index and the L1 way included in the request from the core.

  Here, in step 2001, the L1 index and the L1 way of the second core line storing the data specified by the address (B) are registered as information indicating the lock target. The second core line that stores the data specified by the address (B) is the line to be replaced generated in step 2003. For this reason, the L1 index and L1 way registered as information indicating the lock target coincide with the L1 index and L1 way to be replaced generated in step 2003. Therefore, the load instruction accompanied with the L1 replacement is canceled and retried by the retry control unit. Such retry continues until the lock registered in step 2001 is unlocked.

§4 Actions and effects according to this embodiment Finally, actions and effects according to this embodiment will be described with reference to FIGS. 12A, 12B, 13A, and 13B.

  FIG. 12A illustrates the range locked by the conventional method. FIG. 12B illustrates the range locked by this embodiment.

  As shown in FIG. 12A, when a lock target is specified by a full-size address or a set of L2 index and L2 way, the corresponding line on the secondary cache is locked. Therefore, all accesses to the line on the secondary cache are locked. On the other hand, as shown in FIG. 12B, in addition to the conventional address information, information indicating the L1 way, core, data type information, and the like are further added, and the lock target is designated. The corresponding line on the primary cache is locked. Therefore, access in other cores is not locked.

  Therefore, in the present embodiment, the lock target range can be set in more detail as compared with the conventional method. Thereby, in this embodiment, compared with the conventional method, the possibility of parallel processing can be improved more.

  The increase in the possibility of parallel processing will be described with reference to FIGS. 13A and 13B. FIG. 13A and FIG. 13B illustrate the relationship between lock and replacement when L1 replacement occurs in the first core and the second core for the line storing the data specified by the address A. FIG. 13A illustrates the relationship between lock and replacement in the conventional method. FIG. 13B illustrates the relationship between lock and replacement in the present embodiment.

  In the conventional method, a lock target is expressed by a full-size address or a set of an L2 index and an L2 way. Here, both the replacement targets generated in the first core and the second core are the address A. Therefore, for example, if the L1 replacement in the second core is processed first, the L1 replacement in the first core cannot be processed due to the lock registered based on the L1 replacement in the second core.

  On the other hand, in the present embodiment, the lock target is represented by information indicating the L1 index, L1 way, core, information indicating the type of data, and the like. Therefore, the L1 replacement in the first core can be removed from the lock executed based on the L1 replacement in the second core. Therefore, in the present embodiment, the process relating to the L1 replacement in the first core can be executed even while the process relating to the L1 replacement in the second core is being executed. Therefore, in this embodiment, the possibility of parallel processing can be further increased as compared with the conventional method.

  Further, in the conventional method, the lock check is performed after the search for the L1 tag copy is executed at the time of the lock check of the address to be replaced by the L1. On the other hand, in this embodiment, when performing a lock check of an address that is a target of L1 replacement, a lock check can be performed using the L1 index and the L1 way included in the request. That is, in this embodiment, the search for the L1 tag copy can be omitted in the lock check. Therefore, according to the present embodiment, it is possible to improve the delay that occurs during the lock check of the address that is the target of L1 replacement.

  As shown in FIG. 3A, when registering an address to be locked in a normal order, a delay is caused by searching for an L1 tag copy. However, the process of registering the lock target address is a process performed in parallel with the execution of the access request related to the lock. For this reason, the delay hardly affects the processing speed of the entire processing. On the other hand, the lock check process is executed before the execution of the access request related to the lock. For this reason, the delay of the lock check directly affects the processing speed of the entire process. Therefore, according to the present embodiment, the processing speed of the entire process is also improved.

100, 110, 1m0 Processor core 101, 111, 1m1 Instruction control unit 102, 112, 1m2 Operation execution unit 103, 113, 1m3 Primary cache 104 L1 cache control unit 104a Address conversion unit 104b Request processing unit 105 L1 instruction cache 105a L1 Tag 105b L1 data 105 L1 operand cache 106a L1 tag 106b L1 data 200 Secondary cache 210 L2 cache control unit 211 Request processing unit 212 Retry control unit 213 Address lock control unit 214 L1 attribute information acquisition unit 215 Address holding unit 216 Lock determination unit 220 L2 cache data part 221 L2 tag 222 L2 data 223 L1 tag copy 230 Match circuit 231 Entry selection circuit 232 Set / reset circuit 233 Input selection circuit 234 Holding circuit

On the other hand, when the lock check is executed for the replacement target address in the access request based on the L1 replacement, the address lock control unit 831 reads the L1 tag copy 820 from
An L2 index and an L2 way corresponding to the replacement target address are acquired. Specifically, the address lock control unit 831 searches the L1 tag copy 820 for a line that matches the information included in the access request based on the L1 replacement. Note that the address (A) and the L1 way (A) in FIG. 16 are information included in the access request based on the L1 replacement. Then, the address lock control unit 831 acquires the L2 index and the L2 way corresponding to the replacement target address from the line indicated by the search result. Note that the L2 index (B) and the L2 way (B) in FIG. 16 are the L2 index and the L2 way corresponding to the replacement target address.

Claims (4)

A plurality of arithmetic processing units including a first cache memory, each performing an operation and outputting an access request;
A second cache memory shared by the plurality of arithmetic processing units, each storing data calculated by the plurality of arithmetic processing units;
Acquire attribute information related to the first cache memory of the access request source of the control object including way information indicating the way of the cache block of the first cache memory to be controlled in the arithmetic processing unit of the access request source of the control object An acquisition unit to
A holding unit that holds address information related to a control target address that specifies a cache block that is a target of the control target access request in the second cache memory, and the acquired attribute information;
A replacement target address included in an access request related to a replacement request issued by any of the plurality of arithmetic processing units with respect to the first cache memory, and way information indicating a way of a cache block to be replaced in the first cache memory; A control unit for controlling an access request related to the replacement request for the cache block of the second cache memory specified by the address information to be controlled and the attribute information,
An arithmetic processing device comprising: The acquisition unit further acquires at least one of information indicating an arithmetic processing unit of the access request source to be controlled and information indicating a type of data to be a target of the access request.
The arithmetic processing apparatus according to claim 1. A plurality of arithmetic processing units including a first cache memory, each performing an arithmetic operation and outputting an access request, and a plurality of arithmetic processing units each holding data calculated by the plurality of arithmetic processing units. A control method of an arithmetic processing unit comprising: a second cache memory;
The acquisition unit included in the arithmetic processing unit includes the way information indicating the way of the cache block of the first cache memory to be controlled in the arithmetic processing unit of the access request source to be controlled. Obtaining attribute information about the first cache memory;
A holding unit included in the arithmetic processing unit holds address information related to a control target address that specifies a cache block that is a target of the control target access request in the second cache block and the acquired attribute information. ,
The control unit included in the arithmetic processing unit includes a replacement target address included in an access request related to a replacement request issued by any of the plurality of arithmetic processing units with respect to the first cache memory, and a replacement target in the first cache memory. Controlling an access request related to the replace request for the cache block of the second cache memory specified by the address information to be controlled and the attribute information, based on way information indicating a way of the cache block of
A method for controlling an arithmetic processing unit. The acquisition unit further acquires at least one of information indicating an arithmetic processing unit of the access request source to be controlled and information indicating a type of data to be a target of the access request.
The control method of the arithmetic processing apparatus of Claim 3.

Images