TWI528496B - Manufacturing method of semiconductor device - Google Patents

Description

Semiconductor component manufacturing method

The present invention relates to the field of semiconductor device fabrication, and more particularly to a connection method for a contact hole.

In the manufacturing process of semiconductors, photolithography is an indispensable technology, which mainly forms a designed pattern, such as a circuit pattern, a layout pattern of a planting area, and a contact hole unit pattern. Or a plurality of reticle, and then transferring the pattern on the reticle to the photoresist layer on a substrate by an exposure and development step, thereby accurately transferring the complicated layout pattern to In a semiconductor wafer or a thin film layer thereon. Then, with the subsequent corresponding ion implantation process or etching process, etc., a complicated circuit structure can be completed.

However, in the same film layer, when two or more patterns are formed to partially overlap in position, it is possible to repeatedly etch the same region, thereby affecting the pattern contour of the overlapping region, and even impairing the underlying overlapping region. Other components.

In order to solve the above problems, the present invention provides a method of fabricating a semiconductor device. First of all, Forming at least one gate structure and a plurality of source/drain regions on a substrate, and then forming a dielectric layer on the substrate, and then the dielectric layer on the gate structure and each of the source/drain regions Forming a first contact hole and a second contact hole respectively, and forming a third contact hole in the dielectric layer, wherein the third contact hole and the first contact hole and the second contact hole respectively have a portion overlapping.

The present invention further provides a method of fabricating a semiconductor device. First, at least one gate structure and a plurality of source/drain regions are formed on a substrate, and then a dielectric layer is formed on the substrate, and then a dielectric layer is formed in the dielectric layer on the source/drain region. a contact hole; and a second contact hole formed in the dielectric layer, and the second contact hole partially overlaps the first contact hole.

According to the manufacturing method provided by the present invention, since the number of times of contact hole formation is small at the time of formation, it is possible to effectively reduce the situation in which the inside of the contact hole is destroyed by multiple etchings.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

For the convenience of description, the drawings of the present invention are only for the purpose of understanding the present invention, and the detailed proportions thereof can be adjusted according to the design requirements. As described in the text for the relative relationship between the relative elements in the graph, everyone in the field should It can be understood that it refers to the relative position of the object, and therefore can be turned over to present the same member, which are all within the scope of the present disclosure, which will be described first.

Please refer to FIG. 1 to FIG. 7 , which are schematic cross-sectional views showing a process of a semiconductor device according to a first preferred embodiment of the present invention. As shown in FIG. 1, a substrate 10 is first provided, such as a germanium substrate, a germanium-containing substrate, a tri-five-layered germanium substrate (eg, GaN-on-silicon), and a graphene-coated substrate (graphene-on- a semiconductor substrate such as a silicon-on-insulator (SOI) substrate, the substrate 10 is formed with at least one semiconductor element, such as a metal oxide semiconductor (MOS) transistor, and the MOS transistor has A gate structure 12, and a plurality of source/drain regions 14 are located in the substrate 10 on opposite sides of the gate structure. A contact etch stop layer (CESL) 16 and a dielectric layer, such as an interlevel dielectric layer 18, are sequentially formed on the substrate 10, followed by a planarization step, such as chemical mechanical polishing ( The chemical mechanical polishing removes the excess inter-substrate dielectric layer 18 and exposes the gate structure 12. The gate structure 12 can be a metal gate or a polysilicon gate, etc., and is not limited thereto, and the preferred embodiment can selectively connect the interlayer dielectric layer 18 on the source/drain region 14. The contact structure 20 is formed in contact with the contact etch stop layer 16, wherein the contact structure 20 can be a pole contact or a slot contact and directly contact the source/drain region 14.

A top dielectric layer 22 and a photoresist layer 25 are then sequentially formed on the surface of the interlevel dielectric layer 18. It should be noted that the preferred embodiment can be selectively inter-layered. A mask layer 21 is formed between the electrical layer 22 and the interlayer dielectric layer 18, such as a nitrogen doped carbon doped carbide (NDC) or the like, for use as an etch stop layer. In addition, the photoresist layer 25 may be a single layer or a plurality of layers of photoresist material, and in the preferred embodiment, the photoresist layer 25 is a composite layer. For example, a bottom photoresist layer 24 and a photoresist layer 26 may be selectively formed on the surface of the inter-top dielectric layer 22, and then a top photoresist layer 28 may be formed, so that the multilayer photoresist layer may be used to enhance the subsequent The quality of the contact holes formed in the underlying inter-layer dielectric layer 22 during the etching process. In other words, etching with a multilayer photoresist layer can transfer the etched pattern from one layer to another, and etching is performed using only a single photoresist layer, the pattern alignment is more precise, and the formed contact holes are relatively difficult. Produce defects. Of course, the present invention does not limit the number of layers of the photoresist layer, and only one layer of the photoresist layer is required.

Regarding the photoresist layers used in the present invention, the bottom photoresist layer 24 may be a positive or negative photoresist and comprise an organic material. For example, I-line photoresists preferably have a thickness between 1500 and 2500 angstroms. As is well known to those skilled in the art, I-line photoresist materials are particularly sensitive to light sources of 365 nanometers (nm) wavelengths; The photoresist layer 26 may be a silicon-containing hard-mask bottom anti-reflection coating (SHB), and the composition thereof is an organic silicon polymer or a polysilicon containing germanium. The thickness of the polysilane is preferably between 300 and 700 angstroms. The top photoresist layer 28 can be a positive photoresist or a negative photoresist, such as an ArF photoresist layer, which is suitable for exposure of a light source at a wavelength of 193 nm. It is preferably between 500 and 1000 angstroms.

Then, a first photomask is used to perform a photo-etching process, for example, The top photoresist layer 28 is exposed and developed, and the inter- photoresist layer 26, the bottom photoresist layer 24, and the inter-layer dielectric layer 22 are sequentially etched. After the photoresist layer 25 is removed, as shown in FIG. 2, a first contact hole 32 is formed in the inter-layer dielectric layer 22, wherein the first contact hole 32 is located above the gate structure 12 and exposed. Cover layer 21. Then, in the same step, a photoresist layer is formed, for example, a bottom photoresist layer (not shown) is formed again, an inter-resistive layer (not shown) and a top photoresist layer (not shown) are interposed between the top dielectric layers. 22, then a second mask is used to expose and develop the top photoresist layer, and the inter-photoresist layer, the bottom photoresist layer and the inter-layer dielectric layer 22 are sequentially etched. After removing the photoresist layer, as shown in FIG. 3, a second contact hole 34 is formed in the inter-layer dielectric layer 22, wherein the second contact hole 34 is located above the source/drain region 14, due to the present invention. The middle contact structure 20 can be located above the source/drain region 14, so that the second contact hole 34 can expose the source/drain region 14 or the contact structure 20 in a subsequent etching process, notably, in the present invention, The first contact hole 32 and the second contact hole 34 do not contact each other.

Next, in the same step, as shown in FIG. 4, a photoresist layer 27 is formed, for example, a bottom photoresist layer 24, an inter- photoresist layer 26 and a top photoresist layer 28 are formed on the inter-layer dielectric layer 22, Then, a third mask is used to expose and develop the top photoresist layer 28, and as shown in FIG. 5, the photoresist layer 26, the bottom photoresist layer 24, and the interlayer dielectric layer 22 are sequentially etched, and then removed. The remaining inter-resistive layer 26 and the mask layer 21 or the inter-layer dielectric layer 22 in each contact hole are formed between the first contact hole 32 and the second contact hole 34 as shown in FIG. The third contact hole 36 is in the inter-layer dielectric layer 22, wherein the third contact hole 36 partially overlaps the first contact hole 32 and the second contact hole 34, respectively. Then, the bottom photoresist layer 24 and the mask layer 21 located in each contact hole are removed, as shown in FIG. A barrier layer (not shown) and a conductive layer 40, such as tungsten (tungsten), aluminum or copper, are further filled and planarized for connecting the gate structure 12 to the contact. Structure 20 is either source/drain region 14. Finally, a multiple metal interconnect process is performed to form a desired metal interconnect structure (not shown) on the interlayer dielectric layer 22, such as a first metal wiring layer and a second metal wiring layer. n metal wire layer.

8 is a top view of the semiconductor structure of the present invention. As shown in FIG. 8 , taking the contact structures 20 as strip contacts as an example, the present invention forms a plurality of first contact holes 32 on the gate structure 12 . A second contact hole 34 is then formed on each contact structure 20 or source/drain region 14, and then a third contact hole 36 is formed which serves as an element for connecting the first contact hole 32 and the second contact hole 34. The size of the first contact hole 32 and the second contact hole 34 is not limited to that shown in the drawing, and the width thereof may be slightly larger than the gate structure 12 or the contact structure 20. The present invention is characterized in that the third contact hole 36 is formed behind the first contact hole 32 and the second contact hole 34, and when the first contact hole 32 and the second contact hole 34 are formed, the two positions do not contact each other. And there is no overlapping portion, and the third contact hole 36 formed later connects the first contact hole 32 and the second contact hole 34, so that the positions of the contact holes in the etching process can be reduced to overlap each other and cause overlapping. Part of the etching is repeated multiple times to destroy the underlying components such as the gate structure 12 or the contact structure 20. It should be noted that some of the first contact holes 32 and the second contact holes 34 of the present invention do not overlap with the third contact holes 36. The tangent line AA' corresponds to a process cross-sectional view showing the semiconductor elements of Figs. 1 to 7 of the present invention. The tangent line BB' corresponds to a process cross-sectional view showing the semiconductor elements of the ninth to twelfthth drawings of the present invention.

In the above embodiment, the first contact hole 32 is formed before the second contact hole 34 is formed. However, the present invention is not limited thereto, that is, the second contact hole 34 may be formed first, and then the first contact hole 32 may be formed. Or the first contact hole 32 and the second contact hole 34 are simultaneously formed by the same mask. In more detail, in the above embodiment, the present invention uses a double patterning lithography (DPL) technique to form the first contact hole 32 and the second contact hole 34 disposed along a first direction. Exposing and developing the photoresist layer over the gate structure 12, etching the inter-layer dielectric layer 22 over the gate structure 12, then exposing and developing the photoresist layer over the source/drain region 14, and then etching The inter-top dielectric layer 22 is located above the source/drain region 14, that is, a total of two exposure processes and two etching steps (2P2E). Alternatively, the photoresist layer over the gate structure 12 can be exposed, followed by direct exposure of the photoresist layer over the source/drain region 14, followed by development and etching steps, ie, two exposures and one etching step. (2P1E). Then, a third contact hole 36 disposed along a second direction is formed to connect the elements of the first contact hole 32 and the second contact hole 34, and the first direction and the second direction are not parallel to each other. Of course, the present invention is not limited to the above-mentioned process steps, and different steps may be performed according to actual needs, only the first contact hole 32 and the second contact hole 34 formed are not in contact with each other, and then formed. The three contact holes 36, which partially overlap the first contact holes 32 and the second contact holes 34, are all within the scope of the present invention.

In addition, the mask layer 21 in the present invention can also serve as a stop layer for the subsequent etching step, protecting the underlying gate structure 12 or the contact structure 20 from being damaged by etching. Therefore, the present invention forms the first contact hole 32, Two contact holes 34 and third contact holes 36 When the first contact hole 32, the second contact hole 34 and the third contact hole 36 are completed, the mask layer 21 in each contact hole is removed by wet etching, for example, after the first contact hole 32, the second contact hole 34 and the third contact hole 36 are completed. The bottom gate structure 12, the source/drain region 14 or the contact structure 20 is exposed, but the above is only one embodiment of the present invention, and the present invention is not limited thereto, and the present invention is also applicable to other semiconductor processes, for example, A via plug and wire used to form a multiple metal interconnect process.

In summary, in the method for fabricating a semiconductor device according to the present invention, the first contact hole and the second contact hole are respectively connected to the gate structure and the source/drain region, and the two are connected by the third contact hole, When each contact hole is formed, the number of times of overlapping regions is small, so that damage to the elements under each contact hole is small, and the manufacturing method provided by the present invention contributes to improving the yield of the semiconductor device process.

The various embodiments of the semiconductor device of the present invention are described below, and the following description is mainly for the sake of simplification of the description of the embodiments, and the details are not repeated. In addition, the same elements in the embodiments of the present invention are denoted by the same reference numerals to facilitate the comparison between the embodiments.

9 to 12 are schematic cross-sectional views showing the process of the semiconductor device of the second preferred embodiment of the present invention. This embodiment is the same as the first embodiment in the fabrication of a semiconductor device, and only the differences will be described below. First, as shown in FIG. 1, a semiconductor device having a contact structure 20 on the source/drain region 14 is taken as an example. Next, as shown in FIG. 9, a first contact hole 42 is formed on the top layer by a first mask. In the dielectric layer 22, And the first contact hole 42 is located above the source/drain region 14. Next, as shown in FIG. 10, a photoresist layer 47 is formed on the inter-layer dielectric layer 22 and the first contact hole 42, and the photoresist layer 47 is, for example, a bottom photoresist layer 24, a photoresist layer 26, and a top. Photoresist layer 28. Then, a second mask is used to expose and develop the top photoresist layer 28, and then, as shown in FIG. 11, the inter- photoresist layer 26, the bottom photoresist layer 24, and the inter-layer dielectric layer 22 are sequentially etched, and then removed. The remaining inter-resistive layer 26 and the mask layer 21 or the inter-layer dielectric layer 22 in each contact hole, as shown in FIG. 12, form a second contact hole 44 in the inter-top dielectric layer 22, wherein The second contact hole 44 partially overlaps the first contact hole 42. Finally, a conductive layer (not shown) is filled in the first contact hole 42 and the second contact hole 44. The features, material characteristics, and manufacturing methods of the remaining components are similar to those of the first preferred embodiment described above, and thus are not described herein again.

In the above process, the first contact hole 42 is located above the source/drain region 14, but the invention is not limited thereto, and the first contact hole 42 may also be formed above the gate structure 12. In other words, the present embodiment is different from the first preferred embodiment of the present invention in that the first contact hole 42 only needs to be located above one of the gate structure 12 or the source/drain region 14. The second contact hole 44 connects the gate structure 12 to the source/drain region 14 (or the contact structure 20). Since only the overlapping portions of the first contact hole 42 and the second contact hole 44 are repeatedly etched, for each contact The damage caused by the components under the hole is also small, and the manufacturing method provided by the embodiment helps to improve the yield of the semiconductor device process.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Base

12‧‧‧ gate structure

14‧‧‧Source/bungee area

16‧‧‧Contact etch stop layer

18‧‧‧Interlayer dielectric layer

20‧‧‧Contact structure

21‧‧‧ mask layer

22‧‧‧Interlayer dielectric layer

24‧‧‧ bottom photoresist layer

25‧‧‧Photoresist layer

26‧‧ ‧ photoresist layer

27‧‧‧Photoresist layer

28‧‧‧Top photoresist layer

32‧‧‧First contact hole

34‧‧‧Second contact hole

36‧‧‧ third contact hole

40‧‧‧ Conductive layer

42‧‧‧First contact hole

44‧‧‧Second contact hole

47‧‧‧Photoresist layer

1 to 7 are schematic cross-sectional views showing a process of a semiconductor device according to a first preferred embodiment of the present invention.

Figure 8 is a top plan view of the semiconductor structure of the present invention.

9 to 12 are schematic cross-sectional views showing a process of a semiconductor device according to a second preferred embodiment of the present invention.

10‧‧‧Base

12‧‧‧ gate structure

20‧‧‧Contact structure

32‧‧‧First contact hole

34‧‧‧Second contact hole

36‧‧‧ third contact hole

Claims (15)

A method of fabricating a semiconductor device, comprising the steps of: forming at least one gate structure and a plurality of source/drain regions on a substrate; forming a dielectric layer on the substrate; and forming the gate structure and each of the source/german Forming a first contact hole and a second contact hole in the dielectric layer on the polar region; forming a photoresist layer in the first contact hole and the second contact hole; and patterning the photoresist layer, And forming a third contact hole in the dielectric layer, and the third contact hole partially overlaps the first contact hole and the second contact hole respectively. The manufacturing method of claim 1, wherein the first contact hole and the second contact hole are formed in different steps. The manufacturing method of claim 1, wherein the first contact hole and the second contact hole are formed in the same step. For example, the manufacturing method of the patent scope 1 further includes separately forming a corresponding contact structure on each of the source/drain regions. The manufacturing method of claim 4, wherein the contact structure comprises a pole contact and a slot contact. The manufacturing method of claim 1, wherein the first contact hole and the second contact The hole and the third contact hole are formed in the interlayer dielectric layer by a photo-etching process. The manufacturing method of claim 1, wherein the first contact hole and the second contact hole are not in direct contact with each other. The manufacturing method of claim 1, further comprising forming a conductive layer filled in the first contact hole, the second contact hole, and the third contact hole. The manufacturing method of claim 1, wherein the gate structure comprises a polysilicon gate and a metal gate. The manufacturing method of claim 1, wherein the third contact hole is formed after the first contact hole and the second contact hole are completed. A method of fabricating a semiconductor device, comprising the steps of: forming at least one gate structure and a plurality of source/drain regions on a substrate; forming a dielectric layer on the substrate; and forming the dielectric on the source/drain region Forming a first contact hole in the electrical layer; forming a photoresist layer in the first contact hole; and patterning the photoresist layer to form a second contact hole in the dielectric layer, and the second contact The hole partially overlaps the first contact hole. The manufacturing method of claim 11 further includes separately forming a corresponding contact structure on each of the source/drain regions. The manufacturing method of claim 12, wherein the second contact hole is located above the gate structure and the contact structure. The manufacturing method of claim 11 further includes forming a conductive layer filled in the first contact hole and the second contact hole. The manufacturing method of claim 11, wherein the second contact hole is formed after the first contact hole is completed.