TWI523190B - 多晶粒堆疊結構 - Google Patents

多晶粒堆疊結構 Download PDF

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TWI523190B
TWI523190B TW102146464A TW102146464A TWI523190B TW I523190 B TWI523190 B TW I523190B TW 102146464 A TW102146464 A TW 102146464A TW 102146464 A TW102146464 A TW 102146464A TW I523190 B TWI523190 B TW I523190B
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die
pad
input pad
electrically connected
dies
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梁杰
鈴木孝太郎
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南亞科技股份有限公司
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Description

多晶粒堆疊結構
本發明是有關於一種積體電路結構，且特別是有關於一種多晶粒堆疊結構。
多晶粒堆疊結構常應用於需要在縮小的封裝尺寸中增加記憶體密度及/或裝置性能的電子產品。
圖1繪示QDP(quad-die package，四晶粒封裝)類型的傳統多晶粒堆疊結構，其在晶粒間具有基於CS(Chip-Select，晶粒選擇)墊(pad)的「階梯型(ladder-style)」連接。此種結構目前應用於DDR3 SDRAM(Double-Data-Rate Three Synchronous Dynamic Random Access Memory)。
請參照圖1，此結構包括垂直由下至上堆疊的四個晶粒12、14、16與18。各晶粒12、14、16或18具有四個CS墊，包括：用於該晶粒本身的輸入(input)的CS0墊101、用於高一層的晶粒(若存在)的輸入的CS1墊103、用於高兩層的晶粒(若存在)的輸入的CS2墊105，以及用於高三層的晶粒(若存在)的輸入的CS3墊107，其中晶粒12、14、16與18的CS墊101、103、105與107 是透過基底通孔(through-substrate via，TSV)作階梯型連接。具體而言，在第i晶粒(i=2~4)14、16或18中，第j個CS墊(j=1~3)101、103或105電性連接至第(i-k)晶粒(k=1~i-1)的第(j+k)個CS墊，但其中j+k4。
然而，DDR3 SDRAM的階梯型連接會使CS/ZQ墊之間有很大的輸入電容(Cin，input-capacitance)差異。此現象很可能歸因於各個CS墊的負載(loading)的差異。如圖1所示，CS0墊101有0基底通孔/1墊層的負載，CS1墊103有1基底通孔/2墊層的負載，CS2墊105有2基底通孔/3墊層的負載，CS3墊107有3基底通孔/4墊層的負載。亦即，相較於第n個CS墊，第(n+1)個CS墊多出1基底通孔/1墊層的負載。
有鑑於此，本發明提供一種多晶粒堆疊結構，其能夠降低在晶粒輸入墊之間的輸入電容(Cin)差異。
本發明的多晶粒堆疊結構包括N個(N2)垂直堆疊的晶粒。每個晶粒包括N個晶粒輸入墊(input pads)，其中有一特定輸入墊用於該晶粒本身的輸入。在底晶粒上方的每個晶粒的特定墊透過至少一基底通孔(through-substrate via)電性連接至底晶粒的特定輸入墊以外的不同輸入墊，且當不在與底晶粒相鄰的晶粒中時，亦透過底晶粒上方的每個下方晶粒的不同輸入墊作上述電性連接。底晶粒的特定輸入墊電性連接至上方的單或多個晶粒的至 少一個輸入墊，所述至少一個輸入墊並非任何上方晶粒的特定輸入墊，且未電性連接至任何上方晶粒的特定輸入墊。
在一實施例中，所述晶粒輸入墊是晶粒選擇(CS)墊。
在一實施例中，所述至少一基底通孔包括至少一矽通孔(through-silicon via)。
在一實施例中，所述N個晶粒包括動態隨機存取記憶體(DRAM)晶粒，其例如是DDR3 DRAM晶粒。
由於底晶粒的特定輸入墊電性連接至上方的單或多個晶粒的至少一個輸入墊，所述至少一個輸入墊並非任何上方晶粒的特定輸入墊，且未電性連接任何上方晶粒的特定輸入墊，因此至少可降低底晶粒(在先前技術中具有最低Cin)的特定輸入墊與上方晶粒的特定輸入墊之間的Cin差異。因此，本發明可減少外部輸入CS訊號的變異以降低晶粒對晶粒的CS針腳安裝/維持時間(setup/holding timing)的變異，並減少使用ZQ墊的校正(calibration)結果的變異。
當晶粒的晶粒輸入墊具有前述階梯型連接時，甚至可使所有晶粒的特定輸入墊具有實質相同的Cin或實質上無Cin差異。此種實施例如下所述。N個晶粒包括由下至上的第一至第N晶粒，其中第一晶粒為底晶粒。在每個晶粒中，N個輸入墊包括依序排列的第一至第N輸入墊，其中第一輸入墊用於該晶粒本身的輸入。在各第i晶粒(i=2~N)中，第j輸入墊(j=1~N-1)電性連接各第(i-k)晶粒的第(j+k)墊輸入，但其中j+kN。第一晶粒的特定輸 入墊透過在第一晶粒中的基底通孔電性連接第二晶粒的第N輸入墊。各第m晶粒(m=2~N-1)中的特定輸入墊亦透過在第m晶粒中的基底通孔電性連接第(m+1)晶粒的第N輸入墊。第N晶粒的特定輸入墊亦電性連接在第N晶粒中第N輸入墊上方的基底通孔。
在上述實施例中，所述晶粒輸入墊例如是晶粒選擇墊。
在上述實施例中，各第m晶粒的所述特定輸入墊可透過下述電路電性連接至第(m+1)晶粒的第N輸入墊，此電路包括在所述第m晶粒中的金屬層的延伸部與基底通孔。
在上述實施例中，N例如等於4。
在上述實施例中，所述至少一基底通孔可包括至少一矽通孔。
在上述實施例中，所述N個晶粒可包括DRAM晶粒。所述DRAM晶粒可包括DDR3 DRAM晶粒。
在以上實施例中，因為每個晶粒的特定輸入墊電性連接至相同數目的其他輸入墊與相同數目的TSV，所以在晶粒的特定輸入墊之間實質上沒有Cin差異。
為讓本發明的上述與其他物件、特徵與優點能更明顯易懂，將在下文伴隨附圖詳細描述較佳實施例。
12、14、16、18‧‧‧晶粒
101、103、105、107、CS0、CS1、CS2、CS3‧‧‧輸入墊
100、110、120‧‧‧金屬層
110a‧‧‧延伸部
130‧‧‧基底通孔
140‧‧‧銲球
150‧‧‧箭頭
圖1繪示先前技術的QDP型多晶粒堆疊結構，其在晶粒間具 有利用CS(Chip-Select)墊的階梯式連接。
圖2繪示本發明一實施例的QDP型多晶粒堆疊結構，其在晶粒間亦具有基於CS(Chip-Select)墊的階梯式連接。
下文將以實施例進一步解釋本發明，其並不意圖為限制本發明的範疇。舉例來說，雖然在實施例中N等於4，但N亦可小於或大於4，例如2或8。
圖2繪示本發明一實施例的QDP型多晶粒堆疊結構，其在晶粒間具有基於CS墊的階梯型的連接。
在晶粒12、14、16與18的每一者中，金屬層100已經被定義成CS0墊101、CS1墊103、CS2墊105、CS3墊107、以及其他接觸墊(未繪示，包括ZQ墊等)，金屬層110可以是晶粒12、14、16或18的第三金屬層(M3)。
階梯型連接將在以下詳細描述。
在第二晶粒14中，用於第二晶粒14的輸入的做為前述特定輸入墊的CS0墊101透過以下的導電路徑電性連接至第一晶粒12的CS1墊103：銲球140、第一晶粒12中的TSV 130、第一晶粒12中的第一金屬(M1)層120、第一晶粒12中的第二金屬(M2)層110，以及分別位在第二晶粒14的CS0墊101與銲球140之間、銲球140與TSV 130之間、M1層120與M2層110之間、M2層110與第一晶粒12的CS1墊103之間的特定的中間金屬層及插 塞。此種連接結構可視為一階階梯(1-step ladder)。為描述簡潔起見，以下敘述將不提及導電路徑中對輸入電容影響較小的銲球140、M1層120、M2層110、中間金屬層及插塞。
在第三晶粒16中，CS0墊101透過第二晶粒14中的TSV 130與第二晶粒14的CS1墊103電性連接，且透過第一晶粒12中的TSV 130與第一晶粒12的CS2墊105電性連接。此種連接結構可視為二階階梯。
在第四晶粒18中，CS0墊101透過第三晶粒16中的TSV 130與第三晶粒16的CS1墊103電性連接，再透過第二晶粒14中的TSV 130與第二晶粒14的CS2墊105電性連接，再透過第一晶粒12中的TSV 130與第一晶粒12的CS3墊107電性連接。因此，第四晶粒18的CS0墊101與其他三個CS墊以及三個TSV 130電性連接。此種連接結構可視為三階階梯。
此外，第四晶粒18的CS1墊103透過第三晶粒16中的TSV 130與第三晶粒16的CS2墊105電性連接，再透過第二晶粒14中的TSV 130與第二晶粒14的CS3墊107電性連接而形成二階階梯，且第四晶粒18的CS2墊105透過第三晶粒16中的TSV 130與第三晶粒16的CS3墊107電性連接而形成一階階梯。上述輸入墊以及第四晶粒18的CS3墊107並不在QDP類型的傳統多晶粒堆疊中使用，如圖1所示。
然而，在本發明的此實施例的QDP型多晶粒堆疊結構中，亦包括以下額外的連接。
第四晶粒18的CS0墊101已如前述般透過三個TSV 130與第三晶粒16的CS1墊103、第二晶粒14的CS2墊105及第一晶粒12的CS3墊107電性連接，此處再透過第四晶粒18的M2層110的延伸部110a來與在第四晶粒18中CS3墊107上方的TSV 130電性連接，如對應的箭頭150所示。因此，第四晶粒18的CS0墊101與其他三個CS墊以及四個TSV130電性連接。
第一晶粒12的CS0墊101透過第一晶粒12的M2層110的延伸部110a(如對應的箭頭150所示)、第一晶粒12中的TSV 130等來與第二晶粒14的CS3墊107電性連接。因此，第一晶粒12的CS0墊101亦經由與第三晶粒16的CS2墊105及第四晶粒18的CS1墊103電性連接的第二晶粒14的CS3墊107，而與第三晶粒16的CS2墊105以及第四晶粒18的CS1墊103電性連接。因此，第一晶粒12的CS0墊101總共與三個CS墊以及四個TSV 130電性連接，如同第四晶粒18的CS0墊101。
第二晶粒14的CS0墊101已如前述般與第一晶粒12的CS1墊103電性連接，此處再透過第二晶粒14的M2層110的延伸部110a(如對應箭頭150所示)、第二晶粒14中的TSV 130等來與第三晶粒16的CS3墊107電性連接，從而亦與和第三晶粒16的CS3墊107電性連接的第四晶粒18的CS2墊105電性連接。因此，所述第二晶粒14的CS0墊101總共與三個CS墊以及四個TSV 130電性連接，如同第四晶粒18的CS0墊101。
第三晶粒16的CS0墊101已如前述般與第二晶粒14的 CS1墊103以及第一晶粒12的CS2墊105電性連接，此處再透過第三晶粒16的M2層110的延伸部110a(由對應箭頭150指示)、第三晶粒16中的TSV 130等來與第四晶粒18的CS3墊107電性連接。因此，所述第三晶粒16的CS0墊101總共與三個CS墊以及四個TSV 130電性連接，如同第四晶粒18的CS0墊101。
由於以上實施例的QDP型多晶粒堆疊結構中的任意晶粒的CS0墊皆與其他三個CS墊以及四個TSV電性連接，因此實質上消除了四個晶粒的CS/ZQ墊之間的Cin差異。
此外，各基底通孔130例如是矽通孔(through-silicon via)(當基底為矽基底時)。此外，四個晶粒12、14、16與18可以是DRAM晶粒，其可以是DDR3 DRAM晶粒。然而，本發明並不限於應用於此，而可應用至任何利用階梯型連接的使用TSV的堆疊晶粒結構。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
12、14、16、18‧‧‧晶粒
101、103、105、107、CS0、CS1、CS2、CS3‧‧‧輸入墊
100、110、120‧‧‧金屬層
110a‧‧‧延伸部
130‧‧‧基底通孔
140‧‧‧銲球
150‧‧‧箭頭

Claims (7)

  1. 一種多晶粒堆疊結構，包括N個(N2)垂直堆疊的晶粒，其中每個晶粒包括N個晶粒輸入墊(die-specific input pads)，其中在所述N個輸入墊中有一特定輸入墊用於所述晶粒本身的輸入，在底晶粒上方的每個晶粒的所述特定輸入墊透過至少一基底通孔(through-substrate via)電性連接至所述底晶粒之所述特定輸入墊以外的不同輸入墊，且當不在與所述底晶粒相鄰的晶粒中時，亦透過所述底晶粒上方的每個下方晶粒的不同輸入墊達成上述電性連接，以及所述底晶粒的所述特定輸入墊電性連接至上方晶粒的至少一個輸入墊，所述至少一個輸入墊並非任何上方晶粒的所述特定輸入墊，且未電性連接至任何上方晶粒的所述特定輸入墊，其中所述N個晶粒包括由下至上的第一至第N晶粒，其中第一晶粒即為所述底晶粒，在每個晶粒中，所述N個輸入墊包括依序排列的第一至第N輸入墊，其中第一輸入墊即是用於所述晶粒本身的輸入的所述特定輸入墊，在各第i晶粒(i=2~N)中，第j輸入墊(j=1~N-1)電性連接至各第(i-k)晶粒(k=1~i-1)的第(j+k)輸入墊，但其中j+kN，所述第一晶粒的所述特定輸入墊透過在所述第一晶粒中的基底通孔電性連接至第二晶粒的第N輸入墊， 各第m晶粒(m=2~N-1)的所述特定輸入墊亦透過在所述第m晶粒中的基底通孔電性連接至第(m+1)晶粒的第N輸入墊，第N晶粒的所述特定輸入墊亦電性連接至在所述第N晶粒中第N輸入墊上方的基底通孔。
  2. 如申請專利範圍第1項所述的多晶粒堆疊結構，其中所述晶粒輸入墊是晶粒選擇(chip-select,CS)墊。
  3. 如申請專利範圍第1項所述的多晶粒堆疊結構，其中所述至少一基底通孔包括至少一矽通孔(through-silicon via)。
  4. 如申請專利範圍第1項所述的多晶粒堆疊結構，其中所述N個晶粒包括動態隨機存取記憶體(DRAM)晶粒。
  5. 如申請專利範圍第4項所述的多晶粒堆疊結構，其中所述DRAM晶粒包括DDR3 DRAM晶粒。
  6. 如申請專利範圍第1項所述的多晶粒堆疊結構，其中各第m晶粒的所述特定輸入墊透過電路電性連接至第(m+1)晶粒的第N輸入墊，所述電路包括在所述第m晶粒中的金屬層的延伸部與基底通孔。
  7. 如申請專利範圍第1項所述的多晶粒堆疊結構，其中N=4。
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