TWI523115B - A semiconductor structure forming method and a semiconductor structure - Google Patents
A semiconductor structure forming method and a semiconductor structure Download PDFInfo
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- TWI523115B TWI523115B TW102113280A TW102113280A TWI523115B TW I523115 B TWI523115 B TW I523115B TW 102113280 A TW102113280 A TW 102113280A TW 102113280 A TW102113280 A TW 102113280A TW I523115 B TWI523115 B TW I523115B
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- well region
- ion implantation
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- 239000004065 semiconductor Substances 0.000 title claims description 72
- 238000000034 method Methods 0.000 title claims description 56
- 238000005468 ion implantation Methods 0.000 claims description 84
- 239000000758 substrate Substances 0.000 claims description 55
- 238000002955 isolation Methods 0.000 claims description 51
- 239000000463 material Substances 0.000 claims description 21
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 19
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical group O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 19
- 150000002500 ions Chemical class 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 10
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 229910000420 cerium oxide Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical group [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000004593 Epoxy Substances 0.000 claims description 2
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 claims 1
- 230000008569 process Effects 0.000 description 12
- -1 boron ion Chemical class 0.000 description 11
- 239000002019 doping agent Substances 0.000 description 11
- 229910052796 boron Inorganic materials 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 6
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
本發明涉及半導體製造技術,特別涉及一種半導體結構的形成方法和半導體結構。 The present invention relates to semiconductor fabrication techniques, and more particularly to a method of forming a semiconductor structure and a semiconductor structure.
隨著半導體技術的不斷發展,晶片上的半導體器件的尺寸在不斷地縮小。相應的,將半導體器件進行隔離的隔離結構需要不斷的縮小。專利號為US6171910B1的美國專利文獻公開了一種縮小半導體器件尺寸的方法。 As semiconductor technology continues to evolve, the size of semiconductor devices on wafers continues to shrink. Accordingly, the isolation structure that isolates the semiconductor device needs to be continuously reduced. U.S. Patent Publication No. 6,171,910 B1 discloses a method of reducing the size of a semiconductor device.
參考圖1至圖3,現有的半導體結構之間的淺溝槽隔離結構的製作方法如下:參考圖1,提供半導體襯底100,在所述半導體襯底上形成凹槽102。 Referring to FIGS. 1 through 3, a shallow trench isolation structure between existing semiconductor structures is fabricated as follows: Referring to FIG. 1, a semiconductor substrate 100 is provided on which a recess 102 is formed.
參考圖2,在所述凹槽102內和襯底100表面形成介質層,去除高於凹槽102表面的介質層,形成淺溝槽隔離結構(STI)104。形成淺溝槽隔離結構104後,在所述淺溝槽隔離結構104的兩側的襯底內分別進行離子注入,形成N阱區105和P阱區106。 Referring to FIG. 2, a dielectric layer is formed in the recess 102 and on the surface of the substrate 100 to remove the dielectric layer above the surface of the recess 102 to form a shallow trench isolation structure (STI) 104. After the shallow trench isolation structures 104 are formed, ion implantation is performed in the substrates on both sides of the shallow trench isolation structures 104 to form N well regions 105 and P well regions 106.
參考圖3,形成N阱區105和P阱區106後,在N阱 區105形成PMOS電晶體107,其中,PMOS電晶體中形成有P型的源極108和漏極109。在P阱區106形成NMOS電晶體110,其中,NMOS電晶體中形成有N型的源極111和漏極112。 Referring to FIG. 3, after forming the N well region 105 and the P well region 106, the N well The region 105 forms a PMOS transistor 107 in which a P-type source 108 and a drain 109 are formed in the PMOS transistor. An NMOS transistor 110 is formed in the P well region 106 in which an N-type source 111 and a drain 112 are formed in the NMOS transistor.
現有技術中的淺溝槽隔離結構無法繼續縮小,佔用晶片的面積較大。 The shallow trench isolation structure in the prior art cannot continue to shrink, and the area occupied by the wafer is large.
本發明解決的問題是現有技術中的淺溝槽隔離結構無法繼續縮小,佔用晶片的面積較大。 The problem solved by the present invention is that the shallow trench isolation structure in the prior art cannot continue to shrink, and the area occupied by the wafer is large.
為解決上述問題,本發明提供了一種半導體結構的形成方法,包括:提供半導體襯底,在所述半導體襯底內形成凹槽,所述凹槽將半導體襯底分為第一有源區和第二有源區;在所述凹槽側壁形成側牆;在所述第一有源區內形成第一阱區,在所述第二有源區內形成第二阱區,所述第一阱區和第二阱區的連接處形成耗盡區;形成側牆後,在所述凹槽底部的第一阱區中進行第一離子注入,在所述凹槽底部的第二阱區中進行第二離子注入,第一離子注入的類型與第一阱區的類型相同,第二離子注入的類型與第二阱區的類型相同;離子注入後,在所述凹槽內填充介質層形成隔離結構。 In order to solve the above problems, the present invention provides a method of forming a semiconductor structure, comprising: providing a semiconductor substrate, forming a recess in the semiconductor substrate, the recess dividing the semiconductor substrate into a first active region and a second active region; forming a sidewall in the sidewall of the recess; forming a first well region in the first active region, and forming a second well region in the second active region, the first a junction of the well region and the second well region forms a depletion region; after forming the sidewall, a first ion implantation is performed in the first well region at the bottom of the trench, in the second well region at the bottom of the trench Performing a second ion implantation, the type of the first ion implantation is the same as the type of the first well region, the type of the second ion implantation is the same as the type of the second well region; after the ion implantation, filling the dielectric layer in the groove Isolation structure.
可選的,所述在所述凹槽底部的第一阱區中進行第一離子注入包括:在所述襯底和凹槽形成的表面上形成圖形化的第一掩膜層,定義第一離子注入的區域;以所述圖形化的第一掩膜層為掩膜,進行第一離子注入;第一離子注入後,去除圖形化的第一掩膜層。 Optionally, performing the first ion implantation in the first well region at the bottom of the groove comprises: forming a patterned first mask layer on the surface formed by the substrate and the groove, defining the first a region of ion implantation; performing a first ion implantation using the patterned first mask layer as a mask; and removing the patterned first mask layer after the first ion implantation.
可選的,所述在所述凹槽底部的第二阱區中進行第二離子注入包括:在所述襯底和凹槽形成的表面上形成圖形化的第二掩膜層,定義第二離子注入的區域;以所述圖形化的第二掩膜層為掩膜,進行第二離子注入;第二離子注入後,去除圖形化的第二掩膜層。 Optionally, performing the second ion implantation in the second well region at the bottom of the groove comprises: forming a patterned second mask layer on the surface formed by the substrate and the groove, defining a second a region of ion implantation; performing a second ion implantation using the patterned second mask layer as a mask; and removing the patterned second mask layer after the second ion implantation.
可選的,所述第一離子注入的濃度小於所述隔離結構發生擊穿時的離子注入濃度。 Optionally, the concentration of the first ion implantation is less than the ion implantation concentration when the isolation structure is broken down.
可選的,所述第一離子注入的濃度小於1×1014atom/cm2。 Optionally, the concentration of the first ion implantation is less than 1×10 14 atoms/cm 2 .
可選的,所述第二離子注入的濃度小於所述隔離結構發生擊穿時的離子注入濃度。 Optionally, the concentration of the second ion implantation is less than the ion implantation concentration when the isolation structure is broken down.
可選的,所述第二離子注入的濃度小於1×1014atom/cm2。 Optionally, the concentration of the second ion implantation is less than 1×10 14 atoms/cm 2 .
可選的,所述側牆的材料為氧化矽或氮化矽。 Optionally, the material of the sidewall is yttrium oxide or tantalum nitride.
可選的,所述側牆的形成方法包括: 在所述凹槽表面沈積側牆的材料層;對所述側牆的材料層進行回刻。 Optionally, the method for forming the sidewall spacer includes: Depositing a material layer of the sidewall on the surface of the groove; etching the material layer of the sidewall.
可選的,離子注入後,在所述凹槽內填充介質層形成隔離結構之前還包括步驟:去除所述側牆。 Optionally, after the ion implantation, the step of filling the dielectric layer to form the isolation structure in the groove further comprises the step of removing the sidewall spacer.
可選的,去除所述側牆的方法為濕法腐蝕。 Optionally, the method of removing the sidewall is wet etching.
可選的,在所述半導體襯底上形成凹槽的步驟之前還包括步驟:在所述襯底上形成墊氧層,在所述墊氧層上形成阻擋層。 Optionally, the step of forming a recess on the semiconductor substrate further comprises the steps of: forming an epoxy layer on the substrate, and forming a barrier layer on the pad oxide layer.
可選的,所述墊氧層的材料為氧化矽,所述阻擋層的材料為氮化矽。 Optionally, the material of the pad layer is ruthenium oxide, and the material of the barrier layer is tantalum nitride.
可選的,在所述凹槽側壁形成側牆前還包括步驟:在所述凹槽表面形成氧化矽層。 Optionally, before the forming a sidewall of the sidewall of the recess, the method further includes the step of forming a ruthenium oxide layer on the surface of the recess.
可選的,所述氧化矽層的形成方法為熱氧化。 Optionally, the method for forming the ruthenium oxide layer is thermal oxidation.
可選的,所述介質層的材料為氧化矽。 Optionally, the material of the dielectric layer is cerium oxide.
可選的,所述在所述半導體襯底上形成凹槽的方法包括:在所述半導體襯底上形成圖形化的第三掩膜層,定義凹槽的位置;以所述圖形化的第三掩膜層為掩膜對半導體襯底進行刻蝕。 Optionally, the method for forming a groove on the semiconductor substrate comprises: forming a patterned third mask layer on the semiconductor substrate, defining a position of the groove; The triple mask layer etches the semiconductor substrate as a mask.
本發明還提供一種半導體結構,包括:具有凹槽的半導體襯底,所述凹槽的一側半導體襯底為第一有源區,所述凹槽的另一側半導體襯底為第二有源區; 位於凹槽側壁的側牆;位於第一有源區內的第一阱區,位於第二有源區內的第二阱區,所述第一阱區與所述第二阱區在所述凹槽底部的連接處形成耗盡區;所述凹槽底部的第一阱區的離子濃度大於第一阱區其他位置的濃度,所述凹槽底部的第二阱區的離子濃度大於第二阱區其他位置的濃度;填充所述凹槽的介質層。 The present invention also provides a semiconductor structure comprising: a semiconductor substrate having a recess, one side of the recessed semiconductor substrate being a first active region, and the other side of the recessed semiconductor substrate being second Source area a sidewall located in the sidewall of the recess; a first well region in the first active region, a second well region in the second active region, the first well region and the second well region being a junction at the bottom of the groove forms a depletion region; an ion concentration of the first well region at the bottom of the groove is greater than a concentration of other locations in the first well region, and an ion concentration of the second well region at the bottom of the groove is greater than a second The concentration of other locations in the well region; the dielectric layer filling the recess.
與現有技術相比,本發明的技術方案具有以下優點:在所述凹槽底部的第一阱區中進行第一離子注入,在所述凹槽底部的第二阱區中進行第二離子注入,第一離子注入的類型與第一阱區的類型相同,第二離子注入的類型與第二阱區的類型相同,以使凹槽底部第一阱區和第二阱區的離子濃度都有所增高,從而使得第一阱區和第二阱區在凹槽底部形成的耗盡區的寬度減小。離子注入後,在所述凹槽內填充介質層形成隔離結構。然後,在所述隔離結構的兩側形成漏極和源極,其中,漏極為在第一阱區內形成的與該隔離結構相鄰的電晶體的漏極,所述源極為在第二阱區內與該隔離結構相鄰的電晶體的源極。當縮小該隔離結構的尺寸時,該隔離結構兩側的漏極和源極之間的距離也會相應縮小,但是,在縮小該隔離結構尺寸的情況下,即使對源極或漏極施加電壓,也不會發生源極、漏極與同類型阱區之間的穿通(punchthrough),即,在第一阱區的漏極不會與第二阱區之間發生穿通,在第二阱區的 源極不會與第一阱區之間發生穿通。因此,當對所述凹槽底部進行上述離子注入時,可以縮小該隔離結構的尺寸,進而減小該隔離結構在晶片上的佔用面積。並且,本發明在所述凹槽側壁形成側牆,防止在凹槽側壁處的半導體襯底被離子注入,尤其可以防止後續形成PMOS電晶體或者NMOS電晶體中的柵極附近被離子注入。當在凹槽側壁處的半導體襯底不被離子注入時,可以增加後續形成的隔離結構的擊穿電壓(Breakdown Voltage),從而可以提高後續形成的隔離結構的隔離效果。當後續形成PMOS電晶體或者NMOS電晶體中的柵極附近不被離子注入時,可以使得半導體器件的閾值電壓(VT)減小,飽和電流(Idsat)增加,從而減小需要開啟半導體器件能量,相當於減小能耗,因此,可以避免發生窄器件效應(Narrow Width Effect)。 Compared with the prior art, the technical solution of the present invention has the following advantages: performing first ion implantation in a first well region at the bottom of the groove, and performing second ion implantation in a second well region at the bottom of the groove The first ion implantation is of the same type as the first well region, and the second ion implantation is of the same type as the second well region, so that the ion concentration of the first well region and the second well region at the bottom of the groove are both The increase is such that the width of the depletion region formed by the first well region and the second well region at the bottom of the recess is reduced. After ion implantation, a dielectric layer is filled in the recess to form an isolation structure. Then, a drain and a source are formed on both sides of the isolation structure, wherein the drain is a drain of a transistor formed in the first well region adjacent to the isolation structure, and the source is extremely in the second well a source of a transistor adjacent to the isolation structure in the region. When the size of the isolation structure is reduced, the distance between the drain and the source on both sides of the isolation structure is correspondingly reduced, but even if the size of the isolation structure is reduced, even if a voltage is applied to the source or the drain There is also no punchthrough between the source, the drain and the well of the same type, that is, the drain of the first well region does not pass through with the second well region, and the second well region of The source does not pass through with the first well region. Therefore, when the ion implantation is performed on the bottom of the groove, the size of the isolation structure can be reduced, thereby reducing the occupation area of the isolation structure on the wafer. Moreover, the present invention forms a sidewall on the sidewall of the recess to prevent ion implantation of the semiconductor substrate at the sidewall of the recess, and in particular to prevent ion implantation near the gate in the subsequent formation of the PMOS transistor or the NMOS transistor. When the semiconductor substrate at the sidewall of the recess is not ion-implanted, the breakdown voltage of the subsequently formed isolation structure can be increased, so that the isolation effect of the subsequently formed isolation structure can be improved. When the vicinity of the gate in the PMOS transistor or the NMOS transistor is not ion-implanted, the threshold voltage (VT) of the semiconductor device may be decreased, and the saturation current (Idsat) may be increased, thereby reducing the energy required to turn on the semiconductor device. This is equivalent to reducing the power consumption, so the Narrow Width Effect can be avoided.
更進一步的,在所述凹槽底部進行上述離子注入,以使第一阱區和第二阱區的濃度都有所增加,可以減小靜電放電防護電路的觸發電壓(Trigger Voltage),當有靜電放電現象發生時,本發明可以更容易觸發靜電防護電路,以保護半導體器件不受破壞或損毀。 Further, the ion implantation is performed at the bottom of the groove to increase the concentration of the first well region and the second well region, and the trigger voltage of the electrostatic discharge protection circuit can be reduced. When an electrostatic discharge phenomenon occurs, the present invention can more easily trigger an electrostatic protection circuit to protect the semiconductor device from damage or damage.
100‧‧‧半導體襯底 100‧‧‧Semiconductor substrate
102‧‧‧凹槽 102‧‧‧ Groove
104‧‧‧淺溝槽隔離結構 104‧‧‧Shallow trench isolation structure
105‧‧‧N阱區 105‧‧‧N well zone
106‧‧‧P阱區 106‧‧‧P-well zone
107‧‧‧PMOS電晶體 107‧‧‧ PMOS transistor
108‧‧‧源極 108‧‧‧ source
109‧‧‧漏極 109‧‧‧Drain
110‧‧‧NMOS電晶體 110‧‧‧NMOS transistor
111‧‧‧源極 111‧‧‧ source
112‧‧‧漏極 112‧‧‧Drain
200‧‧‧半導體襯底 200‧‧‧Semiconductor substrate
201‧‧‧凹槽 201‧‧‧ Groove
202‧‧‧墊氧層 202‧‧‧Oxygen layer
203‧‧‧阻擋層 203‧‧‧Block
204‧‧‧第一阱區 204‧‧‧First Well Area
205‧‧‧第二阱區 205‧‧‧Second well area
207‧‧‧第一掩膜層 207‧‧‧First mask layer
208‧‧‧P+區域 208‧‧‧P+ area
209‧‧‧第二掩膜層 209‧‧‧second mask layer
210‧‧‧N+區域 210‧‧‧N+ area
211‧‧‧介質層 211‧‧‧ dielectric layer
212‧‧‧隔離結構 212‧‧‧Isolation structure
213‧‧‧氧化矽層 213‧‧‧Oxide layer
214‧‧‧側牆 214‧‧‧ Side wall
圖1至圖3是現有技術的半導體結構之間的淺溝槽隔離結構的製作方法的剖面結構示意圖;圖4是本發明實施例的半導體結構的形成方法的流程 示意圖;圖5至圖10是本發明實施例的半導體結構的形成過程的剖面結構示意圖。 1 to 3 are schematic cross-sectional views showing a method of fabricating a shallow trench isolation structure between semiconductor structures in the prior art; and FIG. 4 is a flow chart showing a method of forming a semiconductor structure according to an embodiment of the present invention; FIG. 5 to FIG. 10 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to an embodiment of the present invention.
發明人發現和分析,現有技術中的淺溝槽隔離結構無法繼續縮小,佔用晶片的面積較大的原因為:參考圖3,現有技術中,P阱區106的空穴會擴散到N阱區105,N阱區105的電子會擴散到P阱區106,因此,擴散到N阱區105的空穴和擴散到P阱區106的電子會在淺溝槽隔離結構104底部複合形成耗盡區。當器件工作時需要向PMOS電晶體、NMOS電晶體的源極和漏極施加電壓,耗盡區的寬度會在施加電壓的作用下增加,如果此時縮小淺溝槽隔離結構104的尺寸,則相當於縮小NMOS電晶體的漏極112和PMOS電晶體源極108之間的距離,寬度增加的耗盡區很容易進入NMOS電晶體的漏極112和PMOS電晶體源極108,造成源極108、漏極112與同類型摻雜的阱區之間的穿通(punchthrough),使得半導體器件無法工作。具體為,寬度增加的耗盡區中的電子進入到NMOS電晶體中的漏極112,使得NMOS電晶體的漏極112與N阱區105之間發生穿通。寬度增加的耗盡區中的空穴進入到PMOS電晶體中的源極108,使得PMOS電晶體的源極108與P阱區106之間發生穿通。因此,淺溝槽隔離結構的尺寸無法繼續縮小,在晶片中佔用 的面積較大。 The inventors have discovered and analyzed that the shallow trench isolation structure in the prior art cannot continue to shrink, and the reason for occupying a large area of the wafer is as follows: Referring to FIG. 3, in the prior art, holes of the P well region 106 are diffused to the N well region. 105, electrons of the N well region 105 are diffused into the P well region 106, and therefore, holes diffused into the N well region 105 and electrons diffused into the P well region 106 are combined at the bottom of the shallow trench isolation structure 104 to form a depletion region. . When the device is working, it is necessary to apply a voltage to the PMOS transistor, the source and the drain of the NMOS transistor, and the width of the depletion region is increased by the applied voltage. If the size of the shallow trench isolation structure 104 is reduced at this time, Corresponding to reducing the distance between the drain 112 of the NMOS transistor and the PMOS transistor source 108, the depletion region with increased width easily enters the drain 112 of the NMOS transistor and the PMOS transistor source 108, resulting in source 108. The punchthrough between the drain 112 and the well region doped with the same type makes the semiconductor device inoperable. Specifically, electrons in the depletion region having an increased width enter the drain 112 in the NMOS transistor, so that punch-through occurs between the drain 112 and the N well region 105 of the NMOS transistor. Holes in the increased width depletion region enter the source 108 in the PMOS transistor such that a punchthrough occurs between the source 108 and the P well region 106 of the PMOS transistor. Therefore, the size of the shallow trench isolation structure cannot continue to shrink, occupying in the wafer The area is large.
為此,發明人經過研究,提出了一種半導體結構的形成方法,圖4是本發明實施例的半導體結構的形成方法的流程示意圖。圖5至圖8是本發明實施例的半導體結構的形成過程的剖面結構示意圖。下面將圖5至圖8與圖4結合起來對本發明半導體結構的形成方法進行詳細說明。 To this end, the inventors have studied a method of forming a semiconductor structure, and FIG. 4 is a schematic flow chart of a method of forming a semiconductor structure according to an embodiment of the present invention. 5 to 8 are schematic cross-sectional views showing a process of forming a semiconductor structure according to an embodiment of the present invention. The method of forming the semiconductor structure of the present invention will be described in detail below in conjunction with FIGS. 5 to 8 and FIG.
首先參考圖5,執行圖4中的步驟S11,提供半導體襯底200,在所述半導體襯底上形成凹槽201,所述凹槽201將半導體襯底分為第一有源區I和第二有源區Π。 Referring first to FIG. 5, step S11 in FIG. 4 is performed to provide a semiconductor substrate 200 on which a recess 201 is formed, which divides the semiconductor substrate into first active regions I and Two active areas.
襯底200材料可以是矽襯底、鍺矽襯底、Ⅲ-V族元素化合物襯底、碳化矽襯底或其疊層結構,或絕緣體上矽結構,或金剛石襯底,或本領域技術人員公知的其他半導體材料襯底。 The material of the substrate 200 may be a germanium substrate, a germanium substrate, a III-V element compound substrate, a tantalum carbide substrate or a stacked structure thereof, or an insulator upper structure, or a diamond substrate, or a person skilled in the art. Other semiconductor material substrates are known.
本實施例中,半導體200上還形成有墊氧層202,在墊氧層202上形成阻擋層203。阻擋層203的作用為對半導體襯底表面進行保護。所述阻擋層203的材料為氮化矽,形成方法為化學氣相沈積。墊氧層202的作用是為了防止阻擋層203和半導體襯底200之間由於熱膨脹係數不同而產生的應力破壞。墊氧層202的材料為氧化矽,形成方法為化學氣相沈積。 In this embodiment, a pad layer 202 is formed on the semiconductor 200, and a barrier layer 203 is formed on the pad oxide layer 202. The barrier layer 203 functions to protect the surface of the semiconductor substrate. The material of the barrier layer 203 is tantalum nitride, and the formation method is chemical vapor deposition. The function of the pad layer 202 is to prevent stress damage between the barrier layer 203 and the semiconductor substrate 200 due to the difference in thermal expansion coefficient. The material of the pad oxygen layer 202 is ruthenium oxide, and the formation method is chemical vapor deposition.
形成阻擋層203後,在所述阻擋層203的表面形成圖案化的掩膜層(圖未示),以所述圖案化的掩膜層為掩膜,依次對阻擋層203、墊氧層202和襯底200進行刻蝕,在襯底200內形成凹槽201。所述凹槽201將半導體 襯底分為第一有源區I和第二有源區Π。 After the barrier layer 203 is formed, a patterned mask layer (not shown) is formed on the surface of the barrier layer 203, and the patterned mask layer is used as a mask, and the barrier layer 203 and the pad oxide layer 202 are sequentially disposed. The substrate 200 is etched to form a recess 201 in the substrate 200. The groove 201 will be a semiconductor The substrate is divided into a first active region I and a second active region Π.
形成凹槽201後,在所述凹槽201表面形成氧化矽層213,所述氧化矽層213的形成方法為熱氧化。凹槽201表面形成氧化矽層213的作用為:首先,經過刻蝕工藝形成凹槽201的過程中,凹槽201表面的矽有損傷,通過熱氧化工藝可以將表面有損傷的矽變成氧化矽,以使後續形成的淺溝槽隔離結構的隔離效果更好。再者,經過刻蝕工藝形成的凹槽底部邊角處的角度比較尖銳,容易將電荷聚集到尖端,形成尖端放電,從而在後續淺溝槽隔離結構處產生擊穿電壓,因此,在所述凹槽的表面形成氧化矽層,可以使得凹槽底部的邊角處變圓滑,減小尖端放電現象的發生。 After the recess 201 is formed, a ruthenium oxide layer 213 is formed on the surface of the recess 201, and the ruthenium oxide layer 213 is formed by thermal oxidation. The surface of the groove 201 is formed by the yttrium oxide layer 213. Firstly, during the process of forming the groove 201 by the etching process, the surface of the groove 201 is damaged, and the surface damaged yttrium can be transformed into yttrium oxide by a thermal oxidation process. In order to make the isolation effect of the subsequently formed shallow trench isolation structure better. Moreover, the angle at the bottom corner of the groove formed by the etching process is relatively sharp, and it is easy to concentrate the charge to the tip to form a tip discharge, thereby generating a breakdown voltage at the subsequent shallow trench isolation structure, and thus, The surface of the groove forms a layer of ruthenium oxide, which can make the corners at the bottom of the groove smooth, reducing the occurrence of tip discharge.
當然,在其他實施例中,也可以不在凹槽201的表面形成氧化矽層213。 Of course, in other embodiments, the ruthenium oxide layer 213 may not be formed on the surface of the recess 201.
接著,參考圖6,執行圖4中的步驟S12,在所述凹槽201側壁形成側牆214。 Next, referring to FIG. 6, step S12 in FIG. 4 is performed to form a sidewall 214 on the sidewall of the recess 201.
其中,側牆214的材料可以為氧化矽或氮化矽。側牆214的形成方法為:先在所述凹槽201的氧化矽層213表面採用化學氣相沈積的方法形成側牆的材料層,然後將側牆的材料層進行回刻,形成側牆214。本實施例中,側牆214的材料為氧化矽。採用正矽酸乙酯(TEOS)和臭氧(O3)反應沈積氧化矽。之所以採用正矽酸乙酯(TEOS)和臭氧(O3)反應沈積氧化矽,是因為:一方面,採用正矽酸乙酯(TEOS)和臭氧(O3)反應沈積氧 化矽具有良好的填充能力,適合填充高的深寬比的槽,另一方面,採用正矽酸乙酯(TEOS)和臭氧(O3)利用熱化學氣相沈積工藝來沈積氧化矽,不會像等離子體減壓化學氣相沈積(HDPCVD)一樣容易對半導體襯底的邊角造成損傷。再者,採用正矽酸乙酯(TEOS)和臭氧(O3)形成的側牆214在後續工藝中容易被去除。 The material of the sidewall 214 may be tantalum oxide or tantalum nitride. The sidewall 214 is formed by first forming a material layer of the sidewall by chemical vapor deposition on the surface of the ruthenium oxide layer 213 of the recess 201, and then etching the material layer of the sidewall to form the sidewall 214. . In this embodiment, the material of the sidewall 214 is yttrium oxide. The cerium oxide is deposited by the reaction of ethyl orthosilicate (TEOS) and ozone (O 3 ). The reason why the ruthenium oxide is deposited by the reaction of TEOS and ozone (O 3 ) is because: on the one hand, the deposition of ruthenium oxide by the reaction of TEOS and O 3 is good. Filling capacity, suitable for filling high aspect ratio grooves, on the other hand, using TEOS and ozone (O 3 ) to deposit yttrium oxide by thermal chemical vapor deposition, not like plasma reduction Pressure chemical vapor deposition (HDPCVD) is equally susceptible to damage to the corners of the semiconductor substrate. Further, the side wall 214 formed using ethyl orthosilicate (TEOS) and ozone (O 3 ) is easily removed in a subsequent process.
在後續的離子注入的步驟中,側牆214可以保護凹槽201側壁不被離子注入,還可以保護後續形成PMOS電晶體或者NMOS電晶體中的柵極附近不被離子注入。 In the subsequent ion implantation step, the sidewall spacers 214 may protect the sidewalls of the recess 201 from ion implantation, and may also protect the vicinity of the gate in the PMOS transistor or the NMOS transistor from being implanted by ions.
接著,繼續參考圖6,執行圖4中的步驟S13,在所述第一有源區I內形成第一阱區204,在所述第二有源區Π內形成第二阱區205,所述第一阱區204和第二阱區205的連接處形成耗盡區。 Next, with reference to FIG. 6, step S13 in FIG. 4 is performed, a first well region 204 is formed in the first active region I, and a second well region 205 is formed in the second active region ,. The junction of the first well region 204 and the second well region 205 forms a depletion region.
當第一有源區I內的電晶體為NMOS電晶體時,在第一有源區I摻雜三價摻雜劑形成P阱區,其中,三價摻雜劑為硼離子;當第一有源區I內的電晶體為PMOS電晶體時,在第一有源區區I摻雜五價摻雜劑形成N阱區,其中,五價摻雜劑為磷離子、砷離子或銻離子。在第一有源區I內形成第一阱區204的方法為本領域技術人員熟知技術,在此不再贅述。當第一有源區I內的電晶體為NMOS電晶體,在第一有源區I摻雜三價摻雜劑形成P阱區時,則在第二有源區Π摻雜五價摻雜劑形成N阱區;當第一有源區I內的電晶體為PMOS電晶體,在第一有源區I摻雜五價摻雜劑形成N阱區時,則在第二有源區Π摻雜三 價摻雜劑形成P阱區。在第二有源區Π內形成第二阱區205的方法為本領域技術人員熟知技術,在此不再贅述。本實施例中,第一有源區I內的電晶體為NMOS電晶體,是在第一有源區I摻雜三價摻雜劑形成P阱區,在第二有源區Π摻雜五價摻雜劑形成N阱區。形成N阱區後,所述N阱區與在第一有源區I形成的P阱區的連接處形成耗盡區。 When the transistor in the first active region I is an NMOS transistor, the first active region I is doped with a trivalent dopant to form a P-well region, wherein the trivalent dopant is boron ion; When the transistor in the active region I is a PMOS transistor, the pentavalent dopant is doped in the first active region I to form an N-well region, wherein the pentavalent dopant is a phosphorus ion, an arsenic ion or a cerium ion. The method of forming the first well region 204 in the first active region I is well known to those skilled in the art and will not be described herein. When the transistor in the first active region I is an NMOS transistor, when the first active region I is doped with a trivalent dopant to form a P well region, then the second active region is doped with pentavalent doping. The agent forms an N-well region; when the transistor in the first active region I is a PMOS transistor, when the first active region I is doped with a pentavalent dopant to form an N-well region, then in the second active region Doping three The valence dopant forms a P-well region. The method of forming the second well region 205 in the second active region 为本 is well known to those skilled in the art and will not be described herein. In this embodiment, the transistor in the first active region I is an NMOS transistor, which is doped with a trivalent dopant in the first active region I to form a P-well region, and is doped in the second active region. The valence dopant forms an N-well region. After the N-well region is formed, a depletion region is formed at the junction of the N-well region and the P-well region formed at the first active region I.
在其他實施例中,也可以在第一有源區I摻雜五價摻雜劑形成N阱區,在第二有源區Π內摻雜三價摻雜劑形成P阱區也能實施本發明。 In other embodiments, the N-well region may be formed by doping the pentavalent dopant in the first active region I, and the P-well region may be formed by doping the trivalent dopant into the second active region. invention.
接著,參考圖7和圖8,執行圖4中的步驟S14,形成側牆214後,在所述凹槽201底部的第一阱區204中進行第一離子注入,在所述凹槽201底部的第二阱區205中進行第二離子注入,第一離子注入的類型與第一阱區204的類型相同,第二離子注入的類型與第二阱區205的類型相同。 Next, referring to FIG. 7 and FIG. 8, step S14 in FIG. 4 is performed, after the sidewall spacer 214 is formed, a first ion implantation is performed in the first well region 204 at the bottom of the recess 201, at the bottom of the recess 201. A second ion implantation is performed in the second well region 205, the first ion implantation is of the same type as the first well region 204, and the second ion implantation is of the same type as the second well region 205.
具體為:參考圖7,在所述襯底200和凹槽201形成的表面上形成圖形化的第一掩膜層207,定義第一離子注入的區域,然後,以所述圖形化的第一掩膜層為掩膜,進行第一離子注入。第一離子注入的類型與第一阱區204的類型相同。 Specifically, referring to FIG. 7, a patterned first mask layer 207 is formed on the surface formed by the substrate 200 and the recess 201, defining a region of the first ion implantation, and then, with the patterned first The mask layer is a mask for performing the first ion implantation. The type of the first ion implantation is the same as that of the first well region 204.
其中,第一掩膜層207可以為光刻膠、氧化矽、氮氧化矽、氮化鉭或氮化鈦。本實施例較佳選用光刻膠。 The first mask layer 207 may be a photoresist, ruthenium oxide, ruthenium oxynitride, tantalum nitride or titanium nitride. In this embodiment, a photoresist is preferably used.
本實施例中,第一阱區204為P阱區。對凹槽底部 的P阱區進行第一離子注入,形成P+區域208,注入的離子為磷離子、砷離子或銻離子。所述磷離子注入的劑量小於1×1014atom/cm2,磷離子注入的能量小於1000Kev。所述磷離子注入時的射頻電壓和磷離子注入的時間根據離子注入工藝時使用的濺射機台而定,因此,磷離子注入時的射頻電壓和磷離子注入的時間根據具體離子注入工藝的不同而不同。 In this embodiment, the first well region 204 is a P well region. A first ion implantation is performed on the P well region at the bottom of the groove to form a P+ region 208, and the implanted ions are phosphorus ions, arsenic ions or erbium ions. The dose of the phosphorus ion implantation is less than 1 × 10 14 atoms/cm 2 , and the energy of the phosphorus ion implantation is less than 1000 KeV. The RF voltage and the time of the phosphorus ion implantation during the phosphorus ion implantation are determined according to the sputtering machine used in the ion implantation process, and therefore, the RF voltage and the time of the phosphorus ion implantation during the phosphorus ion implantation are according to a specific ion implantation process. Different and different.
形成P+區域208後,去除第一掩膜層207,去除第一掩膜層207的方法為灰化。 After the P+ region 208 is formed, the first mask layer 207 is removed, and the method of removing the first mask layer 207 is ashing.
接著,參考圖8,在所述襯底200和凹槽201形成的表面上形成圖形化的第二掩膜層209,定義第二離子注入的區域,然後,以所述圖形化的第二掩膜層209為掩膜,進行第二離子注入。第二離子注入的類型與第二阱區205的類型相同。 Next, referring to FIG. 8, a patterned second mask layer 209 is formed on the surface formed by the substrate 200 and the recess 201, defining a region of the second ion implantation, and then, with the patterned second mask The film layer 209 is a mask for performing a second ion implantation. The second ion implantation is of the same type as the second well region 205.
其中,第二掩膜層209可以為光刻膠、氧化矽、氮氧化矽、氮化鉭或氮化鈦。本實施例較佳選用光刻膠。 The second mask layer 209 may be a photoresist, ruthenium oxide, ruthenium oxynitride, tantalum nitride or titanium nitride. In this embodiment, a photoresist is preferably used.
本實施例中,第二阱區205為N阱區。對凹槽底部的N阱區進行第二離子注入,形成N+區域210,注入的離子為硼離子。所述硼離子注入的劑量小於1×1014atom/cm2,硼離子注入的能量小於1000Kev。所述硼離子注入時的射頻電壓和硼離子注入的時間根據離子注入工藝時使用的濺射機台而定,因此,硼離子注入時的射頻電壓和硼離子注入的時間根據具體離子注入工藝的不同而不同。 In this embodiment, the second well region 205 is an N-well region. A second ion implantation is performed on the N well region at the bottom of the recess to form an N+ region 210, and the implanted ions are boron ions. The boron ion implantation dose is less than 1 x 10 14 atoms/cm 2 and the boron ion implantation energy is less than 1000 KeV. The radio frequency voltage and the boron ion implantation time during the boron ion implantation are determined according to the sputtering machine used in the ion implantation process, and therefore, the radio frequency voltage and the boron ion implantation time during the boron ion implantation are according to a specific ion implantation process. Different and different.
形成N+區域210後,去除第二掩膜層209,去除第二掩膜層209的方法為灰化。 After the N+ region 210 is formed, the second mask layer 209 is removed, and the method of removing the second mask layer 209 is ashing.
本實施例中,對凹槽201底部進行第一離子注入和第二離子注入後,在P阱區形成P+區域208,在N阱區形成N+區域210。P+區域208和N+區域210的形成增加了凹槽201底部的耗盡區中離子和空穴的濃度,使得耗盡區的寬度變窄。因此在襯底中形成的凹槽的寬度可以相應縮小,後續在P阱區內形成的NMOS電晶體的漏極和在N阱區內形成的PMOS電晶體源極之間的距離也相應縮小,而且不會發生源極或漏極與同類型摻雜的阱區之間的穿通(Punchthrough),即,不會發生後續形成的NMOS電晶體的漏極與N阱區之間的穿通,後續形成的PMOS電晶體中的源極與P阱區之間的穿通。 In this embodiment, after the first ion implantation and the second ion implantation are performed on the bottom of the recess 201, a P+ region 208 is formed in the P well region, and an N+ region 210 is formed in the N well region. The formation of the P+ region 208 and the N+ region 210 increases the concentration of ions and holes in the depletion region at the bottom of the groove 201, so that the width of the depletion region is narrowed. Therefore, the width of the recess formed in the substrate can be correspondingly reduced, and the distance between the drain of the NMOS transistor formed in the P well region and the source of the PMOS transistor formed in the N well region is correspondingly reduced. Moreover, the punch-through between the source or the drain and the well region doped with the same type does not occur, that is, the punch-through between the drain and the N-well region of the subsequently formed NMOS transistor does not occur, and subsequent formation The punch-through between the source and the P-well region in the PMOS transistor.
需要說明的是,P+區域208中磷離子的注入劑量小於1×1014atom/cm2,其中1×1014atom/cm2為後續在P阱區形成NMOS電晶體中的漏極或源極的濃度。N+區域210中硼離子的注入劑量小於1×1014atom/cm2,其中1×1014atom/cm2是後續在P阱區形成NMOS電晶體中的漏極或源極的濃度。1×1014atom/cm2也為隔離結構發生擊穿時的離子注入濃度。P+區域中磷離子的注入劑量和N+區域中硼離子的注入劑量之所以小於1×1014atom/cm2。是因為,如果離子注入的劑量太大,後續形成的隔離結構容易被擊穿,起不到隔離作用,使得半導體器件無法工作。 It should be noted that the implantation dose of phosphorus ions in the P+ region 208 is less than 1×10 14 atoms/cm 2 , wherein 1×10 14 atoms/cm 2 is the drain or source in the subsequent formation of the NMOS transistor in the P well region. concentration. The implantation dose of boron ions in the N+ region 210 is less than 1 × 10 14 atoms/cm 2 , where 1 × 10 14 atoms/cm 2 is the concentration of the drain or source in the subsequent formation of the NMOS transistor in the P well region. 1 × 10 14 atoms/cm 2 is also the ion implantation concentration at which the isolation structure is broken down. The implantation dose of phosphorus ions in the P+ region and the implantation dose of boron ions in the N+ region are less than 1 × 10 14 atoms/cm 2 . This is because if the dose of ion implantation is too large, the subsequently formed isolation structure is easily broken down and does not function as an isolation, making the semiconductor device inoperable.
需要繼續說明的是,如果不在步驟S12中的所述凹槽 側壁形成側牆214,則在凹槽201的側壁也會被離子注入,尤其在後續形成PMOS電晶體或者NMOS電晶體中的柵極附件被注入。當在凹槽201的側壁被離子注入時,使得後續形成的隔離結構的擊穿電壓(Breakdown Voltage)變小,從而使得後續形成的隔離結構的隔離效果不好,很容易被擊穿。當在後續形成PMOS電晶體或者NMOS電晶體中的柵極附近被注入時,會使得半導體器件的閾值電壓(VT)增加,飽和電流(Idsat)變小,從而使得需要開啟半導體器件能量變大,相當於增加能耗,因此,容易發生窄器件效應(Narrow Width Effect)。上述兩種現象尤其在凹槽尺寸減小的情況下更加明顯。 It should be further explained that if the groove is not in step S12 The sidewalls form the sidewalls 214, and the sidewalls of the recesses 201 are also ion implanted, especially in the subsequent formation of PMOS transistors or gate attachments in the NMOS transistors. When the sidewall of the recess 201 is ion-implanted, the breakdown voltage of the subsequently formed isolation structure is made small, so that the isolation structure of the subsequently formed isolation structure is not good and is easily broken down. When implanted in the vicinity of the gate in the subsequent formation of the PMOS transistor or the NMOS transistor, the threshold voltage (VT) of the semiconductor device is increased, and the saturation current (Idsat) is made small, so that the energy required to turn on the semiconductor device becomes large, This is equivalent to increasing the power consumption, so it is easy to have a Narrow Width Effect. Both of the above phenomena are more pronounced especially in the case where the groove size is reduced.
在其他實施例中,也可以先對凹槽201底部的第二阱區205進行離子注入,然後再對凹槽201底部的第一阱區204進行離子注入。 In other embodiments, the second well region 205 at the bottom of the recess 201 may be ion-implanted first, and then the first well region 204 at the bottom of the recess 201 may be ion-implanted.
參考圖8和圖9,離子注入後,去除所述側牆214。 Referring to Figures 8 and 9, after ion implantation, the sidewall spacers 214 are removed.
去除側牆214的方法為濕法腐蝕,屬於本領域技術人員的熟知技術,在此不再贅述。 The method of removing the sidewall spacers 214 is wet etching, which is well known to those skilled in the art and will not be described herein.
在其他實施例中也可以對側牆214不進行去除。 Side wall 214 may also be removed in other embodiments.
接著,繼續參考圖9和圖10,執行圖4中的步驟S15,去除所述側牆214後,在所述凹槽201內填充介質層211形成隔離結構212。 Then, referring to FIG. 9 and FIG. 10, step S15 in FIG. 4 is performed. After the sidewall spacers 214 are removed, the dielectric layer 211 is filled in the recesses 201 to form the isolation structure 212.
其中,介質層211的材料為氧化矽。本實施例中,採用化學氣相沈積的方法在所述凹槽201內和阻擋層203的表面形成氧化矽,例如,採用正矽酸乙酯(TEOS)和臭 氧(O3)反應沈積氧化矽(請參考步驟S12),然後採用化學機械抛光的方法去除阻擋層203表面的氧化矽層,形成隔離結構212,本實施例的隔離結構212為淺溝槽隔離(STI)結構。其中,阻擋層203為化學機械抛光的停止層,保護襯底不受損傷。 The material of the dielectric layer 211 is cerium oxide. In this embodiment, a method of chemical vapor deposition is used to form ruthenium oxide in the groove 201 and on the surface of the barrier layer 203, for example, deposition of ruthenium oxide using tetraethyl orthosilicate (TEOS) and ozone (O 3 ). (Refer to step S12), and then removing the ruthenium oxide layer on the surface of the barrier layer 203 by chemical mechanical polishing to form the isolation structure 212. The isolation structure 212 of the present embodiment is a shallow trench isolation (STI) structure. Wherein, the barrier layer 203 is a stop layer of chemical mechanical polishing to protect the substrate from damage.
在其他實施例中,也可以在凹槽201內採用熱生長的方法形成氧化矽。形成的隔離結構212為局部場氧化隔離(LOCOS)結構。 In other embodiments, yttrium oxide may also be formed by thermal growth in the recess 201. The isolation structure 212 formed is a local field oxide isolation (LOCOS) structure.
後續形成的半導體器件的工藝為本領域技術人員熟知領域。 The process of subsequently forming a semiconductor device is well known in the art.
需要說明的是,本實施例中,在所述淺溝槽隔離結構下面形成P+區域208和N+區域210,還可以使得靜電放電防護電路更容易觸發,進而保護半導體器件正常工作。 It should be noted that, in this embodiment, the P+ region 208 and the N+ region 210 are formed under the shallow trench isolation structure, which can also make the ESD protection circuit easier to trigger, thereby protecting the normal operation of the semiconductor device.
具體為,靜電放電(electrostatic discharge,ESD)是指在短瞬間大量流至半導體器件的電流。此大電流的來源有很多種。例如,人體和機器放電,分別稱為人體放電模型(Human Body Model,HBM)和機器放電模型(machine model,MM)。半導體器件容易受到靜電放電的影響而遭破壞或損毀。尤其是當半導體器件尺寸減小至深次微米的範圍時,靜電放電更容易損壞半導體器件。 Specifically, electrostatic discharge (ESD) refers to a current that flows to a semiconductor device in a large amount in a short time. There are many sources of this large current. For example, human body and machine discharges are called the Human Body Model (HBM) and the machine model (MM), respectively. Semiconductor devices are susceptible to damage or damage due to electrostatic discharge. Especially when the size of the semiconductor device is reduced to the range of deep submicron, electrostatic discharge is more likely to damage the semiconductor device.
本實施例中,在淺溝槽隔離結構下面形成P+區域208和N+區域210,以使P阱區和N阱區的濃度都有所增加,從而減小靜電放電防護電路的觸發電壓(Trigger Voltage),當有靜電放電現象發生時,本發明可以更容 易開啟靜電防護電路,以保護半導體器件不受破壞或損毀。 In this embodiment, the P+ region 208 and the N+ region 210 are formed under the shallow trench isolation structure to increase the concentration of the P well region and the N well region, thereby reducing the trigger voltage of the ESD protection circuit (Trigger Voltage ), when there is an electrostatic discharge phenomenon, the present invention can be more It is easy to turn on the static protection circuit to protect the semiconductor device from damage or damage.
參考圖10,本發明還提供了一種半導體結構,包括:具有凹槽201的半導體襯底200(參考圖5),所述凹槽201的一側半導體襯底為第一有源區I,所述凹槽的另一側半導體襯底為第二有源區Π;位於凹槽201側壁的側牆214;位於第一有源區內I的第一阱區204,位於第二有源區Π內的第二阱區205,所述第一阱區204與所述第二阱區205在所述凹槽底部的連接處形成耗盡區;所述凹槽201底部的第一阱區204的離子濃度大於第一阱區204其他位置的濃度,所述凹槽201底部的第二阱區205的離子濃度大於第二阱區205其他位置的濃度;填充所述凹槽的介質層212。 Referring to FIG. 10, the present invention further provides a semiconductor structure including: a semiconductor substrate 200 having a recess 201 (refer to FIG. 5), a semiconductor substrate of one side of the recess 201 being a first active region I, The other side semiconductor substrate of the recess is a second active region Π; a sidewall spacer 214 located at a sidewall of the recess 201; and a first well region 204 located in the first active region I, located in the second active region a second well region 205, the first well region 204 and the second well region 205 form a depletion region at a junction of the bottom of the recess; the first well region 204 at the bottom of the recess 201 The ion concentration is greater than the concentration of other locations of the first well region 204, the ion concentration of the second well region 205 at the bottom of the recess 201 is greater than the concentration of other locations of the second well region 205; and the dielectric layer 212 filling the recess.
本發明雖然已以較佳實施例公開如上,但其並不是用來限定本發明,任何本領域技術人員在不脫離本發明的精神和範圍內,都可以利用上述揭示的方法和技術內容對本發明技術方案做出可能的變動和修改,因此,凡是未脫離本發明技術方案的內容,依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化及修飾,均屬於本發明技術方案的保護範圍。 The present invention has been disclosed in the preferred embodiments as described above, but it is not intended to limit the invention, and the present invention may be utilized by the method and technical contents disclosed above without departing from the spirit and scope of the invention. The technical solutions make possible changes and modifications. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments in accordance with the technical spirit of the present invention are not included in the technical solutions of the present invention. protected range.
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CN105529250B (en) * | 2014-09-30 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | High-energy ion implantation method and semiconductor structure |
CN117316947B (en) * | 2023-11-27 | 2024-05-24 | 厦门科塔电子有限公司 | ESD protection device |
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US6228726B1 (en) * | 2000-03-06 | 2001-05-08 | Taiwan Semiconductor Manufacturing Company | Method to suppress CMOS device latchup and improve interwell isolation |
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KR100511925B1 (en) * | 2003-12-23 | 2005-09-05 | 주식회사 하이닉스반도체 | Method for forming element isolating layer of semiconductor device |
KR100561519B1 (en) * | 2003-12-30 | 2006-03-17 | 동부아남반도체 주식회사 | Well Making Method In The Semiconductor Device Manufacture Processing |
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US20070026599A1 (en) * | 2005-07-27 | 2007-02-01 | Advanced Micro Devices, Inc. | Methods for fabricating a stressed MOS device |
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KR101477606B1 (en) | 2014-12-30 |
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