TWI523115B - A semiconductor structure forming method and a semiconductor structure - Google Patents

Description

Semiconductor structure forming method and semiconductor structure

The present invention relates to semiconductor fabrication techniques, and more particularly to a method of forming a semiconductor structure and a semiconductor structure.

As semiconductor technology continues to evolve, the size of semiconductor devices on wafers continues to shrink. Accordingly, the isolation structure that isolates the semiconductor device needs to be continuously reduced. U.S. Patent Publication No. 6,171,910 B1 discloses a method of reducing the size of a semiconductor device.

Referring to FIGS. 1 through 3, a shallow trench isolation structure between existing semiconductor structures is fabricated as follows: Referring to FIG. 1, a semiconductor substrate 100 is provided on which a recess 102 is formed.

Referring to FIG. 2, a dielectric layer is formed in the recess 102 and on the surface of the substrate 100 to remove the dielectric layer above the surface of the recess 102 to form a shallow trench isolation structure (STI) 104. After the shallow trench isolation structures 104 are formed, ion implantation is performed in the substrates on both sides of the shallow trench isolation structures 104 to form N well regions 105 and P well regions 106.

Referring to FIG. 3, after forming the N well region 105 and the P well region 106, the N well The region 105 forms a PMOS transistor 107 in which a P-type source 108 and a drain 109 are formed in the PMOS transistor. An NMOS transistor 110 is formed in the P well region 106 in which an N-type source 111 and a drain 112 are formed in the NMOS transistor.

The shallow trench isolation structure in the prior art cannot continue to shrink, and the area occupied by the wafer is large.

The problem solved by the present invention is that the shallow trench isolation structure in the prior art cannot continue to shrink, and the area occupied by the wafer is large.

In order to solve the above problems, the present invention provides a method of forming a semiconductor structure, comprising: providing a semiconductor substrate, forming a recess in the semiconductor substrate, the recess dividing the semiconductor substrate into a first active region and a second active region; forming a sidewall in the sidewall of the recess; forming a first well region in the first active region, and forming a second well region in the second active region, the first a junction of the well region and the second well region forms a depletion region; after forming the sidewall, a first ion implantation is performed in the first well region at the bottom of the trench, in the second well region at the bottom of the trench Performing a second ion implantation, the type of the first ion implantation is the same as the type of the first well region, the type of the second ion implantation is the same as the type of the second well region; after the ion implantation, filling the dielectric layer in the groove Isolation structure.

Optionally, performing the first ion implantation in the first well region at the bottom of the groove comprises: forming a patterned first mask layer on the surface formed by the substrate and the groove, defining the first a region of ion implantation; performing a first ion implantation using the patterned first mask layer as a mask; and removing the patterned first mask layer after the first ion implantation.

Optionally, performing the second ion implantation in the second well region at the bottom of the groove comprises: forming a patterned second mask layer on the surface formed by the substrate and the groove, defining a second a region of ion implantation; performing a second ion implantation using the patterned second mask layer as a mask; and removing the patterned second mask layer after the second ion implantation.

Optionally, the concentration of the first ion implantation is less than the ion implantation concentration when the isolation structure is broken down.

Optionally, the concentration of the first ion implantation is less than 1×10 ¹⁴ atoms/cm ² .

Optionally, the concentration of the second ion implantation is less than the ion implantation concentration when the isolation structure is broken down.

Optionally, the concentration of the second ion implantation is less than 1×10 ¹⁴ atoms/cm ² .

Optionally, the material of the sidewall is yttrium oxide or tantalum nitride.

Optionally, the method for forming the sidewall spacer includes: Depositing a material layer of the sidewall on the surface of the groove; etching the material layer of the sidewall.

Optionally, after the ion implantation, the step of filling the dielectric layer to form the isolation structure in the groove further comprises the step of removing the sidewall spacer.

Optionally, the method of removing the sidewall is wet etching.

Optionally, the step of forming a recess on the semiconductor substrate further comprises the steps of: forming an epoxy layer on the substrate, and forming a barrier layer on the pad oxide layer.

Optionally, the material of the pad layer is ruthenium oxide, and the material of the barrier layer is tantalum nitride.

Optionally, before the forming a sidewall of the sidewall of the recess, the method further includes the step of forming a ruthenium oxide layer on the surface of the recess.

Optionally, the method for forming the ruthenium oxide layer is thermal oxidation.

Optionally, the material of the dielectric layer is cerium oxide.

Optionally, the method for forming a groove on the semiconductor substrate comprises: forming a patterned third mask layer on the semiconductor substrate, defining a position of the groove; The triple mask layer etches the semiconductor substrate as a mask.

The present invention also provides a semiconductor structure comprising: a semiconductor substrate having a recess, one side of the recessed semiconductor substrate being a first active region, and the other side of the recessed semiconductor substrate being second Source area a sidewall located in the sidewall of the recess; a first well region in the first active region, a second well region in the second active region, the first well region and the second well region being a junction at the bottom of the groove forms a depletion region; an ion concentration of the first well region at the bottom of the groove is greater than a concentration of other locations in the first well region, and an ion concentration of the second well region at the bottom of the groove is greater than a second The concentration of other locations in the well region; the dielectric layer filling the recess.

Compared with the prior art, the technical solution of the present invention has the following advantages: performing first ion implantation in a first well region at the bottom of the groove, and performing second ion implantation in a second well region at the bottom of the groove The first ion implantation is of the same type as the first well region, and the second ion implantation is of the same type as the second well region, so that the ion concentration of the first well region and the second well region at the bottom of the groove are both The increase is such that the width of the depletion region formed by the first well region and the second well region at the bottom of the recess is reduced. After ion implantation, a dielectric layer is filled in the recess to form an isolation structure. Then, a drain and a source are formed on both sides of the isolation structure, wherein the drain is a drain of a transistor formed in the first well region adjacent to the isolation structure, and the source is extremely in the second well a source of a transistor adjacent to the isolation structure in the region. When the size of the isolation structure is reduced, the distance between the drain and the source on both sides of the isolation structure is correspondingly reduced, but even if the size of the isolation structure is reduced, even if a voltage is applied to the source or the drain There is also no punchthrough between the source, the drain and the well of the same type, that is, the drain of the first well region does not pass through with the second well region, and the second well region of The source does not pass through with the first well region. Therefore, when the ion implantation is performed on the bottom of the groove, the size of the isolation structure can be reduced, thereby reducing the occupation area of the isolation structure on the wafer. Moreover, the present invention forms a sidewall on the sidewall of the recess to prevent ion implantation of the semiconductor substrate at the sidewall of the recess, and in particular to prevent ion implantation near the gate in the subsequent formation of the PMOS transistor or the NMOS transistor. When the semiconductor substrate at the sidewall of the recess is not ion-implanted, the breakdown voltage of the subsequently formed isolation structure can be increased, so that the isolation effect of the subsequently formed isolation structure can be improved. When the vicinity of the gate in the PMOS transistor or the NMOS transistor is not ion-implanted, the threshold voltage (VT) of the semiconductor device may be decreased, and the saturation current (Idsat) may be increased, thereby reducing the energy required to turn on the semiconductor device. This is equivalent to reducing the power consumption, so the Narrow Width Effect can be avoided.

Further, the ion implantation is performed at the bottom of the groove to increase the concentration of the first well region and the second well region, and the trigger voltage of the electrostatic discharge protection circuit can be reduced. When an electrostatic discharge phenomenon occurs, the present invention can more easily trigger an electrostatic protection circuit to protect the semiconductor device from damage or damage.

100‧‧‧Semiconductor substrate

102‧‧‧ Groove

104‧‧‧Shallow trench isolation structure

105‧‧‧N well zone

106‧‧‧P-well zone

107‧‧‧ PMOS transistor

108‧‧‧ source

109‧‧‧Drain

110‧‧‧NMOS transistor

111‧‧‧ source

112‧‧‧Drain

200‧‧‧Semiconductor substrate

201‧‧‧ Groove

202‧‧‧Oxygen layer

203‧‧‧Block

204‧‧‧First Well Area

205‧‧‧Second well area

207‧‧‧First mask layer

208‧‧‧P+ area

209‧‧‧second mask layer

210‧‧‧N+ area

211‧‧‧ dielectric layer

212‧‧‧Isolation structure

213‧‧‧Oxide layer

214‧‧‧ Side wall

1 to 3 are schematic cross-sectional views showing a method of fabricating a shallow trench isolation structure between semiconductor structures in the prior art; and FIG. 4 is a flow chart showing a method of forming a semiconductor structure according to an embodiment of the present invention; FIG. 5 to FIG. 10 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to an embodiment of the present invention.

The inventors have discovered and analyzed that the shallow trench isolation structure in the prior art cannot continue to shrink, and the reason for occupying a large area of the wafer is as follows: Referring to FIG. 3, in the prior art, holes of the P well region 106 are diffused to the N well region. 105, electrons of the N well region 105 are diffused into the P well region 106, and therefore, holes diffused into the N well region 105 and electrons diffused into the P well region 106 are combined at the bottom of the shallow trench isolation structure 104 to form a depletion region. . When the device is working, it is necessary to apply a voltage to the PMOS transistor, the source and the drain of the NMOS transistor, and the width of the depletion region is increased by the applied voltage. If the size of the shallow trench isolation structure 104 is reduced at this time, Corresponding to reducing the distance between the drain 112 of the NMOS transistor and the PMOS transistor source 108, the depletion region with increased width easily enters the drain 112 of the NMOS transistor and the PMOS transistor source 108, resulting in source 108. The punchthrough between the drain 112 and the well region doped with the same type makes the semiconductor device inoperable. Specifically, electrons in the depletion region having an increased width enter the drain 112 in the NMOS transistor, so that punch-through occurs between the drain 112 and the N well region 105 of the NMOS transistor. Holes in the increased width depletion region enter the source 108 in the PMOS transistor such that a punchthrough occurs between the source 108 and the P well region 106 of the PMOS transistor. Therefore, the size of the shallow trench isolation structure cannot continue to shrink, occupying in the wafer The area is large.

To this end, the inventors have studied a method of forming a semiconductor structure, and FIG. 4 is a schematic flow chart of a method of forming a semiconductor structure according to an embodiment of the present invention. 5 to 8 are schematic cross-sectional views showing a process of forming a semiconductor structure according to an embodiment of the present invention. The method of forming the semiconductor structure of the present invention will be described in detail below in conjunction with FIGS. 5 to 8 and FIG.

Referring first to FIG. 5, step S11 in FIG. 4 is performed to provide a semiconductor substrate 200 on which a recess 201 is formed, which divides the semiconductor substrate into first active regions I and Two active areas.

The material of the substrate 200 may be a germanium substrate, a germanium substrate, a III-V element compound substrate, a tantalum carbide substrate or a stacked structure thereof, or an insulator upper structure, or a diamond substrate, or a person skilled in the art. Other semiconductor material substrates are known.

In this embodiment, a pad layer 202 is formed on the semiconductor 200, and a barrier layer 203 is formed on the pad oxide layer 202. The barrier layer 203 functions to protect the surface of the semiconductor substrate. The material of the barrier layer 203 is tantalum nitride, and the formation method is chemical vapor deposition. The function of the pad layer 202 is to prevent stress damage between the barrier layer 203 and the semiconductor substrate 200 due to the difference in thermal expansion coefficient. The material of the pad oxygen layer 202 is ruthenium oxide, and the formation method is chemical vapor deposition.

After the barrier layer 203 is formed, a patterned mask layer (not shown) is formed on the surface of the barrier layer 203, and the patterned mask layer is used as a mask, and the barrier layer 203 and the pad oxide layer 202 are sequentially disposed. The substrate 200 is etched to form a recess 201 in the substrate 200. The groove 201 will be a semiconductor The substrate is divided into a first active region I and a second active region Π.

After the recess 201 is formed, a ruthenium oxide layer 213 is formed on the surface of the recess 201, and the ruthenium oxide layer 213 is formed by thermal oxidation. The surface of the groove 201 is formed by the yttrium oxide layer 213. Firstly, during the process of forming the groove 201 by the etching process, the surface of the groove 201 is damaged, and the surface damaged yttrium can be transformed into yttrium oxide by a thermal oxidation process. In order to make the isolation effect of the subsequently formed shallow trench isolation structure better. Moreover, the angle at the bottom corner of the groove formed by the etching process is relatively sharp, and it is easy to concentrate the charge to the tip to form a tip discharge, thereby generating a breakdown voltage at the subsequent shallow trench isolation structure, and thus, The surface of the groove forms a layer of ruthenium oxide, which can make the corners at the bottom of the groove smooth, reducing the occurrence of tip discharge.

Of course, in other embodiments, the ruthenium oxide layer 213 may not be formed on the surface of the recess 201.

Next, referring to FIG. 6, step S12 in FIG. 4 is performed to form a sidewall 214 on the sidewall of the recess 201.

The material of the sidewall 214 may be tantalum oxide or tantalum nitride. The sidewall 214 is formed by first forming a material layer of the sidewall by chemical vapor deposition on the surface of the ruthenium oxide layer 213 of the recess 201, and then etching the material layer of the sidewall to form the sidewall 214. . In this embodiment, the material of the sidewall 214 is yttrium oxide. The cerium oxide is deposited by the reaction of ethyl orthosilicate (TEOS) and ozone (O ₃ ). The reason why the ruthenium oxide is deposited by the reaction of TEOS and ozone (O ₃ ) is because: on the one hand, the deposition of ruthenium oxide by the reaction of TEOS and O ₃ is good. Filling capacity, suitable for filling high aspect ratio grooves, on the other hand, using TEOS and ozone (O ₃ ) to deposit yttrium oxide by thermal chemical vapor deposition, not like plasma reduction Pressure chemical vapor deposition (HDPCVD) is equally susceptible to damage to the corners of the semiconductor substrate. Further, the side wall 214 formed using ethyl orthosilicate (TEOS) and ozone (O ₃ ) is easily removed in a subsequent process.

In the subsequent ion implantation step, the sidewall spacers 214 may protect the sidewalls of the recess 201 from ion implantation, and may also protect the vicinity of the gate in the PMOS transistor or the NMOS transistor from being implanted by ions.

Next, with reference to FIG. 6, step S13 in FIG. 4 is performed, a first well region 204 is formed in the first active region I, and a second well region 205 is formed in the second active region ,. The junction of the first well region 204 and the second well region 205 forms a depletion region.

When the transistor in the first active region I is an NMOS transistor, the first active region I is doped with a trivalent dopant to form a P-well region, wherein the trivalent dopant is boron ion; When the transistor in the active region I is a PMOS transistor, the pentavalent dopant is doped in the first active region I to form an N-well region, wherein the pentavalent dopant is a phosphorus ion, an arsenic ion or a cerium ion. The method of forming the first well region 204 in the first active region I is well known to those skilled in the art and will not be described herein. When the transistor in the first active region I is an NMOS transistor, when the first active region I is doped with a trivalent dopant to form a P well region, then the second active region is doped with pentavalent doping. The agent forms an N-well region; when the transistor in the first active region I is a PMOS transistor, when the first active region I is doped with a pentavalent dopant to form an N-well region, then in the second active region Doping three The valence dopant forms a P-well region. The method of forming the second well region 205 in the second active region 为本 is well known to those skilled in the art and will not be described herein. In this embodiment, the transistor in the first active region I is an NMOS transistor, which is doped with a trivalent dopant in the first active region I to form a P-well region, and is doped in the second active region. The valence dopant forms an N-well region. After the N-well region is formed, a depletion region is formed at the junction of the N-well region and the P-well region formed at the first active region I.

In other embodiments, the N-well region may be formed by doping the pentavalent dopant in the first active region I, and the P-well region may be formed by doping the trivalent dopant into the second active region. invention.

Next, referring to FIG. 7 and FIG. 8, step S14 in FIG. 4 is performed, after the sidewall spacer 214 is formed, a first ion implantation is performed in the first well region 204 at the bottom of the recess 201, at the bottom of the recess 201. A second ion implantation is performed in the second well region 205, the first ion implantation is of the same type as the first well region 204, and the second ion implantation is of the same type as the second well region 205.

Specifically, referring to FIG. 7, a patterned first mask layer 207 is formed on the surface formed by the substrate 200 and the recess 201, defining a region of the first ion implantation, and then, with the patterned first The mask layer is a mask for performing the first ion implantation. The type of the first ion implantation is the same as that of the first well region 204.

The first mask layer 207 may be a photoresist, ruthenium oxide, ruthenium oxynitride, tantalum nitride or titanium nitride. In this embodiment, a photoresist is preferably used.

In this embodiment, the first well region 204 is a P well region. A first ion implantation is performed on the P well region at the bottom of the groove to form a P+ region 208, and the implanted ions are phosphorus ions, arsenic ions or erbium ions. The dose of the phosphorus ion implantation is less than 1 × 10 ¹⁴ atoms/cm ² , and the energy of the phosphorus ion implantation is less than 1000 KeV. The RF voltage and the time of the phosphorus ion implantation during the phosphorus ion implantation are determined according to the sputtering machine used in the ion implantation process, and therefore, the RF voltage and the time of the phosphorus ion implantation during the phosphorus ion implantation are according to a specific ion implantation process. Different and different.

After the P+ region 208 is formed, the first mask layer 207 is removed, and the method of removing the first mask layer 207 is ashing.

Next, referring to FIG. 8, a patterned second mask layer 209 is formed on the surface formed by the substrate 200 and the recess 201, defining a region of the second ion implantation, and then, with the patterned second mask The film layer 209 is a mask for performing a second ion implantation. The second ion implantation is of the same type as the second well region 205.

The second mask layer 209 may be a photoresist, ruthenium oxide, ruthenium oxynitride, tantalum nitride or titanium nitride. In this embodiment, a photoresist is preferably used.

In this embodiment, the second well region 205 is an N-well region. A second ion implantation is performed on the N well region at the bottom of the recess to form an N+ region 210, and the implanted ions are boron ions. The boron ion implantation dose is less than 1 x 10 ¹⁴ atoms/cm ² and the boron ion implantation energy is less than 1000 KeV. The radio frequency voltage and the boron ion implantation time during the boron ion implantation are determined according to the sputtering machine used in the ion implantation process, and therefore, the radio frequency voltage and the boron ion implantation time during the boron ion implantation are according to a specific ion implantation process. Different and different.

After the N+ region 210 is formed, the second mask layer 209 is removed, and the method of removing the second mask layer 209 is ashing.

In this embodiment, after the first ion implantation and the second ion implantation are performed on the bottom of the recess 201, a P+ region 208 is formed in the P well region, and an N+ region 210 is formed in the N well region. The formation of the P+ region 208 and the N+ region 210 increases the concentration of ions and holes in the depletion region at the bottom of the groove 201, so that the width of the depletion region is narrowed. Therefore, the width of the recess formed in the substrate can be correspondingly reduced, and the distance between the drain of the NMOS transistor formed in the P well region and the source of the PMOS transistor formed in the N well region is correspondingly reduced. Moreover, the punch-through between the source or the drain and the well region doped with the same type does not occur, that is, the punch-through between the drain and the N-well region of the subsequently formed NMOS transistor does not occur, and subsequent formation The punch-through between the source and the P-well region in the PMOS transistor.

It should be noted that the implantation dose of phosphorus ions in the P+ region 208 is less than 1×10 ¹⁴ atoms/cm ² , wherein 1×10 ¹⁴ atoms/cm ² is the drain or source in the subsequent formation of the NMOS transistor in the P well region. concentration. The implantation dose of boron ions in the N+ region 210 is less than 1 × 10 ¹⁴ atoms/cm ² , where 1 × 10 ¹⁴ atoms/cm ² is the concentration of the drain or source in the subsequent formation of the NMOS transistor in the P well region. 1 × 10 ¹⁴ atoms/cm ² is also the ion implantation concentration at which the isolation structure is broken down. The implantation dose of phosphorus ions in the P+ region and the implantation dose of boron ions in the N+ region are less than 1 × 10 ¹⁴ atoms/cm ² . This is because if the dose of ion implantation is too large, the subsequently formed isolation structure is easily broken down and does not function as an isolation, making the semiconductor device inoperable.

It should be further explained that if the groove is not in step S12 The sidewalls form the sidewalls 214, and the sidewalls of the recesses 201 are also ion implanted, especially in the subsequent formation of PMOS transistors or gate attachments in the NMOS transistors. When the sidewall of the recess 201 is ion-implanted, the breakdown voltage of the subsequently formed isolation structure is made small, so that the isolation structure of the subsequently formed isolation structure is not good and is easily broken down. When implanted in the vicinity of the gate in the subsequent formation of the PMOS transistor or the NMOS transistor, the threshold voltage (VT) of the semiconductor device is increased, and the saturation current (Idsat) is made small, so that the energy required to turn on the semiconductor device becomes large, This is equivalent to increasing the power consumption, so it is easy to have a Narrow Width Effect. Both of the above phenomena are more pronounced especially in the case where the groove size is reduced.

In other embodiments, the second well region 205 at the bottom of the recess 201 may be ion-implanted first, and then the first well region 204 at the bottom of the recess 201 may be ion-implanted.

Referring to Figures 8 and 9, after ion implantation, the sidewall spacers 214 are removed.

The method of removing the sidewall spacers 214 is wet etching, which is well known to those skilled in the art and will not be described herein.

Side wall 214 may also be removed in other embodiments.

Then, referring to FIG. 9 and FIG. 10, step S15 in FIG. 4 is performed. After the sidewall spacers 214 are removed, the dielectric layer 211 is filled in the recesses 201 to form the isolation structure 212.

The material of the dielectric layer 211 is cerium oxide. In this embodiment, a method of chemical vapor deposition is used to form ruthenium oxide in the groove 201 and on the surface of the barrier layer 203, for example, deposition of ruthenium oxide using tetraethyl orthosilicate (TEOS) and ozone (O ₃ ). (Refer to step S12), and then removing the ruthenium oxide layer on the surface of the barrier layer 203 by chemical mechanical polishing to form the isolation structure 212. The isolation structure 212 of the present embodiment is a shallow trench isolation (STI) structure. Wherein, the barrier layer 203 is a stop layer of chemical mechanical polishing to protect the substrate from damage.

In other embodiments, yttrium oxide may also be formed by thermal growth in the recess 201. The isolation structure 212 formed is a local field oxide isolation (LOCOS) structure.

The process of subsequently forming a semiconductor device is well known in the art.

It should be noted that, in this embodiment, the P+ region 208 and the N+ region 210 are formed under the shallow trench isolation structure, which can also make the ESD protection circuit easier to trigger, thereby protecting the normal operation of the semiconductor device.

Specifically, electrostatic discharge (ESD) refers to a current that flows to a semiconductor device in a large amount in a short time. There are many sources of this large current. For example, human body and machine discharges are called the Human Body Model (HBM) and the machine model (MM), respectively. Semiconductor devices are susceptible to damage or damage due to electrostatic discharge. Especially when the size of the semiconductor device is reduced to the range of deep submicron, electrostatic discharge is more likely to damage the semiconductor device.

In this embodiment, the P+ region 208 and the N+ region 210 are formed under the shallow trench isolation structure to increase the concentration of the P well region and the N well region, thereby reducing the trigger voltage of the ESD protection circuit (Trigger Voltage ), when there is an electrostatic discharge phenomenon, the present invention can be more It is easy to turn on the static protection circuit to protect the semiconductor device from damage or damage.

Referring to FIG. 10, the present invention further provides a semiconductor structure including: a semiconductor substrate 200 having a recess 201 (refer to FIG. 5), a semiconductor substrate of one side of the recess 201 being a first active region I, The other side semiconductor substrate of the recess is a second active region Π; a sidewall spacer 214 located at a sidewall of the recess 201; and a first well region 204 located in the first active region I, located in the second active region a second well region 205, the first well region 204 and the second well region 205 form a depletion region at a junction of the bottom of the recess; the first well region 204 at the bottom of the recess 201 The ion concentration is greater than the concentration of other locations of the first well region 204, the ion concentration of the second well region 205 at the bottom of the recess 201 is greater than the concentration of other locations of the second well region 205; and the dielectric layer 212 filling the recess.

The present invention has been disclosed in the preferred embodiments as described above, but it is not intended to limit the invention, and the present invention may be utilized by the method and technical contents disclosed above without departing from the spirit and scope of the invention. The technical solutions make possible changes and modifications. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments in accordance with the technical spirit of the present invention are not included in the technical solutions of the present invention. protected range.

Claims (18)

A method of forming a semiconductor structure, comprising: providing a semiconductor substrate, forming a recess in the semiconductor substrate, the recess dividing the semiconductor substrate into a first active region and a second active region Forming a sidewall in the sidewall of the recess; forming a first well region in the first active region, forming a second well region in the second active region, the first well region and the second a junction of the well region forms a depletion region; after forming the sidewall, a first ion implantation is performed in the first well region at the bottom of the trench, and a second ion implantation is performed in the second well region at the bottom of the trench The first ion implantation is of the same type as the first well region, the second ion implantation is of the same type as the second well region, and the first well region at the bottom of the groove has a larger ion concentration than the first well region. The concentration of the position, the ion concentration of the second well region at the bottom of the groove is greater than the concentration of other locations of the second well region; after ion implantation, the dielectric layer is filled in the groove to form an isolation structure. The method of forming according to claim 1, wherein the performing the first ion implantation in the first well region at the bottom of the groove comprises: forming a pattern on the surface formed by the substrate and the groove a first mask layer defining a region of the first ion implantation; performing a first ion implantation using the patterned first mask layer as a mask; and removing the patterned first mask after the first ion implantation Floor. The method of forming according to claim 1, wherein the performing the second ion implantation in the second well region at the bottom of the groove comprises: forming a pattern on the surface formed by the substrate and the groove a second mask layer defining a second ion implantation region; performing a second ion implantation using the patterned second mask layer as a mask; and removing the patterned second mask after the second ion implantation Floor. The method of forming according to claim 2, wherein the concentration of the first ion implantation is smaller than the ion implantation concentration at which the isolation structure is broken down. The method of forming according to claim 4, characterized in that the concentration of the first ion implantation is less than 1 × 10 ¹⁴ atoms/cm ² . The method of forming according to claim 3, characterized in that the concentration of the second ion implantation is smaller than the ion implantation concentration at which the isolation structure is broken down. The method of forming according to claim 6, wherein the concentration of the second ion implantation is less than 1 × 10 ¹⁴ atoms/cm ² . The method of forming according to claim 1, wherein the material of the sidewall is yttria or tantalum nitride. The method of forming the side wall according to claim 8, wherein the method for forming the sidewall spacer comprises: depositing a material layer of the sidewall wall on the surface of the groove; and etching the material layer of the sidewall wall. The method of forming according to claim 1, characterized in that the ion After the filling, the step of filling the dielectric layer to form the isolation structure in the groove further includes the step of removing the sidewall spacer. The method of forming of claim 10, wherein the method of removing the sidewall is wet etching. The forming method according to claim 1, wherein the step of forming a groove on the semiconductor substrate further comprises the steps of: forming an epoxy layer on the substrate, forming on the pad layer Barrier layer. The method of forming according to claim 12, wherein the material of the pad layer is ruthenium oxide, and the material of the barrier layer is tantalum nitride. The method of forming according to claim 1, characterized in that before the sidewall of the groove is formed into a sidewall, the method further comprises the step of forming a ruthenium oxide layer on the surface of the groove. The method of forming according to claim 14, wherein the method of forming the ruthenium oxide layer is thermal oxidation. The method of forming according to claim 1, wherein the material of the dielectric layer is cerium oxide. The method of forming of claim 1, wherein the forming a recess on the semiconductor substrate comprises: forming a patterned third mask layer on the semiconductor substrate, defining a recess The position of the semiconductor substrate is etched by using the patterned third mask layer as a mask. A semiconductor structure comprising: a semiconductor substrate having a recess, a semiconductor substrate on one side of the recess a first active region, the other side of the recessed semiconductor substrate is a second active region; a sidewall located at a sidewall of the recess; a first well region located in the first active region, located at the second a second well region in the source region, the first well region and the second well region forming a depletion region at a junction of the bottom of the recess; an ion concentration of the first well region at the bottom of the recess is greater than The concentration of other locations in the first well region, the concentration of ions in the second well region at the bottom of the trench is greater than the concentration of other locations in the second well region; and the dielectric layer filling the recess.