TWI517773B - Method for resetting the reflow position of a circuit board for a probe card - Google Patents

Method for resetting the reflow position of a circuit board for a probe card Download PDF

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TWI517773B
TWI517773B TW103117692A TW103117692A TWI517773B TW I517773 B TWI517773 B TW I517773B TW 103117692 A TW103117692 A TW 103117692A TW 103117692 A TW103117692 A TW 103117692A TW I517773 B TWI517773 B TW I517773B
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Taiwan
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reflow
circuit board
conductive
photoresist layer
holes
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TW103117692A
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TW201545624A (en
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Mpi Corp
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Description

用於探針卡的電路板之迴銲位置的重設方法 Method for resetting the reflow position of a circuit board for a probe card

本發明係與探針卡之電路板有關,特別是關於一種用於探針卡的電路板之迴銲位置的重設方法。 The present invention relates to a circuit board for a probe card, and more particularly to a method of resetting a reflow position of a circuit board for a probe card.

探針卡通常包含有一用以直接與測試機台之訊號傳輸端子電性連接之電路板,以及一設置於該電路板下表面之空間轉換器。該空間轉換器之上表面具有多數間距較大之導電接點,用以與該電路板電性連接;該空間轉換器之下表面則設置有多數間距較小之導電接點,用以抵接多數探針(例如垂直式探針),使得該等探針得以維持相對較小之針距,而可對晶片上間距相當小的導電接點進行點測。 The probe card usually includes a circuit board for directly connecting to the signal transmission terminal of the test machine, and a space converter disposed on the lower surface of the circuit board. The upper surface of the space transformer has a plurality of conductive contacts with a large spacing for electrically connecting to the circuit board; the lower surface of the space converter is provided with a plurality of conductive contacts having a small spacing for abutting Most probes (e.g., vertical probes) allow the probes to maintain a relatively small pitch, while spotting conductive contacts on the wafer with relatively small spacing.

探針卡之電路板與空間轉換器通常係藉由迴銲方式(reflow soldering)而相互電性連接,亦即,該電路板之下表面具有多數與該空間轉換器上表面之導電接點位置相對應之導電接點,且上下相對應之導電接點係藉由設於其之間的一銲球(solder ball;例如錫球)而相互電性連接。 The circuit board and the space converter of the probe card are usually electrically connected to each other by reflow soldering, that is, the lower surface of the circuit board has a plurality of conductive contact positions with the upper surface of the space transformer. Corresponding conductive contacts, and the corresponding upper and lower conductive contacts are electrically connected to each other by a solder ball (such as a solder ball) disposed therebetween.

若要將現成具特定目的用之電路板直接應用於探針卡,而非使用為了探針卡而製造的專用電路板,藉以降低探針卡之製造成本,該現成之電路板用以與空間轉換器連接之表面需先經由重新設計,以符合進行迴銲之需求。舉例而言,晶片製造廠商可能提供其現有之電路板給探針卡製造業者,該電路板原先可能是用在晶片封裝完成後的最終測試(final test;簡稱FT)的測試介面中,例如使用在包含有承接座(socket)的測試介面中,但該電路板原有之導電接點無法完全符合其即將連接之空間轉換器的導電接點,若該電路板用以與空間轉換器連接之表面能進行迴銲位置的重新設計,則可應用於在晶片封裝前進行裸晶測試(chip probing;簡稱CP)所使用的探針卡。 The off-the-shelf circuit board is used to reduce the cost of manufacturing the probe card by directly applying the ready-to-use board to the probe card instead of using a dedicated circuit board for the probe card. The surface to which the converter is connected needs to be redesigned to meet the requirements for reflow. For example, a wafer manufacturer may provide its existing circuit board to a probe card manufacturer, which may have been used in a final test (final test; FT for short) test interface, for example, In a test interface that includes a socket, but the original conductive contacts of the board do not fully conform to the conductive contacts of the space converter to which they are to be connected, if the board is used to connect to a space converter The redesign of the surface reflow position can be applied to the probe card used for chip probing (CP) before wafer packaging.

本發明之主要目的在於提供一種用於探針卡的電路板之迴銲位置的重設方法,可對現成之電路板進行迴銲位置的重新設計,使得該電路板能應用於探針卡並降低探針卡之製造成本。 The main object of the present invention is to provide a method for resetting the reflow position of a circuit board for a probe card, which can redesign the reflow position of the ready-made circuit board so that the circuit board can be applied to the probe card and Reduce the manufacturing cost of the probe card.

為達成上述目的,本發明所提供之用於探針卡的電路板之迴銲位置的重設方法係用以在一電路板之一安裝面上重新定義出複數迴銲位置,該電路板之安裝面具有複數導電接點,該電路板更具有一相對於該安裝面之測試面,該測試面係用以與一測試機電性連接;該重設方法包含有下列步驟:a.在該電路板之安裝面設置一覆蓋該等導電接點之層狀結構,該層狀結構具有朝向相反方向之一上表面及一下表面,該下表面貼接於該電路板之安裝面;以及b.在該層狀結構形成出符合該等迴銲位置且於該上表面呈開放狀之複數迴銲孔,該等迴銲孔係分別用以設置一銲球,且各該迴銲孔內有一能使其中之銲球與該電路板之導電接點電性連接的導電區塊。 In order to achieve the above object, the method for resetting the reflow position of a circuit board for a probe card provided by the present invention is for redefining a plurality of reflow positions on a mounting surface of a circuit board, the circuit board The mounting surface has a plurality of conductive contacts, and the circuit board further has a test surface opposite to the mounting surface, the test surface is for electrically connecting with a test; the resetting method comprises the following steps: a. in the circuit The mounting surface of the board is provided with a layered structure covering the conductive contacts, the layered structure having an upper surface and a lower surface facing in opposite directions, the lower surface being attached to the mounting surface of the circuit board; and b. The layered structure forms a plurality of reflow holes that conform to the reflow locations and are open on the upper surface, and the reflow holes are respectively configured to provide a solder ball, and each of the reflow holes has a The conductive block in which the solder ball is electrically connected to the conductive contact of the circuit board.

藉此,只要依據現成之電路板原有的導電接點與欲重新定義出的迴銲位置之間的差異而設計該層狀結構,即可利用前述之方法在該電路板上形成出符合迴銲需求之迴銲孔,如此一來,原先無法應用於探針卡之電路板在重新定義迴銲位置後即可應用於探針卡,藉以降低探針卡之製造成本。 Therefore, by designing the layered structure according to the difference between the original conductive contacts of the ready-made circuit board and the re-deformed reflow position to be redefined, the above method can be used to form a conformal structure on the circuit board. The reflow hole of the welding requirement, so that the circuit board that could not be applied to the probe card can be applied to the probe card after redefining the reflow position, thereby reducing the manufacturing cost of the probe card.

在本發明一實施例中,該步驟a可為於該電路板之安裝面塗佈一絕緣光阻層以成為該層狀結構,該步驟b可包含有下列步驟:b1.使光線隔著一與該層狀結構之上表面相對的光罩而對該層狀結構進行曝光,該光罩具有一符合該等迴銲孔之圖樣,且各個迴銲孔之位置至少與一個所述之導電接點的一部分重疊;以及b2.對該層狀結構進行顯影,以形成出該等迴銲孔,各該迴銲孔係貫穿該層狀結構之上表面與下表面,使對應之導電接點至少有一部分暴露出來,形成各該迴銲孔內之導電區塊。 In an embodiment of the invention, the step a may be to apply an insulating photoresist layer to the mounting surface of the circuit board to form the layered structure. The step b may include the following steps: b1. Exposing the layered structure to a mask opposite to the upper surface of the layered structure, the mask having a pattern conforming to the reflow holes, and each reflow hole being electrically connected to at least one of the conductive contacts a portion of the dots overlap; and b2. developing the layered structure to form the reflow holes, each of the reflow holes extending through the upper surface and the lower surface of the layered structure, so that the corresponding conductive contacts are at least A portion is exposed to form conductive segments in each of the reflow holes.

換言之,各該迴銲孔有一部分與該電路板之導電接點重疊,各該迴銲孔內之導電區塊位於該重疊的部分;藉此,設於各該迴銲孔內之銲球會接觸導電區塊而直接與該電路板之導電接點電性連接。 In other words, a portion of each of the reflow holes overlaps with the conductive contacts of the circuit board, and the conductive blocks in the reflow holes are located at the overlapping portions; thereby, the solder balls disposed in the reflow holes are The conductive block is contacted and electrically connected to the conductive contact of the circuit board.

在本發明另一實施例中,該步驟a可包含有下列步驟:a1.利用微影製程(photolithography)在該電路板之安裝面設置一第一絕緣光阻層,該第一絕緣光阻層具有朝向相反方向之一頂面及一底面,以及複數貫穿該頂面與該底面之第一穿孔,該底面即為該層狀結構之下表面,各該第一穿孔係位置對應於一該導電接點,使各該導電接點至少有一部分係暴露於對應之第一穿孔中;a2.在該等第一穿孔內分別形成一第一導電塊,使得各該第一導電塊與其所在之第一穿孔所對應的導電接點電性連接;以及a3.在該第一絕緣光阻層之頂面設置一第二絕緣光阻層,該第二絕緣光阻層具有朝向相反方向之一頂面及一底面,該第二絕緣光阻層之底面係貼接於該第一絕緣光阻層之頂面。 In another embodiment of the present invention, the step a may include the following steps: a1. Configuring a first insulating photoresist layer on the mounting surface of the circuit board by using photolithography, the first insulating photoresist layer a top surface and a bottom surface facing in opposite directions, and a plurality of first through holes penetrating the top surface and the bottom surface, the bottom surface being the lower surface of the layer structure, each of the first perforation system positions corresponding to the conductive a contact, wherein at least a portion of each of the conductive contacts is exposed to the corresponding first through hole; a2. forming a first conductive block in the first through holes, such that each of the first conductive blocks and the first conductive block a conductive connection electrically connected to a through hole; and a3. a second insulating photoresist layer disposed on a top surface of the first insulating photoresist layer, the second insulating photoresist layer having a top surface facing in an opposite direction And a bottom surface, the bottom surface of the second insulating photoresist layer is attached to the top surface of the first insulating photoresist layer.

若欲將該等迴銲孔設於該第二絕緣光阻層,使得銲球能藉由第一導電塊而間接地與電路板之導電接點電性連接,在該步驟a3中,該第二絕緣光阻層係覆蓋該等第一導電塊,且該第二絕緣光阻層之頂面即為該層狀結構之上表面;該步驟b包含有下列步驟:b1.使光線隔著一與該第二絕緣光阻層之頂面相對的光罩而對該第二絕緣光阻層進行曝光,該光罩具有一符合該等迴銲孔之圖樣,且各個迴銲孔之位置至少與一個所述之第一導電塊的一部分重疊;以及b2.對該第二絕緣光阻層進行顯影,以形成出該等迴銲孔,各該迴銲孔係貫穿該第二絕緣光阻層之頂面與底面,使對應之第一導電塊至少有一部分暴露出來,形成各該迴銲孔內之導電區塊。 If the reflow hole is to be disposed on the second insulating photoresist layer, the solder ball can be indirectly connected to the conductive contact of the circuit board by the first conductive block. In the step a3, the first The second insulating photoresist layer covers the first conductive blocks, and the top surface of the second insulating photoresist layer is the upper surface of the layered structure; the step b includes the following steps: b1. Exposing the second insulating photoresist layer to the reticle opposite to the top surface of the second insulating photoresist layer, the reticle having a pattern conforming to the reflow holes, and the positions of the reflow holes are at least a portion of the first conductive block overlaps; and b2. developing the second insulating photoresist layer to form the reflow holes, each of the reflow holes extending through the second insulating photoresist layer The top surface and the bottom surface expose at least a portion of the corresponding first conductive block to form conductive blocks in each of the reflow holes.

換言之,各該迴銲孔有一部分與第一導電塊重疊,各該迴銲孔內之導電區塊位於該重疊的部分;藉此,設於各該迴銲孔內之銲球會接觸導電區塊,並經由所接觸之導電區塊而間接與該電路板之導電接點電性連接。 In other words, a portion of each of the reflow holes overlaps with the first conductive block, and the conductive blocks in each of the reflow holes are located at the overlapping portion; thereby, the solder balls disposed in each of the reflow holes contact the conductive region And electrically connected to the conductive contacts of the circuit board through the conductive blocks that are in contact.

較佳地,各該第一導電塊具有一不與該電路板之導電接點位置對應之延伸段,各該迴銲孔內之導電區塊係完全位於第一導電塊之延伸段。藉此,該迴銲孔可完全與該電路板之導電接點錯開。 Preferably, each of the first conductive blocks has an extension that does not correspond to the position of the conductive contacts of the circuit board, and the conductive blocks in each of the reflow holes are completely located in the extension of the first conductive block. Thereby, the reflow hole can be completely staggered from the conductive contacts of the circuit board.

或者,該步驟a3亦可係利用微影製程形成該第二絕緣光阻層,該第二絕緣光阻層具有複數貫穿其頂面與底面之第二穿孔,各該第二 穿孔係位置對應於一該第一導電塊,使各該第一導電塊全部或至少有一部分暴露於對應之第二穿孔中;該步驟a更包含有下列步驟:a4.在該等第二穿孔內分別形成一第二導電塊,使得各該第二導電塊與其所在之第二穿孔所對應之第一導電塊電性連接;以及a5.在該第二絕緣光阻層之頂面設置一第三絕緣光阻層,該第三絕緣光阻層具有朝向相反方向之一頂面及一底面,該第三絕緣光阻層之底面係貼接於該第二絕緣光阻層之頂面。 Alternatively, the step a3 may further form the second insulating photoresist layer by using a lithography process, the second insulating photoresist layer having a plurality of second through holes penetrating the top surface and the bottom surface thereof, each of the second The perforation system position corresponds to a first conductive block, so that all or at least a portion of each of the first conductive blocks is exposed to the corresponding second perforation; the step a further comprises the following steps: a4. Forming a second conductive block respectively, such that each of the second conductive blocks is electrically connected to the first conductive block corresponding to the second through hole; and a5. setting a top surface of the second insulating photoresist layer The third insulating photoresist layer has a top surface and a bottom surface facing in opposite directions, and a bottom surface of the third insulating photoresist layer is attached to a top surface of the second insulating photoresist layer.

藉此,該等迴銲孔可設於該第三絕緣光阻層,使得銲球能經由第一導電塊及第二導電塊而間接地與電路板之導電接點電性連接,在此狀況下,在該步驟a5中,該第三絕緣光阻層係覆蓋該等第二導電塊,且該第三絕緣光阻層之頂面即為該層狀結構之上表面;該步驟b包含有下列步驟:b1.使光線隔著一與該第三絕緣光阻層之頂面相對的光罩而對該第三絕緣光阻層進行曝光,該光罩具有一符合該等迴銲孔之圖樣,且各個迴銲孔之位置至少與一個所述之第二導電塊的一部分重疊;以及b2.對該第三絕緣光阻層進行顯影,以形成出該等迴銲孔,各該迴銲孔係貫穿該第三絕緣光阻層之頂面與底面,使對應之第二導電塊至少有一部分暴露出來,形成各該迴銲孔內之導電區塊。 Thereby, the reflow holes can be disposed on the third insulating photoresist layer, so that the solder balls can be indirectly electrically connected to the conductive contacts of the circuit board via the first conductive block and the second conductive block. Next, in the step a5, the third insulating photoresist layer covers the second conductive blocks, and the top surface of the third insulating photoresist layer is the upper surface of the layered structure; the step b includes The following steps: b1. exposing the light to the third insulating photoresist layer via a photomask opposite to the top surface of the third insulating photoresist layer, the mask having a pattern conforming to the reflow holes And each of the reflow holes is overlapped with at least a portion of the second conductive block; and b2. developing the third insulating photoresist layer to form the reflow holes, each of the reflow holes The top surface and the bottom surface of the third insulating photoresist layer are penetrated, and at least a portion of the corresponding second conductive block is exposed to form a conductive block in each of the reflow holes.

較佳地,各該第一導電塊係完全位於其所在之第一穿孔所對應的導電接點上。 Preferably, each of the first conductive blocks is completely located on a conductive contact corresponding to the first through hole where the first conductive block is located.

較佳地,各該第二導電塊具有一不與該電路板之導電接點位置對應之延伸段,各該迴銲孔內之導電區塊係完全位於第二導電塊之延伸段。 Preferably, each of the second conductive blocks has an extension that does not correspond to the position of the conductive contacts of the circuit board, and the conductive blocks in each of the reflow holes are completely located in the extension of the second conductive block.

有關本發明所提供之用於探針卡的電路板之迴銲位置的重設方法的詳細構造、特點、組裝或使用方式,將於後續的實施方式詳細說明中予以描述。然而,在本發明領域中具有通常知識者應能瞭解,該等詳細說明以及實施本發明所列舉的特定實施例,僅係用於說明本發明,並非用以限制本發明之專利申請範圍。 The detailed construction, features, assembly or use of the method of resetting the reflow position of the circuit board for the probe card provided by the present invention will be described in the detailed description of the subsequent embodiments. However, it should be understood by those of ordinary skill in the art that the present invention is not limited by the scope of the invention.

10‧‧‧電路板 10‧‧‧ boards

12‧‧‧安裝面 12‧‧‧Installation surface

122‧‧‧導電接點 122‧‧‧Electrical contacts

124‧‧‧絕緣部位 124‧‧‧Insulation

14‧‧‧測試面 14‧‧‧Test surface

21、22、23‧‧‧電路板 21, 22, 23‧‧‧ circuit boards

30、30'、30"‧‧‧層狀結構 30, 30', 30" ‧ ‧ layered structure

31‧‧‧上表面 31‧‧‧ upper surface

32‧‧‧下表面 32‧‧‧ lower surface

33‧‧‧絕緣光阻層 33‧‧‧Insulating photoresist layer

34‧‧‧第一絕緣光阻層 34‧‧‧First insulating photoresist layer

342‧‧‧頂面 342‧‧‧ top surface

344‧‧‧底面 344‧‧‧ bottom

346‧‧‧第一穿孔 346‧‧‧First perforation

35‧‧‧第一導電塊 35‧‧‧First conductive block

352‧‧‧連接段 352‧‧‧Connection section

354‧‧‧延伸段 354‧‧‧Extension

36‧‧‧第二絕緣光阻層 36‧‧‧Second insulating photoresist layer

362‧‧‧頂面 362‧‧‧ top surface

364‧‧‧底面 364‧‧‧ bottom

366‧‧‧第二穿孔 366‧‧‧Second perforation

37‧‧‧第二導電塊 37‧‧‧Second conductive block

372‧‧‧對應段 372‧‧‧ Corresponding paragraph

374‧‧‧延伸段 374‧‧‧Extension

38‧‧‧第三絕緣光阻層 38‧‧‧ Third insulating photoresist layer

382‧‧‧頂面 382‧‧‧ top surface

384‧‧‧底面 384‧‧‧ bottom

40‧‧‧迴銲孔 40‧‧‧Reflow holes

42‧‧‧導電區塊 42‧‧‧ conductive block

50‧‧‧銲球 50‧‧‧ solder balls

60‧‧‧光罩 60‧‧‧Photomask

62‧‧‧圖樣 62‧‧‧ pattern

P‧‧‧迴銲位置 P‧‧‧Reflow position

第1圖至第4圖為剖視示意圖,係顯示本發明一第一較佳實施例所提供之用於探針卡的電路板之迴銲位置的重設方法之過程;第5圖為第1圖所示之電路板的頂視示意圖;第6圖為第4圖所示之電路板的頂視示意圖;第7圖至第11圖為剖視示意圖,係顯示本發明一第二較佳實施例所提供之用於探針卡的電路板之迴銲位置的重設方法之過程;以及第12圖至第17圖為剖視示意圖,係顯示本發明一第三較佳實施例所提供之用於探針卡的電路板之迴銲位置的重設方法之過程。 1 to 4 are schematic cross-sectional views showing a process of resetting a reflow position of a circuit board for a probe card according to a first preferred embodiment of the present invention; 1 is a top view of the circuit board shown in FIG. 6; FIG. 6 is a top plan view of the circuit board shown in FIG. 4; and FIG. 7 to FIG. 11 are cross-sectional views showing a second preferred embodiment of the present invention. The process of the method for resetting the reflow position of the circuit board for the probe card provided by the embodiment; and the 12th to 17th views are schematic cross-sectional views showing the third preferred embodiment of the present invention. The process of resetting the reflow position of the circuit board of the probe card.

申請人首先在此說明,在以下將要介紹之實施例以及圖式中,相同之參考號碼,表示相同或類似之元件或其結構特徵。 The Applicant first describes the same or similar elements or structural features thereof in the embodiments and the drawings which will be described below.

請先參閱第1圖至第4圖,本發明一第一較佳實施例所提供之用於探針卡的電路板之迴銲位置的重設方法,係用以將一如第1圖所示之現成的電路板10轉變成一如第4圖所示之電路板21,以於該電路板10之一安裝面12上重新定義出複數迴銲位置P,使得該電路板21能符合應用於探針卡所需的特定之迴銲作業需求。該電路板10更具有一相對於該安裝面12之測試面14,在利用該電路板21所製成之探針卡測試待測物時,該測試面14係用以與一測試機(圖中未示)電性連接。 Please refer to FIG. 1 to FIG. 4 , a method for resetting the reflow position of a circuit board for a probe card according to a first preferred embodiment of the present invention, which is used as shown in FIG. 1 . The ready-made circuit board 10 is transformed into a circuit board 21 as shown in FIG. 4 to redefine the plurality of reflow positions P on one of the mounting faces 12 of the circuit board 10, so that the circuit board 21 can be applied in accordance with the application. The specific reflow job requirements required for the probe card. The circuit board 10 further has a test surface 14 opposite to the mounting surface 12, and the test surface 14 is used with a test machine when testing the object to be tested by using the probe card made of the circuit board 21. Not shown in the electrical connection.

舉例而言,該電路板10可能原先為晶片製造廠商使用於最終測試(FT)之電路板,其頂視圖如第5圖所示,並且該電路板10係提供給探針卡製造業者以應用在使用於裸晶測試(CP)之探針卡,該電路板10之安裝面12需經由迴銲方式而與一空間轉換器(圖中未示)對接以組成探針卡。該電路板10之安裝面12原先就有複數導電接點122,惟該等導電接點122並非為了與該空間轉換器對接而設置,因此該等導電接點122之位置分佈,不符合探針卡製造時與空間轉換器進行迴銲作業之銲接位置。本發明所提供之用於探針卡的電路板之迴銲位置的重設方法,係用以將符合需求之迴銲位置P定義在該電路板21上,例如使該電路板21之頂視圖呈現第6圖所示之態樣。換言之,該電路板10在定義出該等迴銲位置P之前可以是 (但不限於)被應用於晶片封裝完成後的最終測試的測試介面中的電路板,前述測試介面可為具有承接座(socket)且用以電性連接測試機與待測物(封裝晶片)之測試介面,而該電路板10在定義出該等迴銲位置P之後,亦即轉變成該電路板21,則可被(但不限於)應用於在晶片封裝前進行裸晶測試所使用的探針卡中。 For example, the circuit board 10 may have been originally used by the wafer manufacturer for the final test (FT) circuit board, the top view of which is shown in FIG. 5, and the circuit board 10 is provided to the probe card manufacturer for application. In the probe card used for the bare crystal test (CP), the mounting surface 12 of the circuit board 10 needs to be reflowed to interface with a space converter (not shown) to form a probe card. The mounting surface 12 of the circuit board 10 originally has a plurality of conductive contacts 122. However, the conductive contacts 122 are not disposed to interface with the space converter. Therefore, the positional distribution of the conductive contacts 122 does not conform to the probe. The welding position of the reflow operation with the space converter during card manufacture. The method for resetting the reflow position of the circuit board for a probe card provided by the present invention is for defining a reflow position P according to requirements on the circuit board 21, for example, a top view of the circuit board 21. The aspect shown in Figure 6 is presented. In other words, the circuit board 10 may be before the reflow position P is defined. (but not limited to) a circuit board used in a test interface for final testing after completion of chip packaging, the test interface may have a socket and is used to electrically connect the tester and the object to be tested (packaged wafer) The test interface, and after the circuit board 10 defines the reflow locations P, that is, into the circuit board 21, it can be used, but not limited to, for the bare crystal test before the wafer package. In the probe card.

在此需先說明的是,第1圖至第4圖中僅顯示二該導電接點122及三該迴銲位置P,以便清楚扼要地表示出本實施例所提供之用於探針卡的電路板之迴銲位置的重設方法。事實上,該電路板10之安裝面12通常具有相當多導電接點122,且最後也會定義出相當多迴銲位置P,例如第5圖及第6圖所示者,但該等導電接點122及迴銲位置P的數量、形狀及位置並無限制。 It should be noted that only the conductive contacts 122 and the three reflow positions P are shown in FIGS. 1 to 4 in order to clearly show the probe card provided in the embodiment. The method of resetting the reflow position of the board. In fact, the mounting surface 12 of the circuit board 10 generally has a relatively large number of conductive contacts 122, and finally a considerable number of reflow locations P are defined, such as those shown in Figures 5 and 6, but the conductive connections The number, shape and position of the point 122 and the reflow position P are not limited.

如第4圖所示,本實施例所提供之用於探針卡的電路板之迴銲位置的重設方法,主要係用於定義出與該等導電接點122不相符合但部分重疊之迴銲位置P,其包含有下列步驟: As shown in FIG. 4, the method for resetting the reflow position of the circuit board for the probe card provided in this embodiment is mainly used to define that the conductive contacts 122 do not coincide but partially overlap. Reflow position P, which includes the following steps:

a.如第2圖所示,在該電路板10之安裝面12設置一覆蓋該等導電接點122之層狀結構30,該層狀結構30具有朝向相反方向之一上表面31及一下表面32,該下表面32貼接於該電路板10之安裝面12。 As shown in FIG. 2, a layered structure 30 covering the conductive contacts 122 is disposed on the mounting surface 12 of the circuit board 10, and the layered structure 30 has an upper surface 31 and a lower surface facing in opposite directions. 32. The lower surface 32 is attached to the mounting surface 12 of the circuit board 10.

在本實施例中,該步驟a係於該電路板10之安裝面12塗佈一絕緣光阻層33以成為該層狀結構30,亦即,該層狀結構30僅包含有該絕緣光阻層33,該層狀結構30之上、下表面31、32即為該絕緣光阻層33之頂、底面。 In this embodiment, the step a is applied to the mounting surface 12 of the circuit board 10 to apply an insulating photoresist layer 33 to form the layer structure 30. That is, the layer structure 30 only includes the insulating photoresist. The layer 33, the upper surface and the lower surface 31, 32 of the layered structure 30 are the top and bottom surfaces of the insulating photoresist layer 33.

b.如第3圖及第4圖所示,在該層狀結構30形成出符合該等迴銲位置P且於該上表面31呈開放狀之複數迴銲孔40,該等迴銲孔40係分別用以設置一銲球50,且各該迴銲孔40內有一能使其中之銲球50與該電路板10之導電接點122電性連接的導電區塊42。 b. As shown in FIGS. 3 and 4, a plurality of reflow holes 40 are formed in the layered structure 30 in conformity with the reflow positions P and open on the upper surface 31, and the reflow holes 40 are formed. The solder balls 50 are respectively disposed, and each of the reflow holes 40 has a conductive block 42 for electrically connecting the solder balls 50 to the conductive contacts 122 of the circuit board 10.

在本實施例中,該步驟b包含有下列步驟: In this embodiment, the step b includes the following steps:

b1.如第3圖所示,使光線隔著一與該層狀結構30之上表面31相對的光罩60而對該層狀結構30進行曝光,該光罩60具有一符合該等迴銲孔40之圖樣62(pattern),且各個迴銲孔40之位置至少與一個導電接點122的一部分相互重疊。 B1. As shown in FIG. 3, the layered structure 30 is exposed by illuminating the light through a mask 60 opposite the upper surface 31 of the layered structure 30. The mask 60 has a reflow conformance The pattern of the holes 40 is pattern 62, and the positions of the respective reflow holes 40 overlap each other at least with a portion of one of the conductive contacts 122.

b2.對該層狀結構30進行顯影,以形成出該等迴銲孔40,各該迴銲孔40係貫穿該層狀結構30之上表面31與下表面32,並使各個導電接點122至少有一部分可以暴露出來,而在迴銲孔40內形成所述之導電區塊42,亦即,各該迴銲孔40內之導電區塊42為一該導電接點122的一部分。 B2. Developing the layer structure 30 to form the reflow holes 40, each of the reflow holes 40 extending through the upper surface 31 and the lower surface 32 of the layer structure 30, and the respective conductive contacts 122 At least a portion of the conductive block 42 may be formed in the reflow hole 40, that is, the conductive block 42 in each of the reflow holes 40 is a portion of the conductive contact 122.

換言之,前述之曝光及顯影程序係用以去除該絕緣光阻層33在該等迴銲位置P之區塊,以於該等迴銲位置P分別形成出一該迴銲孔40,各該迴銲孔40有一部分與該電路板10之導電接點122重疊,而本發明所謂的「各該迴銲孔40內之導電區塊42」,在此實施例中,即是該重疊的部分(導電接點122暴露於迴銲孔40中之部分),藉此,可使得設置於各該迴銲孔40內之銲球50直接接觸該電路板10之導電接點122而相互電性連接。 In other words, the exposure and development process described above is used to remove the blocks of the insulating photoresist layer 33 at the reflow locations P to form a reflow hole 40 at the reflow locations P, respectively. A portion of the soldering hole 40 overlaps with the conductive contact 122 of the circuit board 10, and the so-called "conductive block 42 in each of the reflow holes 40" in the present invention is the overlapping portion in this embodiment ( The conductive contacts 122 are exposed to portions of the reflow holes 40, whereby the solder balls 50 disposed in the reflow holes 40 are directly in contact with the conductive contacts 122 of the circuit board 10 to be electrically connected to each other.

請參閱第7圖至第11圖,本發明一第二較佳實施例所提供之用於探針卡的電路板之迴銲位置的重設方法,係用以將如第1圖所示之電路板10轉變成如第11圖所示之電路板22,以於該電路板22定義出複數迴銲位置P,且該等迴銲位置P不但與該等導電接點122不相符合且位置亦完全不相對應。 Referring to FIG. 7 to FIG. 11 , a method for resetting a reflow position of a circuit board for a probe card according to a second preferred embodiment of the present invention is to be used as shown in FIG. 1 . The circuit board 10 is converted into a circuit board 22 as shown in FIG. 11 to define a plurality of reflow positions P, and the reflow positions P are not in conformity with the conductive contacts 122 and are located. It does not correspond at all.

換言之,本實施例所提供之用於探針卡的電路板之迴銲位置的重設方法,主要係用以形成出完全與該等導電接點122錯開之迴銲孔40,其同樣包含有如前述之步驟a及步驟b,亦即,先形成一層狀結構30'(如第9圖所示),再形成出該等迴銲孔40(如第11圖所示),惟本實施例之步驟a、b之內容係與前述之第一較佳實施例略有差異,詳述如下。 In other words, the method for resetting the reflow position of the circuit board for the probe card provided by the embodiment is mainly for forming a reflow hole 40 which is completely offset from the conductive contacts 122, and the same includes The foregoing steps a and b, that is, forming a layered structure 30' (as shown in FIG. 9), and forming the reflow holes 40 (as shown in FIG. 11), but this embodiment The contents of steps a and b are slightly different from the first preferred embodiment described above, and are described in detail below.

在本實施例中,該步驟a包含有下列步驟: In this embodiment, the step a includes the following steps:

a1.如第7圖所示,利用微影製程(photolithography)在該電路板10之安裝面12設置一第一絕緣光阻層34,該第一絕緣光阻層34具有朝向相反方向之一頂面342及一底面344,以及複數貫穿該頂面342與該底面344之第一穿孔346,該底面344即為該層狀結構30'之下表面32,各該第一穿孔346係位置對應於一該導電接點122,使得導電接點122至少有一部分係暴露於第一穿孔346中。換言之,此步驟包含有塗佈光阻、曝光、顯影等等程序,以形成出該第一絕緣光阻層34。 A1. As shown in FIG. 7, a first insulating photoresist layer 34 is disposed on the mounting surface 12 of the circuit board 10 by photolithography, and the first insulating photoresist layer 34 has a top in the opposite direction. a surface 342 and a bottom surface 344, and a plurality of first through holes 346 extending through the top surface 342 and the bottom surface 344, the bottom surface 344 is the lower surface 32 of the layered structure 30', and the positions of the first through holes 346 are corresponding to The conductive contact 122 is such that at least a portion of the conductive contact 122 is exposed to the first via 346. In other words, this step includes a coating photoresist, exposure, development, and the like to form the first insulating photoresist layer 34.

a2.如第8圖所示,在該等第一穿孔346內分別形成一第一導電塊35,使得各該第一導電塊35與其所在之第一穿孔346所對應的導電接點122電性連接,亦即第一導電塊35至少有一部分係與導電接點122重疊並直接連接。該等第一導電塊35可藉由電鍍、蒸鍍或濺鍍之方式將金屬材料沉積於該等第一穿孔346內而形成。 A2. As shown in FIG. 8, a first conductive block 35 is formed in the first through holes 346, so that the first conductive blocks 35 are electrically connected to the conductive contacts 122 corresponding to the first through holes 346. The connection, that is, at least a portion of the first conductive block 35 overlaps and is directly connected to the conductive contacts 122. The first conductive blocks 35 can be formed by depositing a metal material in the first through holes 346 by electroplating, evaporation or sputtering.

a3.如第9圖所示,在該第一絕緣光阻層34之頂面342設置一第二絕緣光阻層36,該第二絕緣光阻層36具有朝向相反方向之一頂面362及一底面364,該第二絕緣光阻層36之底面364係貼接於該第一絕緣光阻層34之頂面342。 A3. As shown in FIG. 9, a second insulating photoresist layer 36 is disposed on the top surface 342 of the first insulating photoresist layer 34. The second insulating photoresist layer 36 has a top surface 362 facing in the opposite direction and A bottom surface 364 of the second insulating photoresist layer 36 is attached to the top surface 342 of the first insulating photoresist layer 34.

在本實施例中,此步驟僅包含有塗佈光阻之程序,以形成覆蓋該等第一導電塊35之該第二絕緣光阻層36,且該第二絕緣光阻層36之頂面362即為該層狀結構30'之上表面31。 In this embodiment, the step includes only applying a photoresist to form the second insulating photoresist layer 36 covering the first conductive blocks 35, and the top surface of the second insulating photoresist layer 36 362 is the upper surface 31 of the layered structure 30'.

藉由前述之步驟a1~a3,本實施例之層狀結構30'包含有第一、二絕緣光阻層34、36,以及該等第一導電塊35。本實施例之步驟b包含有下列步驟: The layered structure 30' of the present embodiment includes the first and second insulating photoresist layers 34, 36, and the first conductive blocks 35 by the foregoing steps a1 to a3. Step b of this embodiment includes the following steps:

b1.如第10圖所示,使光線隔著一與該第二絕緣光阻層36之頂面362相對的光罩60而對該第二絕緣光阻層36進行曝光,該光罩60具有一符合該等迴銲孔40之圖樣62,且各個迴銲孔40之位置至少與一個導電塊35的一部分相互重疊。 B1. As shown in FIG. 10, the second insulating photoresist layer 36 is exposed by illuminating the light through a mask 60 opposite to the top surface 362 of the second insulating photoresist layer 36. The mask 60 has A pattern 62 conforming to the reflow holes 40 is formed, and the positions of the respective reflow holes 40 overlap at least a portion of one of the conductive blocks 35.

b2.如第11圖所示,對該第二絕緣光阻層36進行顯影,以形成出該等迴銲孔40,各該迴銲孔40係貫穿該第二絕緣光阻層36之頂面362與底面364,並使各個導電塊35至少有一部分可以暴露出來,而在迴銲孔40內形成所述之導電區塊42。換言之,在此實施例中,本發明所謂的「各該迴銲孔40內之導電區塊42」,係為一該第一導電塊35的一部分(導電塊35暴露於迴銲孔40中之部分),而且,透過該等導電塊35,可使設置於各該迴銲孔40內之銲球50間接地電性連接於該電路板10之導電接點122。 B2. As shown in FIG. 11, the second insulating photoresist layer 36 is developed to form the reflow holes 40, and each of the reflow holes 40 extends through the top surface of the second insulating photoresist layer 36. 362 and the bottom surface 364, and at least a portion of each of the conductive blocks 35 can be exposed, and the conductive block 42 is formed in the reflow hole 40. In other words, in this embodiment, the so-called "conductive block 42 in each reflow hole 40" is a part of the first conductive block 35 (the conductive block 35 is exposed in the reflow hole 40). In addition, the solder balls 50 disposed in the reflow holes 40 are electrically connected to the conductive contacts 122 of the circuit board 10 indirectly through the conductive blocks 35.

如第11圖所示,由於本實施例所欲形成之迴銲孔40係完全與該電路板10之導電接點122錯開,各該第一導電塊35係自一該導電接點122上延伸至該安裝面12之絕緣部位124,亦即,各該第一導電塊35具有一連接於導電接點122之連接段352,以及一不與導電接點122位置對應之 延伸段354,使得各該迴銲孔40能設於延伸段354而不與導電接點122位置對應,各該迴銲孔40內之導電區塊42係完全位於第一導電塊35之延伸段354。 As shown in FIG. 11, since the reflow hole 40 to be formed in this embodiment is completely offset from the conductive contact 122 of the circuit board 10, each of the first conductive blocks 35 extends from a conductive contact 122. The insulating portion 124 of the mounting surface 12, that is, each of the first conductive blocks 35 has a connecting portion 352 connected to the conductive contact 122, and a position corresponding to the conductive contact 122 The extension 354 is configured such that each of the reflow holes 40 can be disposed on the extension 354 and does not correspond to the position of the conductive contact 122. The conductive block 42 in each reflow hole 40 is completely located in the extension of the first conductive block 35. 354.

在前述之第二較佳實施例中,由於各該第一導電塊35係直接與該電路板10之導電接點122連接,且通常需要較大的面積,若該安裝面12之導電接點122較為密集,則該等第一導電塊35會較難以配置,此時可採用本發明一第三較佳實施例所提供之方法,詳述如下。 In the foregoing second preferred embodiment, since each of the first conductive blocks 35 is directly connected to the conductive contacts 122 of the circuit board 10, and generally requires a large area, if the conductive contacts of the mounting surface 12 are If the 122 is relatively dense, the first conductive blocks 35 may be more difficult to configure. In this case, the method provided by a third preferred embodiment of the present invention may be used as follows.

請參閱第12圖至第17圖,本發明之第三較佳實施例所提供之用於探針卡的電路板之迴銲位置的重設方法同樣包含有如第一較佳實施例中所述之步驟a及步驟b,且本實施例之步驟a同樣包含有如第二較佳實施例中所述之步驟a1~a3,惟其步驟a1、a2所形成出之第一導電塊35面積較小(如第12圖所示),各該第一導電塊35係完全位於其所在之第一穿孔346所對應的導電接點122上。此外,本實施例之步驟a3係利用微影製程形成該第二絕緣光阻層36(如第13圖所示),亦即,此步驟a3不只塗佈光阻,更有曝光及顯影之程序,使得該第二絕緣光阻層36具有複數貫穿其頂面362與底面364之第二穿孔366,各該第二穿孔366係位置對應於一該第一導電塊35,使第一導電塊35完全(或至少有一部分)暴露於該第二穿孔366中。再者,本實施例之步驟a更包含有下列步驟: Referring to FIG. 12 to FIG. 17, the resetting method for the reflow position of the circuit board for the probe card provided by the third preferred embodiment of the present invention also includes the method as described in the first preferred embodiment. Step a and step b, and step a of the embodiment also includes steps a1 to a3 as described in the second preferred embodiment, except that the first conductive block 35 formed by steps a1 and a2 has a small area ( As shown in FIG. 12, each of the first conductive blocks 35 is completely located on the conductive contacts 122 corresponding to the first through holes 346. In addition, step a3 of the embodiment forms the second insulating photoresist layer 36 by using a lithography process (as shown in FIG. 13), that is, the step a3 is not only coated with a photoresist, but also has a procedure of exposure and development. The second insulating photoresist layer 36 has a plurality of second through holes 366 extending through the top surface 362 and the bottom surface 364, and each of the second through holes 366 is corresponding to a first conductive block 35, so that the first conductive block 35 Complete (or at least a portion) of the second perforations 366 are exposed. Furthermore, step a of the embodiment further comprises the following steps:

a4.如第14圖所示,在該等第二穿孔366內分別形成一第二導電塊37,使得各該第二導電塊37與其所在之第二穿孔366所對應之第一導電塊35電性連接。該等第二導電塊37可藉由電鍍、蒸鍍或濺鍍之方式將金屬材料沉積於該等第二穿孔366內而形成。 As shown in FIG. 14, a second conductive block 37 is formed in each of the second through holes 366, so that each of the second conductive blocks 37 is electrically connected to the first conductive block 35 corresponding to the second through hole 366. Sexual connection. The second conductive blocks 37 can be formed by depositing a metal material in the second through holes 366 by electroplating, evaporation or sputtering.

a5.如第15圖所示,在該第二絕緣光阻層36之頂面362設置一第三絕緣光阻層38,該第三絕緣光阻層38具有朝向相反方向之一頂面382及一底面384,該第三絕緣光阻層38之底面384係貼接於該第二絕緣光阻層36之頂面362。此步驟僅包含有塗佈光阻之程序,以形成覆蓋該等第二導電塊37之該第三絕緣光阻層38,且該第三絕緣光阻層38之頂面382即為本實施例之層狀結構30"之上表面31。 A5. As shown in FIG. 15, a third insulating photoresist layer 38 is disposed on the top surface 362 of the second insulating photoresist layer 36. The third insulating photoresist layer 38 has a top surface 382 facing in an opposite direction. A bottom surface 384 of the third insulating photoresist layer 38 is attached to the top surface 362 of the second insulating photoresist layer 36. This step includes only the process of coating the photoresist to form the third insulating photoresist layer 38 covering the second conductive blocks 37, and the top surface 382 of the third insulating photoresist layer 38 is the embodiment. The layered structure 30" upper surface 31.

藉由前述之步驟a1~a5,本實施例之層狀結構30"包含有第一、二、三絕緣光阻層34、36、38,以及該等第一、二導電塊35、37。本 實施例之步驟b包含有下列步驟: The layered structure 30" of the present embodiment includes the first, second and third insulating photoresist layers 34, 36, 38, and the first and second conductive blocks 35, 37 by the aforementioned steps a1 to a5. Step b of the embodiment includes the following steps:

b1.如第16圖所示,使光線隔著一與該第三絕緣光阻層38之頂面382相對的光罩60而對該第三絕緣光阻層38進行曝光,該光罩60具有一符合該等迴銲孔40之圖樣62,且各個迴銲孔40之位置至少與一個第二導電塊37的一部分相互重疊。 B1. As shown in FIG. 16, the third insulating photoresist layer 38 is exposed by illuminating the light through a mask 60 opposite to the top surface 382 of the third insulating photoresist layer 38. The mask 60 has A pattern 62 conforming to the reflow holes 40 is formed, and the positions of the respective reflow holes 40 overlap at least a portion of one of the second conductive blocks 37.

b2.如第17圖所示,對該第三絕緣光阻層38進行顯影,以形成出該等迴銲孔40,各該迴銲孔40係貫穿該第三絕緣光阻層38之頂面382與底面384,並使各個第二導電塊37至少有一部分可以暴露出來,而在迴銲孔40內形成所述之導電區塊42。換言之,在此實施例中,本發明所謂的「各該迴銲孔40內之導電區塊42」,係為一該第二導電塊37的一部分(第二導電塊37暴露於迴銲孔40中之部分),而且,透過該等二導電塊37與第一導電塊35,可使設置於各該迴銲孔40內之銲球50間接地電性連接於該電路板10之導電接點122。 B2. As shown in FIG. 17, the third insulating photoresist layer 38 is developed to form the reflow holes 40, and each of the reflow holes 40 extends through the top surface of the third insulating photoresist layer 38. 382 and the bottom surface 384, and at least a portion of each of the second conductive blocks 37 may be exposed, and the conductive block 42 is formed in the reflow hole 40. In other words, in this embodiment, the so-called "conductive block 42 in each reflow hole 40" is a part of the second conductive block 37 (the second conductive block 37 is exposed to the reflow hole 40). And the solder balls 50 disposed in the reflow holes 40 are electrically connected to the conductive contacts of the circuit board 10 through the second conductive blocks 37 and the first conductive blocks 35. 122.

如第17圖所示,由於本實施例所欲形成之迴銲孔40係完全與該電路板10之導電接點122錯開,各該第二導電塊37具有一隔著第一絕緣光阻層34及第一導電塊35而位置對應於該電路板10之導電接點122的對應段372,以及一不與導電接點122位置對應(亦即隔著該第一絕緣光阻層34而對應該安裝面12之絕緣部位124)之延伸段374,各該迴銲孔內40之導電區塊42係完全位於第二導電塊37之延伸段374。 As shown in FIG. 17, since the reflow hole 40 to be formed in this embodiment is completely offset from the conductive contact 122 of the circuit board 10, each of the second conductive blocks 37 has a first insulating photoresist layer. 34 and the first conductive block 35 are located corresponding to the corresponding segments 372 of the conductive contacts 122 of the circuit board 10, and one does not correspond to the position of the conductive contacts 122 (ie, across the first insulating photoresist layer 34) An extension 374 of the insulating portion 124) of the face 12 should be mounted, and the conductive segments 42 in each of the reflow holes 40 are completely located in the extension 374 of the second conductive block 37.

由前述內容可得知,本發明所提供之方法可在現成之電路板上重新定義出迴銲位置,亦即形成出符合應用於探針卡的迴銲需求之迴銲孔,只要依據現成之電路板原有的導電接點與欲重新定義出的迴銲位置之間的差異而設計該層狀結構,該層狀結構可根據狀況採用前述任一實施例所提供之態樣,亦可將不同態樣之層狀結構應用在同一電路板上。 It can be seen from the foregoing that the method provided by the present invention can redefine the reflow position on the off-the-shelf circuit board, that is, form a reflow hole conforming to the reflow requirement of the probe card, as long as it is ready-made. The layered structure is designed according to the difference between the original conductive contact of the circuit board and the re-deformed reflow position to be redefined, and the layered structure may adopt the aspect provided by any of the foregoing embodiments according to the situation, or may Layered structures of different patterns are applied on the same circuit board.

最後,必須再次說明,本發明於前揭實施例中所揭露的構成元件,僅為舉例說明,並非用來限制本案之範圍,其他等效元件的替代或變化,亦應為本案之申請專利範圍所涵蓋。 Finally, it is to be noted that the constituent elements disclosed in the foregoing embodiments are merely illustrative and are not intended to limit the scope of the present invention, and alternative or variations of other equivalent elements should also be the scope of the patent application of the present application. Covered.

10‧‧‧電路板 10‧‧‧ boards

12‧‧‧安裝面 12‧‧‧Installation surface

122‧‧‧導電接點 122‧‧‧Electrical contacts

14‧‧‧測試面 14‧‧‧Test surface

21‧‧‧電路板 21‧‧‧ boards

30‧‧‧層狀結構 30‧‧‧Layered structure

31‧‧‧上表面 31‧‧‧ upper surface

32‧‧‧下表面 32‧‧‧ lower surface

40‧‧‧迴銲孔 40‧‧‧Reflow holes

42‧‧‧導電區塊 42‧‧‧ conductive block

50‧‧‧銲球 50‧‧‧ solder balls

P‧‧‧迴銲位置 P‧‧‧Reflow position

Claims (12)

一種用於探針卡的電路板之迴銲位置的重設方法,係用以在一電路板之一安裝面上重新定義出複數迴銲位置,該電路板之安裝面具有複數導電接點,該電路板更具有一相對於該安裝面之測試面,該測試面係用以與一測試機電性連接;該用於探針卡的電路板之迴銲位置的重設方法包含有下列步驟:a.在該電路板之安裝面設置一覆蓋該等導電接點之層狀結構,該層狀結構具有朝向相反方向之一上表面及一下表面,該下表面貼接於該電路板之安裝面;以及b.在該層狀結構形成出符合該等迴銲位置且於該上表面呈開放狀之複數迴銲孔,該等迴銲孔係分別用以設置一銲球,且各該迴銲孔內有一能使其中之銲球與該電路板之導電接點電性連接的導電區塊。 A method for resetting a reflow position of a circuit board for a probe card for redefining a plurality of reflow positions on a mounting surface of a circuit board, the mounting surface of the circuit board having a plurality of conductive contacts The circuit board further has a test surface relative to the mounting surface, the test surface is for electrically connecting with a test; the method for resetting the reflow position of the circuit board for the probe card comprises the following steps: a layered structure covering the conductive contacts on the mounting surface of the circuit board, the layer structure having an upper surface and a lower surface facing in opposite directions, the lower surface being attached to the mounting surface of the circuit board And b. forming, in the layered structure, a plurality of reflow holes conforming to the reflow locations and being open on the upper surface, the reflow holes being respectively used to set a solder ball, and each of the reflows The hole has a conductive block capable of electrically connecting the solder ball to the conductive contact of the circuit board. 如申請專利範圍第1項所述之用於探針卡的電路板之迴銲位置的重設方法,其中該步驟a係於該電路板之安裝面塗佈一絕緣光阻層以成為該層狀結構,該步驟b包含有下列步驟:b1.使光線隔著一與該層狀結構之上表面相對的光罩而對該層狀結構進行曝光,該光罩具有一符合該等迴銲孔之圖樣,且各個迴銲孔之位置至少與一個所述之導電接點的一部分重疊;以及b2.對該層狀結構進行顯影,以形成出該等迴銲孔,各該迴銲孔係貫穿該層狀結構之上表面與下表面,使對應之導 電接點至少有一部分暴露出來,形成各該迴銲孔內之導電區塊。 The method for resetting a reflow position of a circuit board for a probe card according to claim 1, wherein the step a is to apply an insulating photoresist layer to the mounting surface of the circuit board to become the layer. The step b includes the following steps: b1. exposing the light to the layer structure through a mask opposite to the upper surface of the layer structure, the mask having a reflow hole a pattern, wherein each of the reflow holes is overlapped with at least a portion of the one of the conductive contacts; and b2. the layer structure is developed to form the reflow holes, each of the reflow holes being through The upper surface and the lower surface of the layered structure, so that the corresponding guide At least a portion of the electrical contacts are exposed to form conductive segments within each of the reflow holes. 如申請專利範圍第1項所述之用於探針卡的電路板之迴銲位置的重設方法,其中該步驟a包含有下列步驟:a1.利用微影製程(photolithography)在該電路板之安裝面設置一第一絕緣光阻層,該第一絕緣光阻層具有朝向相反方向之一頂面及一底面,以及複數貫穿該頂面與該底面之第一穿孔,該底面即為該層狀結構之下表面,各該第一穿孔係位置對應於一該導電接點,使各該導電接點至少有一部分係暴露於對應之第一穿孔中;a2.在該等第一穿孔內分別形成一第一導電塊,使得各該第一導電塊與其所在之第一穿孔所對應的導電接點電性連接;以及a3.在該第一絕緣光阻層之頂面設置一第二絕緣光阻層,該第二絕緣光阻層具有朝向相反方向之一頂面及一底面,該第二絕緣光阻層之底面係貼接於該第一絕緣光阻層之頂面。 The method for resetting a reflow position of a circuit board for a probe card according to claim 1, wherein the step a comprises the following steps: a1. using photolithography on the circuit board. a first insulating photoresist layer is disposed on the mounting surface, the first insulating photoresist layer has a top surface and a bottom surface facing in opposite directions, and a plurality of first through holes penetrating the top surface and the bottom surface, wherein the bottom surface is the layer a lower surface of the structure, each of the first perforation lines corresponding to a conductive contact, wherein at least a portion of each of the conductive contacts is exposed to the corresponding first through hole; a2. respectively in the first through holes Forming a first conductive block such that each of the first conductive blocks is electrically connected to a conductive contact corresponding to the first through hole; and a3. providing a second insulating light on a top surface of the first insulating photoresist layer The second insulating photoresist layer has a top surface and a bottom surface facing in opposite directions, and a bottom surface of the second insulating photoresist layer is attached to a top surface of the first insulating photoresist layer. 如申請專利範圍第3項所述之用於探針卡的電路板之迴銲位置的重設方法,在該步驟a3中,該第二絕緣光阻層係覆蓋該等第一導電塊,且該第二絕緣光阻層之頂面即為該層狀結構之上表面;該步驟b包含有下列步驟:b1.使光線隔著一與該第二絕緣光阻層之頂面相對的光罩而對該第二絕緣光阻層進行曝光,該光罩具有一符合該等 迴銲孔之圖樣,且各個迴銲孔之位置至少與一個所述之第一導電塊的一部分重疊;以及b2.對該第二絕緣光阻層進行顯影,以形成出該等迴銲孔,各該迴銲孔係貫穿該第二絕緣光阻層之頂面與底面,使對應之第一導電塊至少有一部分暴露出來,形成各該迴銲孔內之導電區塊。 The method for resetting a reflow position of a circuit board for a probe card according to claim 3, wherein in the step a3, the second insulating photoresist layer covers the first conductive blocks, and The top surface of the second insulating photoresist layer is the upper surface of the layered structure; the step b includes the following steps: b1. traversing the light through a mask opposite to the top surface of the second insulating photoresist layer And exposing the second insulating photoresist layer, the photomask has a compliance with the Refining the pattern of the holes, and each of the reflow holes is overlapped with at least a portion of the first conductive block; and b2. developing the second insulating photoresist layer to form the reflow holes, Each of the reflow holes penetrates the top surface and the bottom surface of the second insulating photoresist layer, so that at least a portion of the corresponding first conductive block is exposed to form a conductive block in each of the reflow holes. 如申請專利範圍第4項所述之用於探針卡的電路板之迴銲位置的重設方法,其中各該第一導電塊具有一不與該電路板之導電接點位置對應之延伸段,各該迴銲孔內之導電區塊係完全位於第一導電塊之延伸段。 The method for resetting a reflow position of a circuit board for a probe card according to claim 4, wherein each of the first conductive blocks has an extension that does not correspond to a position of a conductive contact of the circuit board. The conductive blocks in each of the reflow holes are completely located in the extension of the first conductive block. 如申請專利範圍第3項所述之用於探針卡的電路板之迴銲位置的重設方法,其中該步驟a3係利用微影製程形成該第二絕緣光阻層,該第二絕緣光阻層具有複數貫穿其頂面與底面之第二穿孔,各該第二穿孔係位置對應於一該第一導電塊,使各該第一導電塊至少有一部分暴露於對應之第二穿孔中;該步驟a更包含有下列步驟:a4.在該等第二穿孔內分別形成一第二導電塊,使得各該第二導電塊與其所在之第二穿孔所對應之第一導電塊電性連接;以及a5.在該第二絕緣光阻層之頂面設置一第三絕緣光阻層,該第三絕緣光阻層具有朝向相反方向之一頂面及一底面,該第三絕緣光阻層之底面係貼接於該第二絕緣光阻層之頂面。 The method for resetting a reflow position of a circuit board for a probe card according to claim 3, wherein the step a3 forms the second insulating photoresist layer by using a lithography process, the second insulating light The resisting layer has a plurality of second through holes extending through the top surface and the bottom surface, each of the second punching line positions corresponding to a first conductive block, so that at least a portion of each of the first conductive blocks is exposed to the corresponding second through hole; The step a further includes the following steps: a4. forming a second conductive block in the second through holes, such that each of the second conductive blocks is electrically connected to the first conductive block corresponding to the second through hole; And a5. a third insulating photoresist layer is disposed on the top surface of the second insulating photoresist layer, the third insulating photoresist layer has a top surface and a bottom surface facing in opposite directions, and the third insulating photoresist layer The bottom surface is attached to the top surface of the second insulating photoresist layer. 如申請專利範圍第6項所述之用於探針卡的電路板之迴銲位置的重設方法,在該步驟a5中,該第三絕緣光阻層係覆蓋該等第二導電塊,且該第三絕緣光阻層之頂面即為該層狀結構之上表面;該步驟b包含有下列步驟:b1.使光線隔著一與該第三絕緣光阻層之頂面相對的光罩而對該第三絕緣光阻層進行曝光,該光罩具有一符合該等迴銲孔之圖樣,且各個迴銲孔之位置至少與一個所述之第二導電塊的一部分重疊;以及b2.對該第三絕緣光阻層進行顯影,以形成出該等迴銲孔,各該迴銲孔係貫穿該第三絕緣光阻層之頂面與底面,使對應之第二導電塊至少有一部分暴露出來,形成各該迴銲孔內之導電區塊。 The method for resetting a reflow position of a circuit board for a probe card according to claim 6, wherein in the step a5, the third insulating photoresist layer covers the second conductive blocks, and The top surface of the third insulating photoresist layer is the upper surface of the layered structure; the step b includes the following steps: b1. traversing the light through a mask opposite to the top surface of the third insulating photoresist layer And exposing the third insulating photoresist layer, the photomask has a pattern conforming to the reflow holes, and the positions of the reflow holes are overlapped with at least a portion of the second conductive block; and b2. Developing the third insulating photoresist layer to form the reflow holes, each of the reflow holes penetrating the top surface and the bottom surface of the third insulating photoresist layer, so that the corresponding second conductive block has at least a portion Exposed to form conductive blocks in each of the reflow holes. 如申請專利範圍第7項所述之用於探針卡的電路板之迴銲位置的重設方法,其中各該第一導電塊係完全位於其所在之第一穿孔所對應的導電接點上。 The method for resetting a reflow position of a circuit board for a probe card according to claim 7, wherein each of the first conductive blocks is completely located on a conductive contact corresponding to the first through hole thereof . 如申請專利範圍第7項所述之用於探針卡的電路板之迴銲位置的重設方法,其中各該第二導電塊具有一不與該電路板之導電接點位置對應之延伸段,各該迴銲孔內之導電區塊係完全位於第二導電塊之延伸段。 The method for resetting a reflow position of a circuit board for a probe card according to claim 7, wherein each of the second conductive blocks has an extension that does not correspond to a position of a conductive contact of the circuit board. The conductive blocks in each of the reflow holes are completely located in the extension of the second conductive block. 如申請專利範圍第7項所述之用於探針卡的電路板之迴銲位置的重設方法,其中在步驟a3中,各該第一導電塊係完全暴露於對應之第二穿孔中。 A method of resetting a reflow position of a circuit board for a probe card according to claim 7, wherein in step a3, each of the first conductive blocks is completely exposed to the corresponding second perforation. 如申請專利範圍第1項所述之用於探針卡的電路板之迴銲位置的重設方法,其中該電路板在定義出該等迴銲位 置之前,係能被用於晶片封裝完成後的最終測試的測試介面中,而該電路板在定義出該等迴銲位置之後,係能被用於在晶片封裝前進行裸晶測試所使用的探針卡中。 A method for resetting a reflow position of a circuit board for a probe card according to claim 1, wherein the circuit board defines the reflow position Before being placed, it can be used in the test interface of the final test after the wafer package is completed. After defining the reflow locations, the board can be used for the bare crystal test before the wafer package. In the probe card. 如申請專利範圍第11項所述之用於探針卡的電路板之迴銲位置的重設方法,其中該最終測試的測試介面係為具有一承接座且用以電性連接最終測試之測試機與晶片封裝完成後的封裝晶片之測試介面。 The method for resetting a reflow position of a circuit board for a probe card according to claim 11, wherein the test interface of the final test is a test having a socket and electrically connected to the final test. The test interface of the packaged wafer after the machine and chip package are completed.
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