TWI517592B - Communication system and sample rate converter thereof - Google Patents

Description

Communication system and its sample rate converter

The present invention relates to a sample rate converter (SRC) and is particularly relevant to a sample rate converter that is capable of changing the operational configuration.

With the advancement of electronic related technologies, various types of communication devices are becoming more and more popular. Most of the transmitters or receivers in current communication equipment will contain analog circuits and front-end digital circuits. The two signal types have digital-to-analog converters or analog-to-digital converters.

Figure 1 shows a simplified functional block diagram of the transmitter circuit in the 3rd Generation Partnership Project (3GPP) communication device. In order to avoid interference of the higher harmonics of each pulse in the digital signal to the analog circuit, the digital circuit 120 and the analog circuit 160 are usually physically separated by a guard distance to avoid coupling interference. In addition, in order to further reduce the negative impact that the higher harmonics of the digital pulse may cause on the analog circuit 160, the signal to be transmitted 110 passes through a sample rate converter 122 before entering the digital-to-analog converter 140. The sample rate of the up-converted signal 130 output by the sample rate converter 122 is equal to the operational sample rate of the analog circuit 160 divided by a particular integer. In other words, the operational sampling rate of the analog circuit 160 is an integer multiple of the sampling rate of the up-converted signal 130. Similarly, a digital bit circuit of a 3GPP receiver (not shown) also includes a sample rate converter for downconverting the input signal.

Sample rate converter as known to those of ordinary skill in the art to which the present invention pertains The correctness of the conversion result is related to its order. The higher the order rate conversion, the more circuit components/computing programs, the higher the power consumption, but usually provides better conversion results. On the other hand, the external environment faced by communication devices often changes over time. In order to maintain normal operation in a communication environment (such as a large amount of noise interference), the sampling rate converters in communication devices are mostly designed to have a higher order. For mobile communication devices with limited power due to the use of batteries, the high power consumption caused by the high-order sampling rate converter is undoubtedly a disadvantage, which may cause the standby time to drop.

To solve the above problems, the present invention proposes a new sampling rate conversion scheme. Unlike the prior art practice of employing a fixed order sample rate converter, the communication system and sample rate conversion method in accordance with an embodiment of the present invention takes into account one or more constraints and dynamically adjusts the configuration of the sample rate converter. In turn, the power consumption of the sample rate converter is changed or other performance indicators. In communication environments where high quality conversion results are not required, the sample rate converter can be set to operate in a lower power configuration to save power in the communication system.

In accordance with an embodiment of the present invention, a communication system includes a sample rate converter and a controller that are configurable. The sample rate converter is configured to convert a digital signal having a first sampling rate into a converted signal having a second sampling rate. The sample rate converter can operate in a first configuration or a second configuration different from the first configuration. The controller is configured to dynamically control the sampling rate converter to operate in one of the first configuration and the second configuration according to at least one constraint condition.

Another embodiment in accordance with the present invention is a sampling rate conversion method for use in a communication system. A sample rate conversion program can operate in a first configuration or a second configuration different from the first configuration. The sampling rate conversion method includes the following steps: (a) determining one of the sampling rate conversion procedures to configure a switching rule according to at least one restriction condition; and (b) switching the rule according to the configuration to the first configuration and the first The sampling rate conversion procedure is switched between the two configurations.

Another embodiment of the present invention is a changeable configuration sample rate converter for converting a digital signal having a first sampling rate into a converted signal having a second sampling rate. The sample rate converter includes a sample rate conversion circuit and a controller. The sample rate conversion circuit can operate in at least two different configurations. The controller is configured to dynamically control the sampling rate conversion circuit to operate in one of the at least two different configurations according to at least one constraint condition.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

110‧‧‧ signals to be transmitted

120‧‧‧Digital Circuit

122‧‧‧Sampling rate converter

130‧‧‧Upconverted signal

140‧‧‧Digital-to-analog converter

160‧‧‧ analog circuit

200‧‧‧Communication system

210‧‧‧Changeable configuration of sample rate converter

215‧‧‧ Controller

220‧‧‧Digital Circuit

240‧‧‧Digital-to-analog converter

260‧‧‧ analog circuit

210A‧‧‧Low-order sampling rate conversion circuit

210B‧‧‧High-order sampling rate conversion circuit

210C‧‧‧Multiplexer

210D‧‧‧ delay element

212‧‧‧High-order sampling rate conversion circuit

212A‧‧‧Local Circuit

212B‧‧‧Multiplexer

212C‧‧‧ Multiplier

S82~S84‧‧‧ Process steps

FIG. 1 is a block diagram showing the simple function of the transmitting end circuit in the 3GPP communication device.

2 is a functional block diagram of a communication system in accordance with an embodiment of the present invention.

Figure 3 shows an example of the correspondence between the operating order of the sample rate converter and several constraints.

Figures 4(A) and 4(B) present examples of configuration switching methods employed by the controller in accordance with the present invention.

Figures 5(A) and 5(B) illustrate an example of an internal circuit configuration of a sample rate converter in accordance with the present invention.

Figure 6 (A) shows another internal circuit configuration example of the sampling rate converter according to the present invention; Figure 6 (B) shows a detailed implementation example of the sampling rate converter; Figure 6 (C) shows the sampling rate. An example of signal timing for a converter; Figure 6(D) shows the extent of the local circuit used to generate the low-order conversion result; Figure 6(E) shows an example of the implementation of turning off the multiplier in the low-order configuration.

Figure 7 presents a detailed implementation example of another sample rate conversion circuit in accordance with the present invention.

Figure 8 is a flow chart of a sampling rate conversion method in accordance with an embodiment of the present invention.

A specific embodiment of the present invention is a communication system, and a functional block diagram thereof is shown in FIG. It should be noted that the phrase "the invention" is used herein to refer to the inventive concepts presented in the embodiments, but the scope of the invention is not limited by the embodiments themselves. In addition, the mathematical expressions in the present disclosure are intended to illustrate the principles and logic associated with the embodiments of the present invention, and the scope of the present invention is not limited unless otherwise specified.

The communication system 200 includes a changeable configuration sample rate converter 210 and a controller 215. In this embodiment, the sample rate converter 210 is included in the digital circuit 220 for converting a digital signal having one of the input sampling rates F _IN into a converted signal having another output sampling rate F _OUT . The converted signal is then sequentially supplied to the digital-to-analog converter 240 and the analog circuit 260 so that the operational sampling rate of the analog circuit 260 is an integer multiple of the sampling rate of the converted signal, which helps to reduce the digital pulse wave. Interference with analog circuit 260.

The sample rate converter 210 can operate in at least two different configurations. For example, the sample rate converter 210 can be designed to have different operational orders in two different configurations. Alternatively, the sample rate converter 210 can be designed to have the same operational order in two different configurations, but with different operational complexity. In general, sampling rate conversions with higher operating orders or higher complexity are more power-hungry. The configuration change mode of the sampling rate converter 210 will be described in detail later. The following description mainly takes the case where the sampling rate converter 210 has different operating orders of the first configuration and the second configuration, but the scope of the present invention is not limited thereto. Further, it will be understood by those of ordinary skill in the art to which the present invention pertains, the scope of the present invention is not limited to the case where the number of configurations of the sampling rate converter 210 is two.

In practical applications, the controller 215 can be disposed inside the digital circuit 220, or can be independent of the digital circuit 220 as shown in FIG. The controller 215 is configured to dynamically control the sampling rate converter 210 to operate in the first configuration or the second configuration according to at least one restriction condition. The constraints provided to the controller 215 may include, but are not limited to, the communication system 200 measuring the transmitter quality, the quality of the transmission channel, or the correlation determined by the quality of the receiver, such as error vector magnitude (EVM), adjacent channels. Adjacent channel leakage power Ratio, ACLR), TX spurious emission at RX band, or transmit signal output power. The table presented in FIG. 3 is an example of the correspondence between the operating order of the sampling rate converter 210 and several constraints. As shown in the table, the controller 215 can cause the sample rate converter 210 to operate in a lower order group when the required error vector magnitude is poor, the transmitted end mixed emission amount is low, or the signal output power is low. state. In summary, when the quality of the communication environment is better, the sample rate converter 210 does not need to operate in a high-order configuration with high power consumption. In contrast, when the quality of the communication environment is poor, the sample rate converter 210 can be switched to a higher order configuration that provides better performance. Thereby, the average power consumption of the sampling rate converter 210 can be reduced without impairing the overall operational performance of the communication system 200.

Moreover, the constraints provided to controller 215 may also include restrictions from communication system 200 itself, such as the power state of communication system 200. For example, when the controller 215 finds that the power of the communication system 200 is lower than a threshold, the sampling rate converter 210 that is originally configured to operate at a higher power consumption can be switched to operate at a lower power consumption. Configuration to extend the usable time of the communication system 200. The manner of generating the foregoing various limitations is known to those of ordinary skill in the art to which the present invention pertains, and therefore will not be described again.

In practice, the controller 215 can determine the configuration switching rules of the sample rate converter 210 using a lookup table or a logic operation circuit. Taking the table shown in FIG. 3 as an example, the controller 215 can use a constraint condition as an index value, find a corresponding operation order, and determine how to switch the sample rate converter 210 according to the search result. It should be noted that the various numerical values in the correspondences may be determined by the circuit designer of the communication system 200 based on practical experience, and are not limited to those listed in FIG. It will be understood by those of ordinary skill in the art that the correspondence and the logic rules of the controller 215 to select the order can also be implemented by using a circuit including a comparator, a logic gate, etc., or written as a non- The transient computer can read the media and store it in the memory of the controller 215.

When a plurality of restriction conditions must be considered at the same time, the controller 215 can find a corresponding operation order according to each constraint condition, and then find the plurality of operation orders obtained by the self-search. Select the one that is the largest as the final selected operational order. In other words, the controller 215 may determine a first order for the sampling rate converter 210 according to the first constraint condition, determine a second order for the sampling rate converter 210 according to the second limiting condition, and according to the first order number. The configuration switching rule of the sampling rate converter 210 is determined by the larger of the second order.

In an embodiment of the invention, the controller selects an operation order for the sample rate converter to be an integer or a non-integer. It is assumed that the operation order corresponding to the sample rate converter 210 in the first configuration is a positive integer N, and the operation order corresponding to the sample rate converter 210 in the second configuration is another positive integer M. In one embodiment, the operational order selected by the controller 215 for the sample rate converter 210 is between the first operational order N and the second operational order M. Taking N equal to 1, M equal to 2 as an example, if the controller 215 selects the operating order of the sampling rate converter 210 to be 1.5, the controller 215 can cause the sampling rate converter 210 to be in the first configuration and the second group. The inter-state timings alternately switch and each occupy 50% of the working time. As shown in FIG. 4(A), the controller 215 can cause the sample rate converter 210 to operate in the first configuration for the first 50% of the time period T and the second configuration for the last 50% of the time. The controller 215 can also split the time when the sampling rate converter 210 operates in the first configuration and the second configuration into two segments T*25% as shown in FIG. 4(B). Similarly, if N is equal to 1, M is equal to 3, the sampling rate converter 210 is alternately switched between the first configuration and the second configuration, and each occupies 50% of the working time, so that the sampling rate converter 210 can be The operating order is equivalent to 2.

In one embodiment, when the controller 215 selects to alternately switch the sample rate converter 210 between the two configurations to achieve a particular operational order, the controller 215 utilizes a delta-sigma modulation (Delta-Sigma Modulation). A program or Pulse Width Modulation is programmed to switch the time allocation manner of the sample rate converter 210 between the first configuration and the second configuration. It can be seen from the above description that the scope of the present invention is not limited to a specific modulation mode as long as a plurality of converter configurations of different orders can be used to realize a modulation mode of a certain operational order. Thereby, the noise generated by switching the configuration can be shifted to a frequency band that does not interfere with the analog circuit 260.

As shown in FIG. 5(A), in an embodiment, the sampling rate converter 210 includes a low-order sampling rate conversion circuit 210A and a high-order sampling rate conversion circuit 210B. When the sample rate converter 210 operates in a low order configuration, the low order sample rate conversion circuit 210A is activated. When the sample rate converter 210 operates in a high order configuration, the high order sample rate conversion circuit 210B is activated. When the low-order sampling rate conversion circuit 210A is activated, the high-order sampling rate conversion circuit 210B can be turned off to save power. In contrast, when the high-order sampling rate conversion circuit 210B is activated, the low-order sampling rate conversion circuit 210A can be turned off.

Figure 5 (B) further presents a detailed embodiment of the sample rate converter 210 shown in Figure 5 (A). In this example, the switching signal tp generated by the controller 215 is used to control the multiplexer 210C to select the low-order sampling rate conversion circuit 210A or the high-order sampling rate conversion to be supplied to the output terminal OUT of the sampling rate converter 210. The output signal of circuit 210B. As is known to those of ordinary skill in the art, higher order sampling rate conversion circuits require more input data to be manipulated to produce an output signal than a low order sampling rate conversion circuit. In order to achieve the effect of seamless switching, a delay element 210D is provided between the low-order sampling rate conversion circuit 210A and the input terminal IN. Taking the operation order of the low-order sampling rate conversion circuit 210A equal to one, the operation order of the high-order sampling rate conversion circuit 210B is equal to two, and the input sampling rate F _IN is 10 MHz as an example, the delay time provided by the delay element 210D is approximately Equal to 0.1 microseconds, that is, the input point number of the circuits 210A, 210B is multiplied by the reciprocal of the input sample rate F _IN . In this example, the input displacement difference between the second-order transconverter and the first-order transponder is 1. In this way, the output signals of the low-order sampling rate conversion circuit 210A and the high-order sampling rate conversion circuit 210B at the same time can be maintained to correspond to the same input signal. Furthermore, in order to further ensure that the output terminal OUT does not appear glitch due to the state change of the switching signal tp, the controller 215 can be designed to arrange the state transition time point of the switching signal tp to be synchronized with the input sampling rate F _IN or The state transition time point of the clock signal of the sampling rate F _OUT is output.

As shown in FIG. 6(A), in another embodiment, the sample rate converter 210 includes a high The order sampling rate conversion circuit 212. When the sample rate converter 210 is operating in a low order configuration, one of the high order sample rate conversion circuits 212 is utilized to generate a low order conversion result. In theory, the number of components (eg, multipliers, delay elements, adders, subtractors, ...) of the high-order sample rate conversion circuit will be higher than the number of components required to form a low-order sample rate conversion circuit. Therefore, by appropriately selecting the circuit components and using the multiplexer, the high-order sampling rate conversion circuit can also provide low-order conversion results, that is, equivalent to embedding a low-order sampling rate conversion circuit in the high-order sampling rate conversion circuit. When the sample rate converter 210 operates in a high-order configuration, the multiplexer in the high-order sample rate conversion circuit 212 is controlled to output high-order conversion results.

FIG. 6(B) shows a detailed implementation example of the high-order sampling rate conversion circuit 212, and FIG. 6(C) shows an example of the signal timing of the sampling rate conversion circuit. When the switching signal tp is 1, the output terminal OUT provides a first-order conversion result; when the switching signal tp is 0, the output terminal OUT provides a second-order conversion result. In FIG. 6(D), the circuit element included in the partial circuit 212A is a solid line or has a solid outer frame, and circuit elements other than the partial circuit 212A are indicated as dashed lines or have a dotted outer frame. In an embodiment, when the sampling rate converter 210 operates in a low-order configuration, circuit components outside the partial circuit 212A, that is, circuit components that are not required when the low-order conversion result is generated, may be partially or completely turned off. To reduce power consumption.

In practical applications, multipliers implemented with combinational logic elements are quite power intensive. Fig. 6(E) shows an example of an embodiment in which a multiplier 212C is turned off by the multiplexer 212B to reduce power consumption in the first-order configuration.

It should be noted that the delay element input as signal A and output as signal B in FIG. 6(B) can be regarded as equivalent to delay element 210D in FIG. 5(B). Therefore, the sampling rate conversion circuit presented in FIG. 6(B) can also achieve the aforementioned seamless switching effect. In addition, the state transition time point of the switching signal tp is arranged to be synchronized to the state transition time point of the clock signal of the input sampling rate F _IN or the output sampling rate F _OUT , and the output terminal OUT in FIG. 6(B) can be further ensured. A glitch will occur due to a change in the state of the switching signal tp.

Figure 7 presents a detailed implementation example of another sample rate conversion circuit in accordance with the present invention. The switching signal tp supplied to the sampling rate conversion circuit 700 for controlling each multiplexer is dynamically adjusted by a controller (not shown) according to at least one restriction condition. When the switching signal tp is 2, the output terminal OUT provides a first-order conversion result; when the switching signal tp is 1, the output terminal OUT provides a second-order conversion result; when the switching signal tp is 0, the output terminal OUT provides Is the result of the third-order conversion. Similarly, when the sample rate conversion circuit 700 operates in a low-order configuration, components that are independent of the low-order configuration operation (eg, multipliers implemented as combinatorial logic elements) can be selectively turned off to save the sample rate conversion circuit. The overall power consumption of the 700. In this example, the input displacement difference between the third-order frequency converter and the first-order frequency converter is 2, and the input displacement difference between the second-order frequency converter and the first-order frequency converter is 1. In this way, the output signals of the low-order sampling rate conversion circuit and the high-order sampling rate conversion circuit at the same time can be maintained to correspond to the same input signal. As can be seen from this embodiment, the sampling rate conversion circuit that can be employed in accordance with an embodiment of the present invention is not limited to the number of modes being equal to two.

Another embodiment of the present invention is a sampling rate conversion method applied to a communication system, and a flow chart thereof is shown in FIG. A sample rate conversion program can operate in at least two different configurations. First, step S82 is to determine one of the sampling rate conversion programs to configure the switching rule according to at least one restriction condition. Next, step S84 is to switch the sampling rate conversion program between the at least two different configurations according to the configuration switching rule. The various operational changes previously described in the introduction of the communication system presented in Figure 2 (e.g., the type of limiting conditions and the manner in which the configuration switching rules are generated) can also be applied to this sampling rate conversion method, and the details thereof will not be described again.

It should be noted that the scope of the present invention is not limited to the transmitting end in the communication system, nor is it limited to the 3rd Generation Partnership Project (3GPP) communication device. For example, the sample rate converter 210 and the controller 215, which can be changed in configuration, can also be disposed at the receiving end of the communication system for dynamically adjusting the frequency reduction according to the constraints of the transmitter quality, the transmission channel quality, and the receiver quality. Converted electricity Road configuration. In addition, the concept of the present invention can also be applied to various other electronic devices that require sampling rate conversion, such as an image processing system that requires interpolation to generate more pixels to expand the size of the image, or a downsampling of multiple pixels of data ( Decimation) Program to reduce the size of the image processing system. A higher sampling rate conversion configuration provides better image processing results, while a lower operating rate sampling rate configuration provides higher image processing speed and lower power consumption.

As described above, the present invention proposes a new sampling rate conversion scheme. Unlike the prior art practice of employing a fixed order sample rate converter, the communication system and sample rate conversion method in accordance with an embodiment of the present invention takes into account one or more constraints and dynamically adjusts the configuration of the sample rate converter. In turn, the power consumption of the sample rate converter is changed or other performance indicators. In communication environments where high quality conversion results are not required, the sample rate converter can be set to operate in a lower power configuration to save power in the communication system.

The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.

200‧‧‧Communication system

210‧‧‧Changeable configuration of sample rate converter

215‧‧‧ Controller

220‧‧‧Digital Circuit

240‧‧‧Digital-to-analog converter

260‧‧‧ analog circuit

Claims (15)

A communication system includes: a changeable configuration sampling rate converter for converting a digital signal having a first sampling rate into a converted signal having a second sampling rate, the sampling rate converter capable of Operating in a first configuration or a second configuration different from the first configuration; and a controller for dynamically controlling the sampling rate converter to operate in the first configuration and according to at least one constraint condition One of the second configurations; wherein the at least one constraint condition comprises one or more of the following parameters: an error vector magnitude (EVM), an adjacent channel leakage power ratio (ACLR) ), a TX spurious emission at RX band, a transmitter signal output power, and a power state. A communication system includes: a changeable configuration sampling rate converter for converting a digital signal having a first sampling rate into a converted signal having a second sampling rate, the sampling rate converter capable of Operating in a first configuration or a second configuration different from the first configuration; and a controller for dynamically controlling the sampling rate converter to operate in the first configuration and according to at least one constraint condition One of the second configurations; wherein the at least one constraint condition includes a first constraint condition and a second constraint condition, and the controller determines a first order for the sample rate converter according to the first constraint condition Determining a second order for the sampling rate converter according to the second constraint condition, and determining one of the sampling rate converters to switch according to one of the first order number and the second order number rule. A communication system includes: a changeable configuration sampling rate converter for converting a digital signal having a first sampling rate into a converted signal having a second sampling rate, the sampling rate converter Capable of operating in a first configuration or a second configuration different from the first configuration; and a controller for dynamically controlling the sampling rate converter to operate in the first configuration according to at least one constraint condition And one of the second configurations; wherein the first configuration corresponds to a first operational order N, the second configuration corresponds to a second operational order M, N and M are different, and each is a positive integer; the controller determines an operational order according to the at least one condition, the order is between the first operational order N and the second operational order M, and dynamically controls the operation according to the operational order The sample rate converter operates in one of the first configuration and the second configuration. A communication system includes: a changeable configuration sampling rate converter for converting a digital signal having a first sampling rate into a converted signal having a second sampling rate, the sampling rate converter capable of Operating in a first configuration or a second configuration different from the first configuration; and a controller for dynamically controlling the sampling rate converter to operate in the first configuration and according to at least one constraint condition One of the second configurations; wherein the controller determines a configuration switch of the sample rate converter by using a delta-sigma modulation program or a pulse width modulation program rule. A communication system includes: a changeable configuration sampling rate converter for converting a digital signal having a first sampling rate into a converted signal having a second sampling rate, the sampling rate converter capable of Operating in a first configuration or a second configuration different from the first configuration; and a controller for dynamically controlling the sampling rate converter to operate in the first configuration and according to at least one constraint condition One of the second configurations; wherein the sample rate converter includes a low order sampling rate conversion circuit and a high order sampling rate conversion a circuit; when the sample rate converter operates in the first configuration, the low-order sample rate conversion circuit is enabled; when the sample rate converter operates in the second configuration, the high-order sample rate conversion circuit is activated . The communication system of claim 5, wherein the sampling rate converter further comprises a delay element disposed between the input end of the sample rate converter and the low order sampling rate conversion circuit. The delay element provides a delay time length associated with the first sampling rate, and is also related to a sampling operation point displacement difference between the low order sampling rate conversion circuit and the high order sampling rate conversion circuit. The communication system of claim 6, wherein the controller controls the sampling rate converter through a switching signal, wherein a clock signal is used to provide one of the first sampling rate and the second sampling rate. The state transition time point of one of the switching signals is synchronized to a state transition time point of the clock signal. A communication system includes: a changeable configuration sampling rate converter for converting a digital signal having a first sampling rate into a converted signal having a second sampling rate, the sampling rate converter capable of Operating in a first configuration or a second configuration different from the first configuration; and a controller for dynamically controlling the sampling rate converter to operate in the first configuration and according to at least one constraint condition One of the second configurations; wherein the sampling rate converter comprises a high-order sampling rate conversion circuit; and when the sampling rate converter operates in the first configuration, a partial circuit in the high-order sampling rate conversion circuit It is utilized to generate a low-order conversion result; when the sample rate converter operates in the second configuration, the high-order sample rate conversion circuit is utilized to generate a high-order conversion result. The communication system of claim 8, wherein the high-order sampling rate conversion circuit comprises a delay element disposed between an input end of the high-order sampling rate conversion circuit and the local circuit, the delay The component provides one of the delay time lengths and the first sampling rate Off, also related to the sampling operation point displacement difference between the first configuration and the second configuration. The communication system of claim 8, wherein when the sampling rate converter operates in the first configuration, one of the high-order sampling rate conversion circuits and the one of the partial circuits is turned off. A sampling rate conversion method applied to a communication system, comprising: (a) determining, according to at least one constraint condition, a configuration switching rule of a sampling rate conversion program, wherein the sampling rate conversion program can operate at a first Configuring or different from the second configuration of the first configuration; and (b) switching the sampling rate conversion procedure between the first configuration and the second configuration according to the configuration switching rule; wherein the at least A constraint condition includes one or more of the following parameters: an error vector magnitude, an adjacent channel leakage power ratio, a transmitter mixed emission amount, a transmitter signal output power, and a power state. A sampling rate conversion method applied to a communication system, comprising: (a) determining, according to at least one constraint condition, a configuration switching rule of a sampling rate conversion program, wherein the sampling rate conversion program can operate at a first Configuring or different from the second configuration of the first configuration; and (b) switching the sampling rate conversion procedure between the first configuration and the second configuration according to the configuration switching rule; wherein the at least A limiting condition includes a first limiting condition and a second limiting condition, and step (a) includes: determining, according to the first limiting condition, a first order for the sampling rate conversion program; and sampling according to the second limiting condition The rate conversion program determines a second order; and determines the configuration switching rule based on one of the first order and the second order. A sampling rate conversion method applied to a communication system, comprising: (a) determining, according to at least one constraint condition, a configuration switching rule of a sampling rate conversion program, wherein the sampling rate conversion program can operate at a first Configuring or different from the second configuration of the first configuration; and (b) switching the sampling rate conversion program between the first configuration and the second configuration according to the configuration switching rule; wherein the A configuration corresponds to a first operational order N, the second configuration corresponds to a second operational order M, N and M are different, and each is a positive integer; the configuration switching rule corresponds to one operational order The number is between the first operational order N and the second operational order M, and the step (b) includes: determining an operational order according to the at least one condition, the order being between the first operational order N And between the second operational order M; and dynamically controlling the sampling rate conversion program to operate in one of the first configuration and the second configuration according to the operational order. The sampling rate conversion method according to claim 13, wherein the step (b) comprises determining the configuration switching rule by using a trigonometric-integral modulation program or a pulse width modulation program. A changeable configuration sampling rate converter for converting a digital signal having a first sampling rate into a converted signal having a second sampling rate, comprising: a sampling rate conversion circuit capable of operating at least Two or more different configurations; and a controller for dynamically controlling the sampling rate conversion circuit to operate in one of the at least two different configurations according to at least one constraint condition; wherein the controller is the at least one The restriction condition is used as input data, and a configuration table switching rule is determined by a lookup table or a logic operation circuit.