TWI517589B - No Inserting Lockout Lockout phase lock loop - Google Patents

Description

Injection-locked phase-locked loop without frequency divider

The invention relates to an injection-locked phase-locked loop without a frequency divider, in particular to an injection-locked phase-locked loop without a frequency divider which can reduce the power consumption of the whole phase-locked loop.

Phase locked loop (PLL) is a phase synchronization circuit that can follow the input signal, that is, a frequency negative feedback circuit. The action of the voltage controlled oscillator frequency in the closed loop can often be maintained and input. A circuit with a consistent frequency of signals. With its narrow-band filtering characteristics and excellent electrical characteristics due to the development of IC technology, phase-locked loops are widely used in communications, control circuits, and test instruments. Among them, the integer phase-locked loop has been used in the field of communication for a long time. The composition and design of the basic circuit block also have mature technology and corresponding theory. Nowadays, in addition to the circuit performance, the integer phase-locked loop also requires low power consumption. To extend the scope of its application to the field of biomedical electronics. However, after the traditional phase-locked loop is locked, its frequency divider cannot be discarded, and the power consumption of the overall phase-locked loop cannot be reduced, so that the overall power consumption can be too high. Therefore, how to design an injection-locked phase-locked loop without a frequency divider that can reduce the power consumption of the overall phase-locked loop has become the goal of related manufacturers and related R&D personnel.

The inventor of the present invention has the disadvantage that the conventional phase-locked loop has a high overall power consumption due to the inability to discard the frequency-dividing circuit after locking, and actively develops, in order to improve the above-mentioned shortcomings and continuously test And efforts, finally developed the present invention. The main object of the present invention is to provide an injection-locked phase-locked loop without a frequency divider that can reduce the power consumption of the overall phase-locked loop. In order to achieve the above object, the frequency-injection-free injection-locked phase-locked loop of the present invention comprises: a phase-locked loop comprising a frequency divider loop and a frequency-free loop, the frequency divider loop comprising a a frequency divider and generating a first feedback signal, the frequency divider circuit generating a second feedback signal, wherein the phase locked loop is based on a reference clock signal and a frequency difference between the first feedback signal and a phase difference, or a comparison of the frequency difference and the phase difference of the reference clock signal and the second feedback signal to generate a control voltage, and generating a high frequency clock signal according to the voltage value change of the control voltage; a circuit coupled to the phase-locked loop and having a determinable range at an input end of the reference clock signal of the phase-locked loop, the determinable range being evenly distributed over the reference clock signal of the phase-locked loop Determining the edge, and the determinable range is at most one cycle of the high frequency clock signal; a phase correction circuit is respectively connected to the frequency divider circuit and the no frequency divider circuit, and is digitally controlled And correcting a phase difference between the first feedback signal and the second feedback signal to make the first feedback signal and the second feedback signal equal to avoid the phase-locked loop outputting the frequency-free loop The frequency difference and phase difference between the reference clock signal and the second feedback signal are greater than the determinable range, thereby causing the locked phase-locked loop to be unlocked; and an injection-locked oscillator is coupled to the phase-locked loop, and Used as a frequency multiplier, the injection-locked oscillator injects an output into the phase-locked loop to reduce phase noise of the phase-locked loop; and a frequency correction loop with the phase-locked loop and the injection-locked oscillation The device is connected and digitally corrected to output the frequency output of the reference clock signal as an integral multiple, and then the reference clock signal is injected in a subharmonic injection lock mode so that the output frequency is closer to the reference. An integer multiple of the clock signal while reducing the phase noise of the injection-locked oscillator. Through the above structure, the present invention not only uses a circuit technique to implement a phase-locked loop without a frequency divider under the basic structure of the phase-locked loop, but also reduces the power consumption of the overall phase-locked loop, and adds an injection harmonic lock. The technique maintains the performance of low-phase noise while reducing power consumption, which is different from the conventional method of injecting a phase-locked loop with a reference frequency. The present invention injects a phase-locked loop by a multiple of a reference frequency.

(1). . . Injection-locked phase-locked loop without frequency divider

(10). . . Phase-locked loop

(100). . . Frequency divider loop

(1000). . . Frequency divider

(1001). . . Digitally controlled delay circuit

(101). . . No frequency divider circuit

(102). . . First phase frequency detector

(103). . . Charge pump

(104). . . Low pass filter

(105). . . Voltage controlled oscillator

(11). . . Delay circuit

(110). . . First delay unit

(111). . . Second delay unit

(112). . . Second phase frequency detector

(113). . . Virtual delay circuit

(114). . . Second feedback mode switching unit

(115). . . First gate

(12). . . Phase correction loop

(120). . . D-type flip-flop

(121). . . Countdown timer

(13). . . Injection locked oscillator

(14). . . Frequency correction loop

(140). . . Reference clock signal multiple selection unit

(141). . . Frequency comparison circuit

(142). . . Continuous approximation register

(15). . . First feedback mode switching unit

(16). . . First pulse generator

(17). . . Second pulse generator

1 is a structural diagram of an injection-locked phase-locked loop without a frequency divider of the present invention; the second diagram is a detailed structural diagram of an injection-locked phase-locked loop without a frequency divider of the present invention; A detailed structural diagram of the delay circuit and the phase-locked loop; and a fourth diagram showing the voltage versus time of the injection-locked phase-locked loop without the frequency divider of the present invention.

The preferred embodiments of the present invention are described in detail below with reference to the drawings. Referring to the first figure, the frequency-injection-free injection-locked phase-locked loop (1) of the present invention comprises: a phase-locked loop (10) comprising a frequency divider loop (100) and a non-deletion a frequency converter circuit (101), the frequency divider circuit (100) includes a frequency divider (1000) and generates a first feedback signal, and the frequency divider circuit (101) generates a second feedback signal The phase-locked loop (10) is based on a reference clock signal (fref) and a frequency difference and a phase difference of the first feedback signal, or according to the reference clock signal (fref) and the second feedback signal The frequency difference and the phase difference are compared to generate a control voltage, and a high frequency clock signal is generated according to the voltage value change of the control voltage; a delay circuit (11) is coupled to the phase locked loop (10), and The input end of the reference clock signal (fref) of the phase-locked loop (10) produces a determinable range, and the determinable range is evenly distributed on the reference clock signal (fref) of the phase-locked loop (10) Determining the edge, and the determinable range is at most one cycle of the high frequency clock signal; a phase correction circuit (12) is respectively associated with the The frequency converter circuit (100) and the no-divider circuit (101) are connected, and the phase difference between the first feedback signal and the second feedback signal is adjusted in a digitally controlled manner to enable the first feedback signal and The second feedback signal is equal to avoid the frequency difference and phase difference between the reference clock signal (fref) and the second feedback signal when the phase-locked loop (10) is output by the frequency-free loop (101) Greater than the determinable range, causing the locked phase-locked loop (10) to be unlocked; an injection-locked oscillator (13) coupled to the phase-locked loop (10) and used as a frequency multiplier, An injection-locked oscillator (13) injects an output into the phase-locked loop (10) to reduce phase noise of the phase-locked loop (10); and a frequency correction loop (14) associated with the phase-locked loop ( 10) and the injection-locked oscillator (13) is coupled, and digitally outputs the output to an integer multiple of the reference clock signal (fref) frequency output, and then injected into the subharmonic injection lock Referring to the clock signal (fref), the output frequency is closer to an integer multiple of the reference clock signal (fref), The small injection locked oscillator (13) of the phase noise. Referring to the second and third figures, the phase-locked loop (10) further includes: a first phase frequency detector (102) that receives the reference clock signal (fref) and the feedback signal to Performing frequency and phase comparison, and generating a series of incremental control signals (UP) and decrement control signals (DN) according to the reference clock signal (fref) and the frequency and phase difference of the feedback signal; a charge pump ( 103), connected to the first phase frequency detector (102), and receiving the incremental control signal and the decrementing control signal from the first phase frequency detector (102) for charging and discharging to generate a control Current; a low pass filter (104) coupled to the charge pump (103) and receiving the control current from the charge pump (103), and the increment from the charge pump (103) a control signal and a high frequency signal of the decrement control signal are filtered to generate the control voltage (Vctrl); and a voltage controlled oscillator (105) is coupled to the low pass filter (104) and based on the low pass The voltage value of the control voltage (Vctrl) of the filter (104) generates the high frequency clock signal; Frequency divider (1000) lines connected to the voltage controlled oscillator (105), and generating a first feedback signal based on the clock signal from the voltage controlled oscillator (105) of the high frequency. The output of the injection-locked oscillator (13) is injected into the voltage controlled oscillator (105). The phase correction circuit (12) is composed of a D-type flip-flop (120) and an up-countdown timer (121). The low-pass filter (104) is a second-order loop low-pass filter, which is composed of a resistor connected in series with a first capacitor, and the resistor and the first capacitor are further connected in parallel with a second capacitor. The frequency divider circuit (100) further includes a digital control delay circuit (1001), the digital control delay circuit (1001) is connected in series with the frequency divider (1000), and the upper countdown timer (121) The output is connected. The frequency-injection-free injection-locked phase-locked loop (1) of the present invention further includes a first feedback mode switching unit (15), an input system of the first feedback mode switching unit (15) and the frequency divider The loop (100) and the no-divider circuit (101) are connected, and the output of the first feedback mode switching unit (15) is connected to the input of the first phase frequency detector (102). The pulse-free injection-locked phase-locked loop (1) of the present invention further includes a first pulse generator (16) and a second pulse generator (17), the first pulse generator (16) The input system receives the reference clock signal (fref), and the output of the first pulse generator (16) is connected to the injection-locked oscillator (13), and the output of the injection-locked oscillator (13) is injected. To the second pulse generator (17), and the second pulse generator (17) injects the output of the injection-locked oscillator (13) to the voltage controlled oscillator (105). The delay circuit (11) includes: a first delay unit (110) that receives the reference clock signal (fref) and generates a first delayed reference clock signal (ref1); a second delay unit ( 111), connected to the first delay unit (110), and receiving the first delayed reference clock signal (ref1) to generate a second delayed reference clock signal (ref2); a second phase frequency detection The device (112) is connected to the second delay unit (111), and receives the reference clock signal (fref) and the second delayed reference clock signal (ref2) for frequency and phase comparison, and according to The reference clock signal (fref) and the frequency and phase difference of the second delayed reference clock signal (ref2) generate a series of incremental control signals (UP) and decrement control signals (DN); a virtual delay circuit (113) And consisting of at least two reverse gates connected to the second delay unit (111) and receiving the second delayed reference clock signal (ref2); a second feedback mode switching unit (114), Connected to the second phase frequency detector (112) and receive the hand of the second phase frequency detector (112) a control signal (DN), the second feedback mode switching unit (114) includes a demultiplexer mode and a no-divider mode, when the second feedback mode switching unit (114) is the no-divider In the mode, the decrement control signal (DN) of the second phase frequency detector (112) is output; a first AND gate (115), an input system thereof and the virtual delay circuit (113) and the second feedback The mode switching unit (114) is connected, the output is coupled to the first phase frequency detector (102), and the second gate (116) is coupled to the first feedback mode switching unit (15). The second feedback mode switching unit (114) is coupled to the first phase frequency detector (102). The frequency correction circuit (14) includes: a reference clock signal multiple selection unit (140) for receiving the reference clock signal (fref) and for selecting a multiple of the reference clock signal (fref); The circuit (141) is coupled to the reference clock signal multiple selection unit (140) and the injection-locked oscillator (13), and receives an integer multiple of the reference clock signal (fref) and the reference clock signal ( Fref), and comparing the integer multiple of the reference clock signal (fref) and the reference clock signal (fref) to output an integer multiple of the reference clock signal (fref) and the reference clock signal (fref) a frequency difference; and a continuous approximation register (142) having an input coupled to the frequency comparison circuit (141), the output of which is coupled to the injection-locked oscillator (13), the continuous approximation register (142) Receiving an integer multiple of the reference clock signal (fref) and a frequency difference of the reference clock signal (fref), and using an integer multiple of the reference clock signal (fref) and the reference clock signal (fref) The frequency difference is digitally corrected to make its output fall Times the reference clock signal (FREF) frequency output. Referring to the first and fourth figures, the injector-free injection-locked phase-locked loop (1) of the present invention is first frequency-corrected and locked via the first pulse wave after the phase-locked loop (10) is locked. The device (16) is injected into the injection-locked oscillator (13), and then output to the second pulse generator (17) via the injection-locked oscillator (13) and thereby injected into the voltage-controlled oscillator (105). After the phase correction is performed via the phase correction circuit (12), the first feedback mode switching unit (15) switches to the no-divider circuit, and the phase-locked loop (10) is still locked. The frequency-injection-free injection-locked phase-locked loop (1) of the present invention can discard the frequency divider (1000). Through the above structure, the present invention utilizes a circuit technique to enable the phase-locked loop to remove the frequency divider when locked, thereby reducing the power consumption of the overall phase-locked loop, and using the modified first phase frequency detection. And the phase correction loop is added to ensure that there is no need for a frequency divider in the case of process offset, unlike the conventional method of injecting a phase-locked loop with a reference frequency, the present invention injects a lock with a multiple of the reference frequency. The phase loop can improve its phase noise. Moreover, its structural form is not easily reached by those skilled in the art, and it is novel and progressive. Through the above detailed description, it can fully demonstrate that the object and effect of the present invention are both progressive in implementation, highly industrially usable, and are new inventions not previously seen on the market, and fully comply with the invention patent requirements. , 提出 apply in accordance with the law. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the invention. All changes and modifications made in accordance with the scope of the patent of the invention shall fall within the scope of the patent of the invention. Please ask the reviewer to give a clear explanation and pray for it.

(1). . . Injection-locked phase-locked loop without frequency divider

(10). . . Phase-locked loop

(100). . . Frequency divider loop

(1000). . . Frequency divider

(101). . . No frequency divider circuit

(11). . . Delay circuit

(12). . . Phase correction loop

(13). . . Injection locked oscillator

(14). . . Frequency correction loop

Claims (10)

An injection-locked phase-locked loop without a frequency divider includes: a phase-locked loop comprising a frequency divider loop and a frequency-free loop, the frequency divider loop including a frequency divider and generating a a feedback signal, the non-divider circuit generates a second feedback signal, the phase-locked loop is based on a reference clock signal and a frequency difference and a phase difference of the first feedback signal, or according to the reference Comparing the frequency difference and the phase difference of the pulse signal and the second feedback signal to generate a control voltage, and generating a high frequency clock signal according to the voltage value change of the control voltage; a delay circuit is connected to the phase locked loop Connecting, and creating a determinable range at the input end of the reference clock signal of the phase locked loop, the determinable range is evenly distributed on the judgment edge of the reference clock signal of the phase locked loop, and the determinable range At most one cycle of the high frequency clock signal; a phase correction circuit is respectively connected to the frequency divider circuit and the frequency divider circuit, and the first feedback signal is adjusted in a digitally controlled manner and The phase difference between the two feedback signals is such that the first feedback signal and the second feedback signal are equal, and the reference clock signal and the second back-grant signal are avoided when the phase-locked loop is outputted by the frequency-free loop The frequency difference and the phase difference are greater than the determinable range, and the locked phase locked loop is unlocked; an injection locked oscillator is coupled to the phase locked loop and used as a frequency multiplier, the injection locking An oscillator injects an output into the phase-locked loop to reduce phase noise of the phase-locked loop; and a frequency correction loop coupled to the phase-locked loop and the injection-locked oscillator and digitally corrected The output falls in an integer multiple of the frequency output of the reference clock signal, and the reference clock signal is injected in a subharmonic injection lock mode so that the output frequency is closer to an integer multiple of the reference clock signal, and the Phase noise is injected into the locked oscillator. The injection-locked phase-locked loop without a frequency divider according to the first aspect of the invention, wherein the phase-locked loop further comprises: a first phase frequency detector for receiving the reference clock signal and the feedback signal And comparing the frequency and the phase, and generating a series of incremental control signals (UP) and decrement control signals (DN) according to the frequency and phase difference between the reference clock signal and the feedback signal; a charge pump Connecting to the first phase frequency detector, and receiving the incremental control signal and the decrementing control signal from the first phase frequency detector for charging and discharging to generate a control current; a low pass filter The charge pump is connected and receives the control current from the charge pump, and filters the high frequency signal from the incremental control signal and the decrement control signal of the charge pump to generate the control voltage; and a voltage a controlled oscillator connected to the low pass filter and generating the high frequency clock signal according to a voltage value change of the control voltage from the low pass filter; the frequency divider is connected to the voltage controlled oscillator And generating the first signal based upon feedback from the voltage controlled oscillator to the frequency of the clock signal. The inverter-free injection-locked phase-locked loop of claim 2, wherein the output of the injection-locked oscillator is injected into the voltage-controlled oscillator. The injection-locked phase-locked loop without a frequency divider according to claim 1, wherein the phase correction circuit is composed of a D-type flip-flop and an upper countdown timer. The injection-locked phase-locked loop without a frequency divider according to the second aspect of the patent application, wherein the low-pass filter is a second-order loop low-pass filter, which is connected in series by a resistor and a first capacitor. The resistor and the first capacitor are further connected in parallel with a second capacitor. The injection-locked phase-locked loop without a frequency divider according to the first aspect of the invention, wherein the frequency divider circuit further comprises a digital control delay circuit, the digital control delay circuit is connected in series with the frequency divider, and The output of the upper countdown timer is connected. The injection-locked phase-locked loop without a frequency divider according to claim 2, further comprising a first feedback mode switching unit, the input system of the first feedback mode switching unit and the frequency divider circuit and The no-divider circuit is connected, and the output of the first feedback mode switching unit is connected to the input of the first phase frequency detector. The injection-locked phase-locked loop without a frequency divider according to claim 2, further comprising a first pulse generator and a second pulse generator, wherein the input of the first pulse generator is received The reference clock signal, the output of the first pulse generator is connected to the injection lock oscillator, the output of the injection lock oscillator is injected to the second pulse generator, and the second pulse generator The output of the injection-locked oscillator is injected into the voltage controlled oscillator. The injection-locked phase-locked loop without a frequency divider according to claim 7, wherein the delay circuit includes: a first delay unit that receives the reference clock signal and generates a first delay reference a second delay unit connected to the first delay unit and receiving the first delayed reference clock signal to generate a second delayed reference clock signal; a second phase frequency detector Connected to the second delay unit, and receive the reference clock signal and the second delayed reference clock signal to perform frequency and phase comparison, and according to the reference clock signal and the second delay reference clock signal The frequency and phase difference generate a series of incremental control signals (UP) and decrement control signals (DN); a virtual delay circuit is composed of at least two reverse gates connected and connected to the second delay unit, and receives the a second delay reference clock signal; a second feedback mode switching unit is coupled to the second phase frequency detector and receives the decrement control signal (DN) of the second phase frequency detector, the two The feedback mode switching unit includes a frequency divider mode and a no frequency divider mode, and when the second feedback mode switching unit is in the no frequency divider mode, outputting the decrementing control signal of the second phase frequency detector (DN); a first gate, the input system is coupled to the virtual delay circuit and the second feedback mode switching unit, the output is coupled to the first phase frequency detector; and a second gate is connected The input system is coupled to the first feedback mode switching unit and the second feedback mode switching unit, and the output thereof is coupled to the first phase frequency detector. The method of claim 2, wherein the frequency correction circuit comprises: a reference clock signal multiple selection unit that receives the reference clock signal and selects the Referring to a multiple of the clock signal; a frequency comparison circuit is coupled to the reference clock signal multiple selection unit and the injection-locked oscillator, and receives an integer multiple of the reference clock signal and the reference clock signal, and compares An integer multiple of the reference clock signal and the reference clock signal to output an integer multiple of the reference clock signal and a frequency difference of the reference clock signal; and a continuous approximation register, the input system thereof a frequency comparison circuit is coupled, the output of which is coupled to the injection-locked oscillator, the continuous approximation register receiving an integer multiple of the reference clock signal and a frequency difference of the reference clock signal, and using the reference clock signal The integer multiple of the signal and the frequency difference of the reference clock signal are digitally corrected so that the output falls within an integer multiple of the reference clock signal Frequency output.