TWI499217B - Prescaler of divide-by-7 with a high division-ratio and phase-locked loop system using the same - Google Patents

Description

High divisor division 7 pre-discharger and phase-locked loop system using the high divisor division 7 pre-discharger

The invention relates to the technical field of a phase-locked loop, in particular to a high divisor division 7 pre-discharger and a phase-locked loop system using the high divisor division and 7 pre-discharger.

The frequency spectrum from 1 to 6 GHz accommodates current wireless standards and most applications. Low-cost radio frequency (RF) components and sophisticated integrated circuit (IC) technology have led to the rapid development of wireless receive/transmit systems.

In most wireless receive/transmit systems, the phase-locked loop is an important component. In the wireless receiving/transmitting system, designing a wide range of adaptive phase-locked loops such as TV receivers and WiMax receivers is a daunting challenge. For each output frequency of the phase-locked loop, the parameters of the phase-locked loop (eg, the frequency of the input signal, the multiplication factor, etc.) must be precisely adjusted to minimize phase noise and maintain the stability of the phase-locked loop.

1 is a block diagram of a conventional phase-locked loop 100, including a phase detector (Detect Detector) 110, a charge pump 120, a filter 130, a voltage controlled oscillator (VCO) 140, and a Frequency dividing device 150. When the phase locked loop 100 is locked, the frequency of the signal CK _OUT generated by the phase locked loop 100 is N times the frequency of the reference signal CK _REF .

Phase-locked loop 100 often operates at different frequencies. When the operating frequency exceeds the GHz frequency, the frequency dividing device 150 is generally divided into a first stage pre-processor 151 and a rear stage frequency divider 153. The voltage controlled oscillator and the first stage prescaler are called The front end of the phase-locked loop 100 is the most challenging component because it operates at the highest frequency.

The pre-processor can be divided into digital, analog, and mixed digits and analogs. The digital type can be further divided into a static frequency divider (SFD) and a dynamic frequency divider (DFD). The mixed digit and analogy are the traveling wave frequency divider. The analogy can be divided into a regenerative frequency divider and an injection locked frequency divider (ILFD).

In the phase-locked loop, the pre-discharger is the first stage of the frequency division device. When the frequency of the output signal of the phase-locked loop is low, the design of the pre-processor is quite straightforward and simple. However, when the frequency of the output signal of the phase-locked loop exceeds GHz, even up to 60 GHz, the pre-discharger typically uses an injection-locked frequency divider (ILFD). In the application of millimeter wave (mm-wave), there are two pre-dividers and three pre-dividers. However, due to the lower divisor, the output frequency is still high. For example, in a 60 GHz application, the frequency of the output signal of a divide-by-2 pre-divider is still as high as 30 GHz, which increases the design difficulty of the rear-stage frequency divider 153. Accordingly, the present invention provides a high divisor divide-by-seven pre-discharger and a phase-locked loop system using the high divisor divide-by-seven pre-discharger.

The main object of the present invention is to provide a high divisor division 7 pre-discharger and a phase-locked loop system using the high divisor division and 7 pre-discharger, which can reach a lower frequency band faster, thereby reducing the use of the overall circuit. Frequency divider stage, but also due to As the number of stages of the frequency divider is reduced, the circuit complexity can be reduced, and any coupling noise that may be fed into the circuit via the supply voltage terminal can be reduced, and the locked frequency range can be effectively increased.

According to a feature of the present invention, the present invention provides a high divisor divide-by-seven pre-discharger comprising an injection transistor group, a ring oscillator, and an output buffer stage circuit. The injection transistor group mixes an injection signal into a high frequency signal and a low frequency signal. The ring oscillator is coupled to the injection transistor group to retain the low frequency signal while suppressing the high frequency signal. The output buffer stage circuit is coupled to the ring oscillator to gradually increase the energy of the low frequency signal to generate a frequency division signal, wherein the frequency of the injection signal is 7 times the frequency of the frequency division signal.

According to another feature of the present invention, the present invention provides a phase locked loop system including a detector, a charge pump, a filter, a controllable oscillator, a high divisor division 7 prescaler, and a divide Frequency device. The detector generates a detection signal according to the difference between the logic level values of an input signal and a feedback signal. The charge pump is coupled to the detector to generate a control signal based on the detection signal. The filter is coupled to the charge pump to generate an adjustment signal based on the control signal. The controllable oscillator is coupled to the filter to generate a differential output signal based on the adjusted signal. The high divisor divide-by-seven preprocessor is coupled to the controllable oscillator for dividing the differential output signal to generate a divisor signal. The frequency dividing device is coupled to the high divisor dividing 7 pre-divider to generate the feedback signal according to the frequency dividing signal.

2 is a block diagram of a phase locked loop system 200 of the present invention, including a detector 210, a charge pump 220, a filter 230, a controllable oscillator 240, a high divisor divide and 7 prescaler 250, And a frequency dividing device 260.

The detector 210 generates a detection signal UP, DN according to the difference between the logic level values of an input signal CK _REF and a feedback signal CK _FB .

The charge pump 220 is coupled to the detector 210 to generate a control signal Vctrl according to the detection signals UP and DN.

The filter 230 is coupled to the charge pump 220 to generate an adjustment signal Vfilter according to the control signal Vctrl.

The controllable oscillator 240 is coupled to the filter 230 to generate a differential output signal CK _OUT+ , CK _OUT- according to the adjustment signal Vfilter. The frequency of the differential output signals CK _OUT+ and CK _OUT- is 24 GHz.

The high-divide divide-by-seven pre- _discharger 250 is coupled to the controllable oscillator 240 for dividing the differential output signals CK _OUT+ and CK _OUT- to generate a frequency-divided signal CK _DIV7+ , CK _DIV7- .

The frequency dividing device 260 is coupled to the high divisor dividing and dividing unit 250 to generate the feedback signal CK _FB according to the frequency dividing signal. The frequency dividing device 260 is composed of a first stage divide by 2 frequency divider 261, a second stage divide by 2 frequency divider 263, and a divide by 3 frequency divider 265. The frequency of the input signal CK _REF and the feedback signal CK _FB is 287 MHz.

3A and 3B are circuit diagrams of a high divisor division 7 pre-discharger 250 of the present invention. The high divisor division 7 pre-discharger 250 includes an injection transistor group 310, a ring oscillator 320, and an output buffer. Stage circuit 330.

The injection transistor group 310 mixes an injection signal Vin into a high frequency signal and a low frequency signal.

The ring oscillator 320 is coupled to the injection transistor group 310 to retain the low frequency signal while suppressing the high frequency signal.

The output buffer stage circuit 330 is coupled to the ring oscillator 320 to gradually increase the energy of the low frequency signal retained to generate a divisor signal Voutp, Voutn. The frequency of the injection signal Vin is 7 times the frequency of the frequency-divided signals Voutp and Voutn.

The injection type transistor group 310 is composed of a first to seventh transistors M1-M7. The gates of the first to seventh transistors M1-M7 are both connected to a node A, the source of the first transistor M1 is connected to the drain of the seventh transistor M7, and the first transistor M1 The drain is connected to the source of the second transistor M2. The connection of other transistors can be referred to the drawings. For those skilled in the art, the connection manner can be understood based on the drawings of the present invention, and details are not described herein again.

The ring oscillator 320 is a low pass filter and is composed of a seven-stage inverter consisting of an eighth to twenty-first transistor M8-M21.

The high divisor division 7 pre-divider 250 is based on a seven-stage ring oscillator, and is mainly divided into the ring oscillator 320 composed of the injection transistor group 310 and a seven-stage inverter. The injection transistor group 310 can be regarded as a mixer architecture, and the injection signal Vin is mixed into high and low frequencies. The injection signal Vin can be one of the differential output signals CK _OUT+ and CK _OUT- of the controllable oscillator 240, or the differential output signals CK _OUT+ and CK _{OUT- can be} converted to a single-ended signal by the differential signal. After the single-ended signal.

Then, low-pass filtering is performed through the ring oscillator 320 to preserve the low-frequency term while the high-frequency term is suppressed. Because the ring oscillator 320 utilizes the phase offset and is divided into different phases according to the number of stages, the advantage is that the frequency lock range can be increased, and all the oscillation frequencies of the controllable oscillator 240 of the previous stage can be successfully divided. At the same time, the ring oscillator 320 architecture of the invention can effectively solve the problem that the frequency locking range that the frequency divider of the conventional LC-tank architecture encounters in the case of high divisibility is insufficient.

As shown in FIG. 3B, the output buffer stage circuit 330 utilizes the three-stage inverter circuit 331 to gradually increase the output energy. In addition, the output terminal Voutp of the third-stage inverter 331 is connected to one end of the first stage divided by the second frequency divider 261, and the output terminal Voutp is connected to the first-stage inverter 333 and then connected to the first stage. The other end of the 2 frequency divider 261 is input. Although the phase does not exhibit a perfect 180° phase difference due to the circuit delay effect, the delay can be minimized by proper parameter adjustment, and the first stage divide-by-two frequency divider 261 of the next stage can also operate normally. .

4 is a circuit diagram of a conventional single-ended Cobbitz voltage controlled oscillator circuit. The conventional single-ended Cobbitz voltage controlled oscillator circuit is connected to a fixed voltage source Vbias through a gate to determine a bias value of the transistor M410. The method will make the transistor M410 transduction value a fixed value, and its equivalent transduction value is as shown in formula (1): Among them, g _m is the transconductance value of the transistor M410, C ₄₂₀ is the capacitance value of the capacitance C420, C ₄₃₀ is the capacitance value of the capacitance C430, and ω is the frequency of the conventional single-ended Cobbitz voltage controlled oscillator circuit.

Figure 5 is a circuit diagram of a controllable oscillator 240 of the present invention. The controllable oscillator 240 includes a first inductor L1, a second inductor L2, a first variable capacitor Cvar1, a second variable capacitor Cvar2, a third to sixth capacitor C3-C6, and a first Twenty-two to twenty-fifth transistors M22-M25.

The adjustment signal Vfilter generated by the filter 230 is connected to the node B to adjust the frequency of the differential output signals CK _OUT+ and CK _OUT- of the controllable oscillator 240. One end of the first inductor L1 is connected to a high voltage VDD, and the other end is connected to one end of the first variable capacitor Cvar1, one end of the third capacitor C3, the drain of the second twelve transistor M22, and The gate of the twenty-third transistor M22. For the connection of other circuits, reference may be made to the drawings, and the connection manner of the present invention can be understood based on the drawings of the present invention, and details are not described herein again.

6 is a schematic diagram showing a comparison of a conventional single-ended Cobbitz voltage controlled oscillator circuit and a controllable oscillator 240 of the present invention. The controllable oscillator 240 is a transconducting enhanced Colpitts oscillator architecture, the concept of which can be understood by adding an amplifier 610. When an amplifier 610 having a gain of -A is inserted between the gate G and the source S of the transistor M620, the feedback path does not consume additional current, and the transduction value is increased by (1+A) times. In the controllable oscillator 240 circuit of the present invention, the drain D and the source S are in-phase signals and are oscillated by feedback. Therefore, the same effect can be achieved regardless of whether the drain D or the source S is selected as the coupling end, and the drain D is selected as the coupling end in this circuit. In addition, the equivalent transduction value seen by transistor M610 is shown in equation (2):

It can be found from equation (2) that the equivalent transconductance value of the controllable oscillator 240 is more than that of the conventional single-ended Cobbitz voltage controlled oscillator circuit in FIG. Times, it is known that the increase factor A is Therefore, through this transfer promotion mode, the power consumption required to ensure oscillation can be reduced.

7 is a block diagram of a first stage divide by two frequency divider 261 and a second stage divide by two frequency divider 263 of the present invention. The first stage divide by 2 frequency divider 261 and the second stage divide by 2 frequency divider 263 are current mode logic (CML). The first stage divide by two frequency divider 261 and the second stage divide by two frequency dividers 263 are each formed by positive feedback connection of two D-type flip-flops 710.

The differential signals Voutp and Voutn output by the high divisor 7 pre-processor 250 are connected to the timing input terminal clk of the two D-type flip-flops 710, . After the second stage divide/divider 263 divides by 2 to generate the four-phase signal (IP, IN, QP, QN), the second stage divides the second frequency divider 263 to generate the four-phase signal, and finally generates the four-phase signal. Re-injection into the divide-by-three frequency divider 265. The first stage divide by 2 frequency divider 261 of the current mode logic and the second stage divide by 2 frequency divider 263 can utilize the current and the frequency controlled by the load control, so the advantages are: (1) operable higher frequency (2) can remove the four-phase signal, and (3) can tolerate a smaller input swing.

Figure 8 is a circuit diagram of a D-type flip-flop 710 of the present invention. Each of the D-type flip-flops includes the twenty-sixth to thirty-thirdth transistors M26-M33. For the connection of the transistor, reference may be made to the drawings, and the connection manner of the present invention can be understood based on the drawings of the present invention, and details are not described herein again. In FIG. 7, the symbol of the D-type flip-flop 710 is used, so the input D of the D-type flip-flop 710, And output Q, Corresponding to In1n, In1p, Out1n, and Out1p in Fig. 8, respectively.

Figure 9 is a block diagram of a divide-by-three frequency divider 265 of the present invention. The divide-by-three frequency divider 265 is composed of two true single phase clock (TSPC) divide-by-three circuits 910. The divide-by-three frequency divider 265 continuously divides the alternating current signal of the first two stages of the first two stages except the two frequency dividers 261 and the second stage divided by two frequency dividers 263 to a lower frequency, and transmits the feedback. The path and the detector 210 compare the phase frequency errors. Therefore, the divide-by-three frequency divider 265 has a low operating frequency, but has a very low power consumption, and also has a good operating frequency range and performance.

Figure 10 is a circuit diagram of a real single phase clock (TSPC) divide by 3 circuit 910 of the present invention. The True Single Phase Clock (TSPC) divide 3 circuit 910 includes thirty-fourth to forty-seventh transistors M34-M47.

Figure 11 is a circuit diagram of the detector 210 of the present invention. The detector 210 includes forty-eighth to fifty-ninth transistors M48-M59, first to seventh inverters Inv01-Inv07, and a delay chain 1110.

In order to solve the dead zone effect generated by the detector 210, the delay circuit 1110 is incorporated in the circuit. The delay circuit 1110 includes eighth to tenth inverters Inv08-Inv10, and first to second inverse gates Nand1-Nand2. Even when the phase difference between the input signal CK _REF and the feedback signal CK _FB is small, the detection signals UP and DN can be completely charged and discharged, thereby properly controlling the charge pump 220 to be charged and discharged. In addition, the delay circuit 1110 has a CLEAR control signal terminal. At the beginning, the CLEAR signal will be 1, and the circuit will perform a reset operation. Then, after the CLEAR signal becomes 0, the circuit starts to input the signal CK _REF and the feedback signal. Comparison of CK _FB . Since the previous state has been reset, the previous state of the circuit has been cleared to avoid causing a judgment error, which will improve the accuracy of the phase frequency detector detection.

Figure 12 is a circuit diagram of the charge pump 220 of the present invention. The charge pump 220 includes sixty to seventy-third transistors M60-M73, and an error amplifier 1210.

The charge pump 220 plays an important role in the phase-locked loop system 200. When the currents of the detection signals UP and DN are mismatched, jitter is generated, and the filter 230 is converted into voltage jitter through the next stage of the filter 230, thereby causing noise. The controllable oscillator 240 is affected such that the phase noise of the controllable oscillator 240 is reduced while the entire phase locked loop system 200 is added.

The reason why this phenomenon occurs is the channel length modulation (CLM) relationship of the transistor in the charge pump 220. Therefore, the charge pump 220 selects a current steering charge pump circuit. . Under the original current-operated charge pump circuit architecture, the use of the error amplifier 1210 can solve the UP-DN current mismatch problem, thereby reducing the jitter caused by the offset charge. During the rapid opening and closing of the charge pump 220, the generated leakage charge may affect the control signal Vctrl through the path, causing the voltage jitter mentioned above, and reducing the phase noise of the controllable oscillator 240. . for To solve the mismatch effect, the circuit is slightly improved. Two NMOS transistors M60 and M61 and two PMOS transistors M72 and M73 are added to the circuit as capacitors. When the switch is open, the generated leakage charge is stored in the added capacitor, and when stored, the stored charge is released again, thereby reducing the influence of the leakage charge.

Figure 13 is a circuit diagram of an error amplifier 1210 of the present invention. The error amplifier 1210 includes seventy-fourth to eighty-seventh transistors M74-M87.

Figure 14 is a circuit diagram of a filter 230 of the present invention, which is a low pass filter. The low pass filter 230 includes a first resistor R1, a first capacitor C1, and a second capacitor C2. The loop width of the low pass filter 230 is 3 MHz, the charge and discharge current is 65 μA, the KVCO is 2.833 GHz/V, and the phase margin (PM) is 66°, and the first resistor R1 can be calculated as 21.477 kΩ, the first capacitor C1 is 10.385 pF, and the second capacitor C2 is 0.4914 pF.

Figure 15 is a schematic illustration of a transient simulation of a phase locked loop system 200 of the present invention. As shown in Figure 15, where the lock time is approximately 800 ns, the corresponding lock voltage is approximately 0.81 V. Figure 16 is a schematic illustration of the simulated parameters and results of the phase locked loop system 200 of the present invention.

17 is a circuit diagram of a conventional LC-tank oscillator. As shown in FIG. 17, the frequency division concept is a common mode point at the center Vcm, and is suppressed by an inductor and a capacitor. 2nd order harmonic term filter, which can be used to mix 4th order high frequency harmonic terms and injection signals The frequency division function can be achieved by using an inductor-capacitor resonant base voltage controlled oscillator with an equivalent bandpass filter.

Figure 18 is a graphical representation of a comparison of the maximum lock frequency range of the high divisor divide-by-seven pre-discharger 250 of the present invention and the pre-discharger of Figure 17. As can be seen from the results of Fig. 18, the high divisor division 7 pre-discharger 250 of the present invention has a large frequency locking range regardless of the injection power of 1.5 dBm or 3 dBm. This is the core technology of the present invention and is also the greatest improvement of the present invention. In view of process variation, the high divisor division 7 pre-remover 250 of the present invention can ensure the correct operation of the overall phase-locked loop. In the 24 GHz phase-locked loop system, the injected power comes from the output power of the previous stage controllable oscillator 240, which is 3 dBm. Therefore, the maximum frequency locking range is 1.8 GHz, and the circuit bias point is 0.34. V.

The present invention can achieve a lower frequency band faster by using a higher divisor division 7 pre-divider 250 using a higher divisor, thereby reducing the use of the overall circuit. The number of divider stages; because the number of stages of the divider is reduced, circuit complexity can be reduced while reducing any coupling noise that may be fed into the circuit via the supply voltage terminal. In addition, the injection-locked frequency divider of the Ring-oscillator-based architecture used in the present technology can effectively increase the locked frequency range compared with the traditional frequency divider using the LC-tank-oscillator-based architecture.

From the above, it can be seen that the present invention is extremely useful in terms of its purpose, means, and efficacy, both of which are different from those of the prior art. It should be noted that the above various embodiments are merely examples for convenience of explanation. The scope of the claims is intended to be limited only by the scope of the claims.

100‧‧‧ phase-locked loop

110‧‧‧ phase detector

120‧‧‧Charge pump

130‧‧‧ Filter

140‧‧‧Voltage Controlled Oscillator

150‧‧‧Dividing device

151‧‧‧First stage pre-processor

153‧‧‧ Rear section frequency divider

200‧‧‧ phase-locked loop system

210‧‧‧Detector

220‧‧‧Charge pump

230‧‧‧ filter

240‧‧‧Controllable Oscillator

250‧‧‧High Divisor Division 7 Prescaler

260‧‧‧frequency divider

261‧‧‧First stage divide by 2 frequency divider

263‧‧‧Second stage divide by 2 frequency divider

265‧‧‧ except 3 frequency divider

310‧‧‧Injected transistor group

320‧‧‧Ring Oscillator

330‧‧‧Output buffer stage circuit

M1-M7‧‧‧first to seventh transistors

M8-M21‧‧‧ eighth to twenty-first crystal

M410‧‧‧O crystal

C420‧‧‧ capacitor

Vbias‧‧‧ fixed voltage source

L1‧‧‧first inductance

L2‧‧‧second inductance

Cvar1‧‧‧first variable capacitor

Cvar2‧‧‧Second variable capacitor

C3-C6‧‧‧ third to sixth capacitor

M22-M25‧‧‧22nd to 25th crystal

610‧‧Amplifier

M620‧‧‧O crystal

710‧‧‧D type flip-flop

M26-M33‧‧‧Twenty-sixth to thirty-third crystals

910‧‧‧Real single phase clock divided by 3 circuits

M34-M47‧‧‧Thirteenth to forty-seventh transistor

M48-M59‧‧‧48th to 59th Crystal

Inv01-Inv07‧‧‧First to Seventh Inverters

1110‧‧‧Delay circuit

Inv08-Inv10‧‧‧ eighth to tenth inverter

Nand1-Nand2‧‧‧first to second reverse gates

M60-M73‧‧‧60 to 73 crystal

1210‧‧‧Error amplifier

M74-M87‧‧‧ Seventy-fourth to eighty-seventh crystal

R1‧‧‧first resistance

C‧‧‧first capacitor

C2‧‧‧second capacitor

Figure 1 is a block diagram of a conventional phase-locked loop.

2 is a block diagram of a phase locked loop system of the present invention.

3A and 3B are circuit diagrams of the high divisor division 7 pre-discharger of the present invention.

Figure 4 is a circuit diagram of a conventional single-ended Cobbitz voltage controlled oscillator circuit.

Figure 5 is a circuit diagram of a controllable oscillator of the present invention.

6 is a schematic diagram showing a comparison between a conventional single-ended Cobbitz voltage controlled oscillator circuit and a controllable oscillator of the present invention.

Figure 7 is a block diagram of a first stage divide by two frequency divider and a second stage divide by two frequency divider of the present invention.

Figure 8 is a circuit diagram of a D-type flip-flop of the present invention.

Figure 9 is a block diagram of a divide-by-three frequency divider of the present invention.

Figure 10 is a circuit diagram of a true single phase clock division 3 circuit of the present invention.

Figure 11 is a circuit diagram of the detector of the present invention.

Figure 12 is a circuit diagram of the charge pump of the present invention.

Figure 13 is a circuit diagram of the error amplifier of the present invention.

Figure 14 is a circuit diagram of a filter of the present invention.

Figure 15 is a schematic illustration of a transient simulation of a phase locked loop system of the present invention.

Figure 16 is a schematic illustration of simulation parameters and results of a phase locked loop system of the present invention.

Figure 17 is a circuit diagram of a conventional inductor-capacitor resonator oscillator.

Figure 18 is a graphical representation of a comparison of the maximum lock frequency range of the high divisor divide-by-seven pre-discharger of the present invention and the pre-discharger of Figure 17.

200‧‧‧ phase-locked loop system

210‧‧‧Detector

220‧‧‧Charge pump

230‧‧‧ filter

240‧‧‧Controllable Oscillator

250‧‧‧High Divisor Division 7 Prescaler

260‧‧‧frequency divider

261‧‧‧First stage divide by 2 frequency divider

263‧‧‧Second stage divide by 2 frequency divider

265‧‧‧ except 3 frequency divider

Claims (11)

A high divisor divide-by-seven pre-discharger includes: an injection-type transistor group for mixing an injection signal into a high-frequency signal and a low-frequency signal; and a ring oscillator connected to the injection-type transistor group, The low frequency signal simultaneously suppresses the high frequency signal, the ring oscillator is composed of a seven-stage inverter; and an output buffer stage circuit is connected to the ring oscillator to gradually increase the energy of the low frequency signal The output buffer circuit is composed of a three-stage inverter circuit; wherein the frequency of the injected signal is 7 times the frequency of the frequency-divided signal. The high divisor division 7 pre-discharger according to claim 1, wherein the injection type transistor group is composed of a first to seventh transistors. The high divisor division 7 pre-discharger according to claim 2, wherein the ring oscillator is composed of an eighth to twenty-first transistor. A phase-locked loop system includes: a detector that generates a detection signal according to a difference between a logic level value of an input signal and a feedback signal; and a charge pump coupled to the detector to detect the detector The signal generates a control signal; a filter is coupled to the charge pump to generate an adjustment signal according to the control signal, the filter is a low pass filter, the low pass filter includes a first resistor, a first capacitor and a second capacitor; a controllable oscillator coupled to the filter to generate a differential output signal according to the adjustment signal; a high divisor division 7 pre-distributor coupled to the controllable oscillator for The differential output signal is frequency-divided to generate a frequency-divided signal; and a frequency-dividing device is coupled to the high-division-splitting and 7-splitter to generate the feedback signal according to the frequency-divided signal, and the frequency-dividing device is A first stage divides the 2 frequency divider, a second stage divides the 2 frequency divider, and a divide by 3 frequency divider. The phase-locked loop system of claim 4, wherein the differential output signal has a frequency of 24 GHz, and the input signal and the feedback signal have a frequency of 287 MHz. The phase-locked loop system of claim 5, wherein the high divisor-by-seven pre-discharger comprises an injection-type transistor group, a ring oscillator, and an output buffer stage circuit. The phase-locked loop system of claim 6, wherein the injection-type transistor group is composed of a first to seventh transistors, and the ring oscillator is an eighth to a twenty-first The crystal is composed of. The phase-locked loop system of claim 7, wherein the controllable oscillator comprises a first inductor, a second inductor, a first variable capacitor, a second variable capacitor, and a first phase Three to six capacitors, and one twenty-second to twenty-fifth transistor. The phase-locked loop system of claim 8, wherein the first-stage divide-by-2 divider and the second-stage divide-by-2 divider are provided by two D-type flip-flops as positive feedback links. Made. The phase-locked loop system of claim 9, wherein each of the D-type flip-flops comprises a twenty-sixth to thirty-thirdth transistor. The phase-locked loop system of claim 10, wherein the divide-by-three frequency divider is composed of two true single-phase clock division and three circuits.