TWI517362B - Semiconductor structure - Google Patents

Description

Semiconductor structure

This invention relates to a semiconductor structure, and more particularly to a semiconductor structure for a memory device including a ground line and a bit line.

In a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the body end (Body or Substrate) is usually the same as the source (Source), source-substrate junction (source-body) The junction) voltage is zero.

However, component design may result in situations where the base end is not directly connected to the source terminal. As a result, the extra load on the line causes the source terminal to generate a bias voltage V _S , which in turn changes the threshold voltage (V _T ) of the transistor. This effect is called the body effect.

When multiple transistors are connected in series (for example, a plurality of bit lines connected in series in a memory device), the accumulated matrix effect causes a considerable change in the V _{T of the} transistor, changing the circuit characteristics. Therefore, eliminating the matrix effect is quite necessary for the semiconductor process. A typical flash memory device will be designed with a metal ground wire to reduce the matrix effect. However, the grounding wire of the prior art is larger than the bit line, which not only occupies a lot of space, but also the bit line adjacent to the grounding wire is susceptible to the loading effect or coupling effect of the surrounding circuit. To change the electrical properties, it must be designed as a dummy line to increase costs.

The present invention relates to a semiconductor structure having a specific bit line and ground line configuration, which can reduce the footprint of the ground line while maintaining good electrical properties of the device.

According to an aspect of the invention, a semiconductor structure is proposed comprising a plurality of stacked blocks and a plurality of conductive lines. The stacked blocks are arranged in parallel and successively, and each stacked block is composed of two opposite finger vertical gate structures. The finger vertical gate structure comprises a stepped structure and a plurality of bit line stacks, the stepped structure is perpendicular to the bit line stack, and the bit lines of the opposite two finger vertical gate structures are staggered. The conductive lines are spaced above the stacked block and extend in a direction perpendicular to the bit line stack. The conductive line includes a plurality of bit lines and a plurality of ground lines, and each of the stacked blocks includes at least one ground line.

According to another aspect of the present invention, a semiconductor structure is proposed comprising a substrate, a plurality of memory cells, and a plurality of conductive lines. The memory cells are located on the substrate and are arranged in a matrix. The conductive line is located above the memory unit, and the plurality of conductive lines are parallel to each other and spaced apart by the same distance. The conductive wire is electrically connected to the memory unit, and includes a plurality of bit lines and a plurality of ground lines.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

1, 4‧‧‧ semiconductor structure

102B, 103B, 104B, 105B, 112A, 113A, 114A, 115A‧‧‧ stepped structure

102C‧‧‧Contact area

119‧‧‧String selection line gate structure

125-1,...,125-N‧‧‧word line

126, 127‧‧ ‧ gate selection line

128‧‧‧ source line

131‧‧‧ bit line stacking

140‧‧‧Source contact

150‧‧‧through hole

2‧‧‧ finger vertical gate structure

200‧‧‧ bit line

3‧‧‧Stacking blocks

300‧‧‧ Grounding wire

ML1‧‧‧ first metal layer

ML2-1, ML2-2‧‧‧ second metal layer

ML3-1,...ML3-10‧‧‧ third metal layer

1A is a schematic view showing a semiconductor structure according to an embodiment of the present invention, and FIG. 1B is a schematic side view showing the semiconductor structure of FIG. 1A.

2A to 2D are schematic views showing a manufacturing process of a semiconductor structure according to an embodiment of the present invention, and FIG. 2D is a schematic view showing a semiconductor structure according to an embodiment of the present invention.

3 is a simplified schematic diagram of a semiconductor structure in accordance with an embodiment of the present invention.

Embodiments of the present invention will be described in detail below with reference to the drawings. The same reference numerals are used to designate the same or similar parts. It is to be noted that the drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn to the scale of the actual products, and thus are not intended to limit the scope of the present invention.

Please refer to FIGS. 1A and 1B. FIG. 1A is a schematic view showing a semiconductor structure according to an embodiment of the present invention, and FIG. 1B is a side view of the semiconductor structure of FIG. 1A. The semiconductor structure 1 shown in FIG. 1A is a three-dimensional anti-NAND (NAND) gate flash memory device, which adopts a finger vertical gate (Finger VG) design. The contents of the finger-shaped vertical gate structure are described in detail in the U.S. Patent Nos. 8,503,213 and 8,383,512, both to the same applicant and the inventor, which are hereby incorporated by reference. The semiconductor structure 1 in Figs. 1A and 1B ignores part of the insulating material to show an additional structure. For example, The insulating layers between the semiconductor stripes, in the ridge stack, and between the ridge stacks of semiconductor stripes are removed.

As shown in FIGS. 1A and 1B, a multilayer array is formed over the insulating layer and includes a plurality of word lines 125-1, . . ., 125-N conformal to the plurality of bit line stacks. The plurality of bit line stacks include semiconductor stripes 112, 113, 114, and 115. The semiconductor stripes in the same plane are electrically connected to the stepped structures 112A, 113A, 114A, 115A, 102B, 103B, 104B, 105B.

The stepped structures 112A, 113A, 114A, 115A terminate the semiconductor stripes 112, 113, 114, 115; the stepped structures 102B, 103B, 104B, 105B terminate the semiconductor stripes 102, 103, 104, 105. As shown, the stepped structures 112A, 113A, 114A, 115A, 102B, 103B, 104B, 105B are electrically coupled to different bit lines for connection to the decoding circuitry to select a plane in the array.

The bit line stack formed by the semiconductor stripes is coupled to the stepped structures 112A, 113A, 114A, 115A or the stepped structures 102B, 103B, 104B, 105B, but only one of them is coupled, and the two are not coupled at the same time.

The bit line stack formed by the semiconductor stripes 112, 113, 114, 115 is terminated at one end by the stepped structures 112A, 113A, 114A, 115A, and the line select gate 119, the gate select line 126, and the word line are passed through the string. 125-1 to 125-N, gate select line 127, and terminate at the other end by source line 128. The bit line stack formed by the semiconductor stripes 112, 113, 114, 115 does not reach the stepped structures 102B, 103B, 104B, 105B.

Similarly, the bit line stack formed by the semiconductor stripes 102, 103, 104, 105 terminates at one end by the stepped structures 102B, 103B, 104B, 105B, and passes through the string selection line gate structure 109 and the gate selection line 127. , word line 125-N to 125-1, gate selection line 126 is terminated by the source line 128 at the other end (Fig. 1B). The bit line stack formed by the semiconductor stripes 102, 103, 104, 105 does not reach the stepped structures 112A, 113A, 114A, 115A.

The first metal layer ML1, the second metal layer ML2, and the third metal layer ML3 are electrically conductive materials, and are formed as conductive lines on the semiconductor stripes and the array of word lines 125-1 to 124-N. The second metal layer ML2 includes two source lines (corresponding to portions of the source line 128) whose direction is parallel to the word line (y-axis). The third metal layer ML3 includes a bit line and a ground line, the direction of which is parallel to the stripe of the semiconductor material (x-axis). In the example of FIGS. 1A and 1B, the semiconductor structure has five third metal layers ML3, which are sequentially numbered ML3-1 to ML3-5. For example, the third metal layer closest to the right side in FIG. 1A is ML3-1. The third metal layer closest to the left side is ML3-5. ML3-1~ML3-4 are used as bit lines, and are electrically connected to the steps of different stepped structures 112A, 113A, 114A, 115A and 102B, 103B, 104B, and 105B. The bit lines ML3-1~ML3-4 enable the bit line signals to select a particular semiconductor stripe plane. The ML3-5 is not connected to the stepped structures 112A, 113A, 114A, 115A or 102B, 103B, 104B, 105B, but is connected to the semiconductor stripes 112, 113, 114, 115 through the source line 128. The bit lines are stacked. In this example, the third metal layer ML3 has the same size and spacing, and can be formed simultaneously in a single yellow light process, and only the connection relationship defines which bit line (ML3-1~ML3-4), which is grounded. Line (ML3-5).

2A to 2D are diagrams showing a method of fabricating a semiconductor structure according to an embodiment of the present invention. The semiconductor structure 4 of this embodiment is a side-by-side arrangement of two semiconductor structures 1 shown in FIGS. 1A and 1B. For convenience of explanation, only A top view of the semiconductor structure is shown. This semiconductor structure can significantly reduce the space occupied by the ground line, but still maintain a low substrate effect.

As shown in FIG. 2A, the semiconductor structure includes two sets of stacked blocks that are successively arranged. 3 (stacking block). The stacking block 3 is the portion of the broken line frame A of FIG. 1B, that is, the semiconductor structure 1 removes the remaining portions of the metal layers ML1 to ML3. The stacking block 3 shown in FIG. 2A further removes the structure in the y-axis direction such as the word lines 125-1 to 121-N for convenience of explanation.

Referring also to FIGS. 1B and 2A, the finger vertical gate structure 2 (Finger VG) is a stepped structure (only the topmost stepped structure 102B is shown in the upper view of FIG. 2A) and a plurality of bits. The line stack 131 is constructed. The orientation of the stepped structure 102B is the y-axis, and the orientation of the bit line stack is the x-axis, which are perpendicular to each other. The stepped structure 102B has a plurality of contact regions 102C. The number of contact regions 102C is the same as the number of bit line stacks 131, and the pitch of the contact regions 102C is also the same as the pitch of the bit line stacks. Here, the four-bit line stack 131 is taken as an example, but the number of upper bit line stacks can be freely changed. The shape of the stepped structure 102B is similar to that of the palm of the hand, and the bit line stack 131 is similar to a finger, so such a structure is referred to as a finger-shaped vertical gate structure (Finger VG). The end of the bit line stack 131 (similar to the fingertip portion) has a source contact 140. The two finger-shaped vertical gate structures 2 are disposed opposite each other such that the bit line stacks 131 are staggered to form the stacked blocks 3 shown in FIGS. 1B and 2A.

As shown in FIG. 2A, since the stacking block 3 is formed by interdigitating two finger-shaped vertical gate structures 2, if the single finger-shaped gate structure has a distance of 2F between the contact regions 102C (the initial pitch of the bit line stack 131) Then, the pitch of the bit line stack 131 in the stack block 3 after the interleaving becomes F, which is reduced by half. In other words, in the case where the distance between the contact regions 102C is constant, the Finger VG structure in which the finger portions are interdigitated with each other can reduce the spacing between the bit line stacks 131, and the precision of the process can be reduced. In one embodiment, the pitch 2F of the contact regions 102C may be equal to or less than 75 nanometers (nm). Each bit line stack can be used as a memory unit, and a 0 or 1 signal can be applied when a voltage is applied. In addition, if the storage capacity of the semiconductor structure 4 is to be increased, a plurality of stacked blocks 3 may be connected in series. Can increase the number of memory cells.

Next, as shown in FIG. 2B, the second metal layer ML2 is formed over the source contact 140. The orientation of the second metal layer is the y-axis, and the bits stacked with the bit lines are perpendicular to the x-axis. The second metal layer ML2 is electrically connected to the source contact 140 of the bit line stack 131 and serves as a source line. In this example, two second metal layers ML2-1 and ML2-2 (corresponding to the second metal layer ML2 above the source line 128 in FIG. 1B) are included, and the ML2-1 connection is located in the lower half of FIG. 2B. The bit line is stacked; the ML2-2 is connected to the bit line stack located in the upper half of the 2B picture.

Further, as shown in FIG. 2C, an additional through hole 150 is formed on the second metal layer ML2 as the source line. The via 150 extends through the second metal layer ML2 to expose the bit line stack 131 under the second metal layer. In detail, the via 150 exposes each of the semiconductor stripes in the bit line stack 131 (refer to 102, 103, 104, 105, 112, 113, 114, 114 of FIGS. 1A and 1B).

Finally, as shown in FIG. 2D, a plurality of third metal layers ML3-1 to ML3-10 are formed over the semiconductor structure, and the semiconductor structure 4 described in this embodiment is completed. The bit direction of the third metal layer ML3-X is the x-axis, which is the same as the bit direction of the bit line stack 131, and is perpendicular to the bit of the second metal layer ML2 toward the y-axis. The material of the third metal layer ML3 is a conductive material and can be used as a bit line and a ground line of the semiconductor structure 4. In FIG. 2D, the third metal layers ML3-1 to ML3-4 and ML3-6 to ML3-9 coupled to the contact region 102C of the finger vertical gate structure 2 are used as the bit lines of the semiconductor structure 4; The third metal layers ML3-5, ML3-10 coupled to the vias 150 on the second metal layer ML2 serve as ground lines for the semiconductor structure. In this embodiment, the four bit lines in each set of stacked blocks 3 share a single ground line. Such a design ensures that each set of stacked blocks 3 has at least one ground line, reducing the matrix effect.

In the semiconductor structure 4 shown in FIG. 2D, the ground line is formed simultaneously with the bit lines and has the same width and pitch, so that the ground line occupies only a small space of the semiconductor structure 4. Compared with the large grounding wire design of a typical 2D NAND, in this embodiment, by dispersing a large grounding wire into a plurality of small grounding wires, the grounding wire and the bitline can be simultaneously formed in one process, and the grounding wire is occupied. Space not only speeds up the process time, but also reduces costs. What's more, since the size and spacing of the grounding wire and the bitline are the same, the electrical properties of the bitline adjacent to the grounding wire are not easily affected by factors such as the loading effect, so it is not necessary to design at the edge of the grounding wire. Additional dummy line.

It should be noted that, in this embodiment, the third metal layer ML3 originally used as the bit line is not used as the ground line, but a new ground line is added through the line design. For example, when the external grounding wire is not designed, one stacking block 3 has only four third metal layers ML3 (for example, ML3-1~ML3-4 of FIG. 1A and FIG. 2D) with a pitch of 2F. The ground line added in the 2D diagram will slightly reduce the pitch of the third metal layer ML3, for example, to become 8/5F (2*4/5). The pitch of the third metal layer ML3 can be changed by adjusting the position of the contact region 102C.

In addition, in the embodiments of the above 2A to 2D, the three-dimensional memory device of the finger vertical gate structure (Finger VG) is taken as an example, but the present invention is not limited thereto, and the above disclosed semiconductor structure can also Applied to other 2D or 3D memory devices.

3 is a simplified embodiment of a semiconductor structure in accordance with the present invention, including a substrate (not shown) and memory cells (not shown) arranged in a matrix. A plurality of bit lines 200 and ground lines 300 are arranged on the memory unit. The number of the bit lines 200 is greater than the number of the ground lines 300, that is, the plurality of bit lines 200 share a single ground line 300. In this embodiment, the eight bit lines 200 share a ground line as an example, and the practical application is Can be adjusted according to needs. In one embodiment, the bit line The ratio to the ground line is equal to or less than 128, meaning that up to 128 bit lines can share a single ground line.

In addition, in FIG. 3, the pitch between the adjacent bit lines 200 or between the bit lines 200 and the ground line 300 is equal. This design can be used for semiconductor structures with a pitch of 75 nm or less.

The semiconductor structure of the above embodiment can reduce the substrate effect by allowing a plurality of bit lines to share a ground line, so that the element maintains good electrical properties. In addition, the design of the embodiment can also reduce the size occupied by the ground wire, and does not need to design additional blank lines to avoid interference, reduce cost and increase the use area.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

200‧‧‧ bit line

300‧‧‧ Grounding wire

Claims (10)

A semiconductor structure comprising: a plurality of stacking blocks arranged in parallel and successively, each of the stacked blocks being composed of two opposite finger vertical gate structures, each of the finger-shaped vertical gate structures The method includes a stepped structure and a plurality of bit line stacks, the stepped structure is perpendicular to the bit line stacks, and the plurality of bit line stacks of the two finger vertical gate structures are staggered; and a plurality of The conductive lines are arranged on the stacking blocks, and the extending direction of each of the conductive lines is parallel to the stack of the bit lines; wherein the conductive lines comprise a plurality of bit lines and a plurality of ground lines, and the stacking At least one of the grounding wires is included on the block. The semiconductor structure of claim 1, wherein the total number of the conductive lines on each of the stacked blocks is less than or equal to 128. The semiconductor structure of claim 1, wherein the adjacent conductive lines have the same pitch. The semiconductor structure of claim 1, wherein the distance between the conductive lines is the same as the distance between the plurality of bit line stacks and less than or equal to 75 nm. The semiconductor structure of claim 1, wherein each of the bit line stack tails has a source contact, the semiconductor structure further comprising: a plurality of source lines located at the stacked blocks and the conductive lines Between and parallel to the stepped structure, the source lines are electrically connected to the source contacts. A semiconductor structure comprising: a substrate; a plurality of memory cells are disposed on the substrate, the memory cells are arranged in a matrix, and a plurality of conductive lines are located on the memory cells, the conductive wires are parallel to each other and spaced apart by a distance, The conductive wires are electrically connected to the memory cells, and include a plurality of bit lines and a plurality of ground lines. The semiconductor structure of claim 6, wherein the ratio of the bit lines to the number of the ground lines is less than or equal to 128. The semiconductor structure of claim 6, wherein the adjacent conductive lines have the same one of the pitches, the pitch being less than or equal to 75 nm. The semiconductor structure of claim 6, wherein the conductive lines have the same width. The semiconductor structure of claim 6, wherein the ground lines are spaced apart by the same number of the bit lines.