TWI517337B - Metal line structure and manufacturing method for trench - Google Patents

Description

Metal wire structure and groove manufacturing method

The present invention relates to semiconductor devices and process technology, and more particularly to metal wire structures and trench fabrication methods.

As the density of integrated circuits on semiconductor wafers increases, the resolution of the mask used to define the pattern increases, but the resolution of the mask has reached its limit due to the limitation of the wavelength range of the exposure source, unless The wavelength of the exposure light source is reduced downward, otherwise the resolution of the mask cannot meet the requirements of the next generation integrated circuit. In order to solve this problem, it is a common practice today to separate the pattern into two lower resolution masks to separately expose the same layer structure, such as a metal wire structure.

Due to the inevitable alignment error during the exposure process, overlapping areas are provided at the wire joints defined by the two masks, but the overlapping areas are affected by two etchings, which are easily over-etched and cause subsequent processes. And how to improve the lack of such practices is the main purpose of the development of this case.

Accordingly, it is an object of the present invention to provide a metal wire structure for the purpose of improving the absence of conventional means.

Another object of the present invention is to provide a method of making a groove for the purpose of improving the lack of conventional means.

Specifically, a metal wire structure according to an embodiment of the present invention includes a substrate, a target layer, a trench, and a wire. The target layer is located above the substrate; the trench is formed in the target layer, the bottom of the trench has a micro trench and the depth of the micro trench is no more than 50 angstroms; the wire is embedded in the trench.

In an embodiment of the invention, the substrate is a germanium substrate, and the target layer is an ultra low dielectric constant material (ULK).

In an embodiment of the invention, the wire is a gate electrode, and the gate electrode is made of polysilicon or metal.

In an embodiment of the invention, the wire is an interconnect and the interconnect is a copper wire.

In an embodiment of the invention, the micro-groove is located in a region defined by the first reticle and the second reticle.

In an embodiment of the invention, the micro-groove is located in a region that is overlapped by the first reticle and the second reticle and is partially mis-aligned.

In an embodiment of the invention, the wire above the micro-trench belongs to the type I junction, the T-shaped junction, the L-shaped corner, the Π-type junction or the S-shaped corner.

A trench manufacturing method according to an embodiment of the present invention includes the steps of: providing a substrate; sequentially forming a target layer and a plurality of mask layers on the substrate; the multilayer mask layer comprising at least a metal mask layer and a dielectric layer; Forming a first photoresist structure layer over the multilayer mask layer; defining a first photoresist layer by using a first mask to form a first opening; and etching the exposed plurality of mask layers using the first opening After removing the dielectric layer to expose the metal mask layer, removing the first photoresist structure layer; forming a second photoresist structure layer over the multilayer mask layer; defining the second photoresist structure layer by using the second mask Forming a second opening, the second opening partially overlapping the position of the first opening; using the second opening to etch the exposed plurality of mask layers to remove the dielectric layer to expose the metal mask layer, and then removing the second light a resistive structure layer; the metal mask layer is etched using a remaining dielectric layer as a mask to form a third opening; and the exposed target layer is etched using a third opening to complete the trench.

In an embodiment of the invention, the trench fabrication method further comprises the steps of: embedding a wire in the trench.

In an embodiment of the invention, the multi-layer mask layer further includes a buffer layer between the metal mask layer and the target layer.

In an embodiment of the invention, the buffer layer is made of lanthanum oxynitride or boron nitride, the metal mask layer is formed by a titanium nitride/titanium layer, and the dielectric layer is made of tantalum oxide or tantalum nitride. The ruthenium oxynitride, tantalum carbide or tantalum carbonitride is completed, the etching selectivity ratio of the metal mask layer to the buffer layer is greater than 8, and the etching selectivity ratio of the dielectric layer to the metal mask layer is greater than 5.

In an embodiment of the invention, the first photoresist structure layer and the second photoresist structure layer are each completed by three photoresist structures.

In an embodiment of the invention, the thickness of the dielectric layer is between five times the thickness of the metal mask layer and 0.8 times the thickness of the metal mask layer.

In an embodiment of the present invention, the multi-layer mask layer further includes a second dielectric layer and a second metal mask layer, which are located under the metal mask layer, and the trench manufacturing method further includes : etching the exposed second dielectric layer using a third opening to expose the second metal mask layer; and etching the exposed second metal mask layer using the third opening.

The embodiment of the invention improves the process, so that the depth of the micro-grooves does not exceed 50 angstroms and is thus much smaller than the depth of the micro-grooves generated by the conventional means, thereby effectively avoiding the troubles of subsequent processes and improving the lack of conventional means. To achieve the main purpose of developing this case.

Please refer to the first figure, which is a top view of the layout of the inlaid trench structure for highlighting the overlapping area, and the first partial pattern 21 and the second partial pattern 22 are respectively defined by two masks. There is an overlapping area 210 between the two patterns.

Referring again to the second figure (a) (b) (c) (d) (e) (f) (g), which is a preferred embodiment of the present invention for highlighting the two mask overlap regions The schematic diagram of the step flow is described in accordance with the cross-sectional view indicated by the arrow in the first figure.

First, the second figure (a) utilizes a first mask (not shown) for the multilayer mask layer of the yttria layer 33, the titanium nitride/titanium layer 34, and the cap oxide layer 35. A schematic cross-sectional view of the first partial pattern 21 (shown in the first figure) is performed. In this embodiment, the cap oxide layer 35 is removed first but stopped on the titanium nitride/titanium layer 34 to form a pattern. The opening 360 is shown. Then, as shown in the second diagram (b), after the tri-layer photoresist layers 361, 362, and 363 are formed, the photoresist layer 363 is performed by using a second mask (not shown). The definition, and thus the opening 364 similar to the second partial pattern 22 (shown in the first figure) is exposed, and the dashed line in the figure is the overlapping area of the wire joint.

Then, the photoresist layers 361 and 362 are etched by the opening 364 to form an opening 365 as shown in the second figure (c), and then the exposed cap oxide layer 35 is etched, and finally stopped at the titanium nitride/titanium layer. 34, forming an opening 380 as shown in the second figure (d), and then removing the remaining photoresist layer to form an opening 381 as shown in the second figure (e).

Finally, the lower titanium nitride/titanium layer 34 is etched by the opening 381 to stop on the yttrium oxynitride layer 33, thereby forming an opening 382 as shown in the second figure (f), and the bottom of the opening 382 is exposed at this time. The depth of the micro-grooves 383 will be less than 50 angstroms, which is much smaller than the depth of the trenches created by over-etching in conventional means. Then, the opening 382 can be used to fabricate the trench structure 40 and the wire structure 41 of the ultra-low dielectric constant material (ULK) 39 of the lower target layer, and finally complete the structure as shown in the second figure (g). The groove 383 is located in a region defined by the first partial pattern of the first mask and the second partial pattern of the second mask, even if the first mask is as shown in the second diagram (h) When the second mask overlap is defined, the first partial pattern 91 and the second partial pattern 92 are partially mis-aligned. However, because the depth of the micro-grooves 383 is small, it can effectively avoid the troubles of subsequent processes, thereby improving the lack of conventional means and achieving the main purpose of developing the case.

In order to further reduce the depth of the micro trench 383, the titanium nitride/titanium layer 34 and the cap oxide layer 35 may be repeatedly deposited, so that the multilayer mask layer includes the original titanium/titanium layer 34 and The second oxidized layer 421 composed of titanium nitride/titanium and the yttria constitute a second dielectric layer 420, which is located below the titanium nitride/titanium layer 34, for example, the third layer. (a)(b)(c), which is continued after the second figure (e), and the third figure (a) shows the use of the opening 382 to etch the exposed second dielectric layer 420. And exposing the second metal mask layer 421 as shown in the third figure (b), and then etching the exposed second metal mask layer 421 using the opening 382 as shown in the third figure (c). It stops at the yttria layer 33. Thus, by repeating the high selection ratio etching, the depth of the micro trench 383 can be reduced to a smaller extent, thereby achieving better groove bottom flatness.

The target layer to which the present invention can be applied may be bismuth oxynitride in addition to the above-mentioned ultra-low dielectric constant material (ULK). The completed wire structure 41 may be a gate electrode or an interconnect wire, the gate electrode may be completed by polysilicon or metal, and the interconnect wire may be a copper wire. The overlapping area of the wire joints may be an I-type junction 51, a T-shaped junction 52, an L-shaped corner 53, a 交-shaped junction 54 or an S-shaped corner 55, as shown in the fourth figure. Show. The multilayer mask layer composed of the yttrium oxynitride layer 33, the titanium nitride/titanium layer 34 and the capped yttrium oxide layer 35, wherein the buffer layer formed by the yttrium oxynitride layer 33 is mainly used for buffering The stress, another function of the yttria layer 33 can act as a protective layer to avoid the generation of crater defects in the underlying target layer, and the yttria layer 33 can also be modified by boron nitride. However, the buffer layer can also be completely omitted. The metal mask layer completed by the titanium nitride/titanium layer may also be formed of tantalum nitride, tantalum or other metal, and the dielectric layer formed by the capped yttrium oxide layer 35 may also be made of tantalum nitride, tantalum oxynitride or tantalum carbide. , nitrogen-doped lanthanum carbide or lanthanum oxyhydroxide is completed. In addition, in order to ensure the correct etching, the etching selectivity of the metal mask layer and the buffer layer is controlled to be greater than 8, preferably 9-11, and the etching metal mask layer can be used with chlorine (Cl). For the etching gas of the substrate, the etching selectivity of the dielectric layer and the metal mask layer is controlled to be greater than 5, preferably 6-8, and the etching dielectric layer may be etched with fluorine (F) as the substrate. Gas, such as CxHyFz. Furthermore, in order to ensure that the dielectric layer can still function as a mask after multiple etchings, the thickness of the dielectric layer can be controlled to be less than five times the thickness of the metal mask layer and the metal cover. Between 0.8 times the thickness of the curtain layer, or the thickness of the metal mask layer, the thickness of the dielectric layer, and the thickness of the buffer layer are controlled to be approximately equal, for example, controlled to about 150 angstroms.

twenty one. . . First part pattern

twenty two. . . Second part pattern

210. . . Overlapping area

33. . . Niobium oxynitride layer

34. . . Titanium nitride/titanium layer

35. . . Cover yttrium oxide layer

360, 364, 365, 380, 381, 382. . . Opening

361, 362, 363. . . Photoresist layer

383. . . Micro-groove

39. . . Ultra low dielectric constant material

40. . . Groove structure

41. . . Wire structure

420. . . Second dielectric layer

421. . . Second metal cover layer

51. . . Type I junction

52. . . T-type junction

53. . . L-shaped corner

54. . .交 type junction

55. . . S-shaped corner

The first figure shows a schematic top view of the layout of the overlapping regions required for the copper wire inlay using two masks.

The second figure (a)(b)(c)(d)(e)(f)(g)(h) depicts a schematic flow chart of the method steps of the preferred embodiment of the present invention for highlighting the overlapping regions.

Third (a), (b) and (c) are schematic flow diagrams showing part of the steps of another preferred embodiment of the method for highlighting overlapping regions.

The fourth figure depicts various exemplary diagrams of overlapping regions of wire bonds.

40. . . Trench

41. . . wire

Claims (20)

A metal wire structure comprising: a substrate; a target layer formed by a single structure over the substrate; a trench formed in the target layer, the trench having a micro trench at the bottom, the micro trench The depth is no more than 50 angstroms, wherein the micro-groove is located in the middle of the target layer; and a wire is embedded in the trench. The metal wire structure of claim 1, wherein the substrate is a germanium substrate, and the target layer is an ultra low dielectric constant material (ULK). The metal wire structure of claim 1, wherein the wire is a gate electrode, and the gate electrode is made of polysilicon or metal. The metal wire structure of claim 1, wherein the wire is an interconnecting wire, and the interconnecting wire is a copper wire. The metal wire structure of claim 1, wherein the micro-groove is located in a region defined by a first reticle and a second reticle. The metal wire structure of claim 1, wherein the micro-groove is located in a region where a first mask and a second mask are overlapped and a partial misalignment is generated. The metal wire structure according to claim 5, wherein the wire above the micro groove belongs to a type I junction, a T-shaped junction, an L-shaped corner, A type of junction or S-shaped corner. A trench manufacturing method includes the steps of: providing a substrate; sequentially forming a target layer and a multilayer mask layer over the substrate, the multilayer mask layer comprising at least a metal mask layer and a dielectric layer Forming a first photoresist structure layer over the multilayer mask layer; defining a first photoresist layer by using a first mask to form a first opening; and using the first opening pair to expose the plurality of layers The mask layer is etched to remove the dielectric layer to expose the metal mask layer, and then remove the first photoresist structure layer; a second photoresist structure layer is formed over the multilayer mask layer; The second mask defines the second photoresist structure layer to form a second opening, and the second opening partially overlaps the position of the first opening; and the multilayer mask layer is exposed by using the second opening pair Etching to remove the dielectric layer to expose the metal mask layer, and then removing the second photoresist structure layer; using the remaining dielectric layer as a mask to etch the metal mask layer to form a third Opening; and using the third opening to expose The target layer is etched to complete a groove. The trench manufacturing method of claim 8, wherein the substrate is a germanium substrate, and the target layer is an ultra low dielectric constant material (ULK). The trench manufacturing method of claim 8, further comprising the step of: embedding a wire in the trench. The method of manufacturing a trench according to claim 10, wherein the wire is a gate electrode, and the gate electrode is made of polysilicon or metal. The method of manufacturing a trench according to claim 10, wherein the wire is an interconnecting wire, and the interconnecting wire is a copper wire. The trench manufacturing method of claim 8, wherein the multilayer mask layer further comprises a buffer layer between the metal mask layer and the target layer. The method of manufacturing a trench according to claim 13, wherein the buffer layer is completed by hafnium oxynitride or boron nitride. The trench manufacturing method of claim 14, wherein the metal mask layer is completed by a titanium nitride/titanium layer. The trench manufacturing method according to claim 15, wherein the dielectric layer is made of tantalum oxide, tantalum nitride, niobium oxynitride, tantalum carbide, nitrogen-doped tantalum carbide or tantalum carbonitride. The trench manufacturing method of claim 13, wherein an etching selectivity ratio of the metal mask layer to the buffer layer is greater than 8, and an etching selectivity ratio of the dielectric layer to the metal mask layer is greater than 5 . The trench manufacturing method of claim 8, wherein the first photoresist structure layer and the second photoresist structure layer are each completed by a three-layer photoresist structure layer. The trench manufacturing method of claim 8, wherein the dielectric layer is thick The extent is between five times the thickness of the metal mask layer and 0.8 times the thickness of the metal mask layer. The trench manufacturing method of claim 8, wherein the multilayer mask layer further comprises a second dielectric layer and a second metal mask layer under the metal mask layer, and The method further includes: etching the exposed second dielectric layer using the third opening to expose the second metal mask layer; and etching the exposed second metal mask layer using the third opening.